skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
06/27/2000
Application #:
09234242
Filing Dt:
01/20/1999
Title:
TEST INTERPROSER FOR USE WITH BALL GRID ARRAY PACKAGES ASSEMBLIES AND BALL GRID ARRAY PACKAGES INCLUDING SAME AND METHODS
2
Patent #:
Issue Dt:
02/20/2001
Application #:
09234282
Filing Dt:
01/19/1999
Title:
SPACER PATTERNED, HIGH DIELECTRIC CONSTANT CAPACITOR
3
Patent #:
Issue Dt:
05/07/2002
Application #:
09234430
Filing Dt:
01/20/1999
Title:
SYSTEM FOR CONFIGURING A FLASH MEMORY CARD TO A SELECTED OPERATING MODE BY MONITORING AN UNENCODED SIGNAL FROM A HOST AND AN ENCODED SIGNAL IN THE CARD
4
Patent #:
Issue Dt:
07/18/2000
Application #:
09234942
Filing Dt:
01/21/1999
Title:
METHOD FOR CONTROLLED ERASING MEMORY DEVICES, IN PARTICULAR ANALOG AND MULTI-LEVEL FLASH-EEPROM DEVICES
5
Patent #:
Issue Dt:
02/01/2000
Application #:
09235080
Filing Dt:
01/21/1999
Title:
CIRCUIT AND METHOD FOR READING AND WRITING DATA IN A MEMORY DEVICE
6
Patent #:
Issue Dt:
05/29/2001
Application #:
09235224
Filing Dt:
01/22/1999
Title:
METHOD FOR CONDITIONING A POLISHING PAD USED IN CHEMICAL-MECHANICAL PLANARIZATION OF SEMICONDUCTOR WAFERS
7
Patent #:
Issue Dt:
08/14/2001
Application #:
09235225
Filing Dt:
01/22/1999
Title:
METHOD FOR POST CHEMICAL-MECHANICAL PLANARIZATION CLEANING OF CSEMICONDUCTOR WAFERS
8
Patent #:
Issue Dt:
11/09/1999
Application #:
09235226
Filing Dt:
01/22/1999
Title:
UNDER-PAD FOR CHEMICAL-MECHANICAL PLANARIZATION OF SEMICONDUCTOR WAFERS
9
Patent #:
Issue Dt:
11/07/2000
Application #:
09235227
Filing Dt:
01/22/1999
Title:
CHEMICAL-MECHANICAL PLANARIZATION MACHINE AND METHOD FOR UNIFORMLY PLANARIZING SEMICONDUCTOR WAFERS
10
Patent #:
Issue Dt:
12/14/1999
Application #:
09235468
Filing Dt:
01/22/1999
Title:
SEMICONDUCTOR MEMORY WITH TEST CIRCUIT
11
Patent #:
Issue Dt:
08/28/2001
Application #:
09235568
Filing Dt:
01/22/1999
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY
12
Patent #:
Issue Dt:
08/14/2001
Application #:
09236649
Filing Dt:
01/26/1999
Title:
METHOD AND APPARATUS FOR PROPERLY DISABLING HIGH CURRENT PARTS IN A PARALLEL TEST ENVIRONMENT
13
Patent #:
Issue Dt:
08/14/2001
Application #:
09236761
Filing Dt:
01/25/1999
Title:
ETCH PROCESS FOR ALIGNING A CAPACITOR STRUCTURE AND AN ADJACENT CONTACT CORRIDOR
14
Patent #:
Issue Dt:
07/11/2000
Application #:
09236825
Filing Dt:
01/25/1999
Title:
PROCESS FOR SELECTIVELY ETCHING SILICON NITRIDE IN THE PRESENCE OF SILICON OXIDE
15
Patent #:
Issue Dt:
08/06/2002
Application #:
09237004
Filing Dt:
01/25/1999
Title:
ION-ASSISTED OXIDATION METHODS AND THE RESULTING STRUCTURES
16
Patent #:
Issue Dt:
04/25/2000
Application #:
09237394
Filing Dt:
01/26/1999
Title:
DISPLAY DEVICE WITH GRILLE HAVING GETTER MATERIAL
17
Patent #:
Issue Dt:
03/27/2001
Application #:
09237482
Filing Dt:
01/26/1999
Title:
METHOD OF FORMING SELF-ALIGNED ISOLATED PLUGGED CONTACTS
18
Patent #:
Issue Dt:
03/26/2002
Application #:
09237501
Filing Dt:
01/26/1999
Title:
NON-VOLATILE MEMORY SYSTEM HAVING INTERNAL DATA VERIFICATION TEST MODE
19
Patent #:
Issue Dt:
01/30/2001
Application #:
09237998
Filing Dt:
01/26/1999
Title:
METHOD AND APPARATUS FOR TESTING OF DIELECTRIC DEFECTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
20
Patent #:
Issue Dt:
02/13/2001
Application #:
09238289
Filing Dt:
01/28/1999
Title:
VOLTAGE DIFFERENTIAL SENSING CIRCUIT AND METHODS OF USING SAME
21
Patent #:
Issue Dt:
08/14/2001
Application #:
09239908
Filing Dt:
01/29/1999
Title:
HIGH-VOLTAGE PUMP ARCHITECTURE FOR INTEGRATED ELECTRONIC DEVICES
22
Patent #:
Issue Dt:
01/27/2004
Application #:
09239911
Filing Dt:
01/29/1999
Publication #:
Pub Dt:
06/20/2002
Title:
METHOD TO ACCESS MEMORY BASED ON A PROGRAMMABLE PAGE LIMIT
23
Patent #:
Issue Dt:
09/02/2003
Application #:
09240395
Filing Dt:
01/29/1999
Title:
FABRICATION OF SEMICONDUCTOR DEVICES WITH TRANSITION METAL BORIDE FILMS AS DIFFUSION BARRIERS
24
Patent #:
Issue Dt:
06/18/2002
Application #:
09240526
Filing Dt:
01/29/1999
Title:
DEVICE TO ACCESS MEMORY BASED ON A PROGRAMMABLE PAGE LIMIT
25
Patent #:
Issue Dt:
08/14/2001
Application #:
09241061
Filing Dt:
02/01/1999
Title:
SILICON MULTI-CHIP MODULE PACKAGING WITH INTEGRATED PASSIVE COMPONENTS AND METHOD OF MAKING
26
Patent #:
Issue Dt:
05/16/2000
Application #:
09241553
Filing Dt:
02/01/1999
Title:
METHOD, APPARATUS AND SYSTEM FOR WAFER LEVEL TESTING SEMICONDUCTOR DICE
27
Patent #:
Issue Dt:
02/06/2001
Application #:
09243220
Filing Dt:
02/01/1999
Title:
SEMICONDUCTOR PROCESSING METHOD OF FORMING A CONTACT OPENING TO A REGION ADJACENT A FIELD ISOLATION MASS, AND A SEMICONDUCTOR STRUCTURE
28
Patent #:
Issue Dt:
02/20/2001
Application #:
09243584
Filing Dt:
02/03/1999
Title:
INDUCTOR WITH MAGNETIC MATERIAL LAYERS
29
Patent #:
Issue Dt:
03/07/2000
Application #:
09243587
Filing Dt:
02/03/1999
Title:
HIGH AND NEGATIVE VOLTAGE COMPARE
30
Patent #:
Issue Dt:
07/09/2002
Application #:
09243929
Filing Dt:
02/03/1999
Title:
MATRIX-ADDRESSABLE DISPLAY WITH MINIMUM COLUMN-ROW OVERLAP AND MAXIMUM METAL LINE-WIDTH
31
Patent #:
Issue Dt:
03/25/2003
Application #:
09243942
Filing Dt:
02/04/1999
Title:
DEPOSITION OF SMOOTH ALUMINUM FILMS
32
Patent #:
Issue Dt:
09/18/2001
Application #:
09244557
Filing Dt:
02/03/1999
Title:
METHOD OF JOINTLY FORMING STACKED CAPACITORS AND ANTIFUSES METHOD OF BLOWING ANTIFUSES AND ANTIFUSES AND STACKED CAPACITORS CONSTITUTING A PART OF INTEGRATED CIRCUITRY
33
Patent #:
Issue Dt:
07/04/2000
Application #:
09244733
Filing Dt:
02/05/1999
Title:
HERMETIC CHIP AND METHOD OF MANUFACTURE
34
Patent #:
Issue Dt:
12/14/1999
Application #:
09244917
Filing Dt:
02/10/1999
Title:
FAST POWER UP REFERENCE VOLTAGE CIRCUIT AND METHOD
35
Patent #:
Issue Dt:
06/05/2001
Application #:
09244920
Filing Dt:
02/04/1999
Title:
FLASH MEMORY SYSTEM HAVING FAST ERASE OPERATION
36
Patent #:
Issue Dt:
01/23/2001
Application #:
09244948
Filing Dt:
02/04/1999
Title:
METHOD AND APPARATUS FOR UNIFORMLY PLANARIZING A MICROELECTRONIC SUBSTRATE
37
Patent #:
Issue Dt:
11/07/2000
Application #:
09244972
Filing Dt:
02/05/1999
Title:
TAPE UNDER FRAME FOR CONVENTIONAL-TYPE IC PACKAGE ASSEMBLY
38
Patent #:
Issue Dt:
01/16/2001
Application #:
09245108
Filing Dt:
01/13/1999
Title:
METHOD FOR BURNING IN AND DIAGNOSTICALLY TESTING A COMPUTER
39
Patent #:
Issue Dt:
09/12/2000
Application #:
09245996
Filing Dt:
02/05/1999
Title:
METHOD OF FORMING AN INTEGRATED CIRCUIT STRUCTURE
40
Patent #:
Issue Dt:
10/17/2000
Application #:
09246029
Filing Dt:
02/05/1999
Title:
TEMPERATURE-STABLE CURRENT GENERATION
41
Patent #:
Issue Dt:
06/19/2001
Application #:
09246668
Filing Dt:
02/05/1999
Title:
WIRE BOND MONITORING SYSTEM FOR LAYERED PACKAGES
42
Patent #:
Issue Dt:
01/04/2005
Application #:
09246918
Filing Dt:
02/09/1999
Title:
DEVICES HAVING IMPROVED CAPACITANCE AND METHODS OF THEIR FABRICATION
43
Patent #:
Issue Dt:
02/26/2002
Application #:
09247009
Filing Dt:
02/08/1999
Title:
MULTIPLE DIE STACK APPARATUS EMPLOYING T-SHAPED INTERPOSER ELEMENTS
44
Patent #:
Issue Dt:
05/29/2001
Application #:
09247126
Filing Dt:
02/08/1999
Title:
A METHOD OF FORMING A CAPACITOR
45
Patent #:
Issue Dt:
07/03/2001
Application #:
09247680
Filing Dt:
02/09/1999
Title:
CURRENT MODE SIGNAL INTERCONNECTS AND CMOS AMPLIFIER
46
Patent #:
Issue Dt:
10/05/1999
Application #:
09247701
Filing Dt:
02/10/1999
Title:
MEMORY DEVICE COMMUNICATION LINE CONTROL
47
Patent #:
Issue Dt:
09/14/1999
Application #:
09247994
Filing Dt:
02/10/1999
Title:
SYNCHRONOUS DRAM CHACHE USING WRITE SIGNAL TO TO DETERMINE SINGLE OR BURST WRITE
48
Patent #:
Issue Dt:
03/13/2001
Application #:
09248091
Filing Dt:
02/10/1999
Title:
METHOD OF FORMING AN ELECTRICAL CONNECTION
49
Patent #:
Issue Dt:
05/02/2000
Application #:
09248499
Filing Dt:
02/10/1999
Title:
METHOD FOR IMPROVED METAL FILL BY TREATMENT OF MOBILITY LAYERS
50
Patent #:
Issue Dt:
07/18/2000
Application #:
09248908
Filing Dt:
02/12/1999
Title:
THERMAL CONDITIONING APPARATUS
51
Patent #:
Issue Dt:
09/18/2001
Application #:
09249478
Filing Dt:
02/12/1999
Title:
METHOD FOR PECVD DEPOSITION OF SELECTED MATERIAL FILMS
52
Patent #:
Issue Dt:
08/22/2000
Application #:
09249659
Filing Dt:
02/12/1999
Title:
INTERLEVEL DIELECTRIC STRUCTURE
53
Patent #:
Issue Dt:
05/22/2001
Application #:
09249787
Filing Dt:
02/16/1999
Title:
SIMPLIFIED ETCHING TECHNIQUE FOR PRODUCING MULTIPLE UNDERCUT PROFILES
54
Patent #:
Issue Dt:
11/21/2000
Application #:
09250067
Filing Dt:
02/12/1999
Title:
SELF-CONTAINED THERMAL CONDITIONING APPARATUS
55
Patent #:
Issue Dt:
04/18/2000
Application #:
09250071
Filing Dt:
02/12/1999
Title:
THERMAL CONDITIONING APPARATUS
56
Patent #:
Issue Dt:
09/05/2000
Application #:
09250289
Filing Dt:
02/12/1999
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS USING FOCUSED LASER BEAM
57
Patent #:
Issue Dt:
08/22/2000
Application #:
09250366
Filing Dt:
02/12/1999
Title:
SELF-CONTAINED THERMAL CONDITIONING APPARATUS
58
Patent #:
Issue Dt:
01/09/2001
Application #:
09250484
Filing Dt:
02/12/1999
Title:
THERMAL CONDITIONING APPARATUS
59
Patent #:
Issue Dt:
01/28/2003
Application #:
09250592
Filing Dt:
02/16/1999
Publication #:
Pub Dt:
02/07/2002
Title:
TEMPERATURE COMPENSATED REFERENCE VOLTAGE CIRCUIT
60
Patent #:
Issue Dt:
05/09/2000
Application #:
09250593
Filing Dt:
02/16/1999
Title:
METHOD AND APPARATUS FOR SIMULTANEOUS MEMORY SUBARRAY TESTING
61
Patent #:
Issue Dt:
03/11/2008
Application #:
09250940
Filing Dt:
02/18/1999
Title:
SYSTEM AND METHOD FOR CONTROLLING AN ELECTRONIC DEVICE
62
Patent #:
Issue Dt:
05/16/2000
Application #:
09250950
Filing Dt:
02/16/1999
Title:
APPARATUS FOR UNIFORM GAS AND RADIANT HEAT DISPERSION FOR SOLID STATE FABRICTION PROCESSES
63
Patent #:
Issue Dt:
12/05/2000
Application #:
09250992
Filing Dt:
02/16/1999
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING SELF-ALIGNED CONTACT OPENINGS
64
Patent #:
Issue Dt:
07/30/2002
Application #:
09250994
Filing Dt:
02/16/1999
Title:
INSERT FOR SEATING A MICROELECTRONIC DEVICE HAVING A PROTRUSION AND A PLURALITY OF RAISED-CONTACTS
65
Patent #:
Issue Dt:
04/22/2003
Application #:
09251219
Filing Dt:
02/16/1999
Publication #:
Pub Dt:
06/14/2001
Title:
PROCESSING METHODS OF FORMING AN ELECTRICALLY CONDUCTIVE PLUG TO A NODE LOCATION
66
Patent #:
Issue Dt:
09/18/2001
Application #:
09251252
Filing Dt:
02/16/1999
Title:
METHOD AND APPARATUS FOR REDUCING BGA WARPAGE CAUSED BY ENCAPSULATION
67
Patent #:
Issue Dt:
07/10/2001
Application #:
09251264
Filing Dt:
02/16/1999
Title:
METHODS OF FORMING SILICON-COMPRISING MATERIALS HAVING ROUGHENED OUTER SURFACES, AND METHODS OF FORMING CAPACITOR CONSTRUCTIONS
68
Patent #:
Issue Dt:
06/27/2000
Application #:
09251281
Filing Dt:
02/16/1999
Title:
TIMER CIRCUIT WITH PROGRAMMABLE DECODE CIRCUITRY
69
Patent #:
Issue Dt:
04/02/2002
Application #:
09251758
Filing Dt:
02/18/1999
Title:
SMART COLUMN CONTROLS FOR HIGH SPEED MULTI-RESOLUTION SENSORS
70
Patent #:
Issue Dt:
08/13/2002
Application #:
09251954
Filing Dt:
02/17/1999
Title:
METHOD OF CHECKING DATA INTEGRITY FOR A RAID 1 SYSTEM
71
Patent #:
Issue Dt:
03/14/2000
Application #:
09252369
Filing Dt:
02/18/1999
Title:
MEMORY ARCHITECTURE AND DECODER ADDRESSING
72
Patent #:
Issue Dt:
03/30/2004
Application #:
09252448
Filing Dt:
02/18/1999
Publication #:
Pub Dt:
11/08/2001
Title:
FABRICATION OF SEMICODUCTOR DEVICES USING ANTI- REFLECTIVE COATINGS
73
Patent #:
Issue Dt:
07/17/2001
Application #:
09252697
Filing Dt:
02/18/1999
Title:
FORMATION OF ELECTRICAL CONTACTS TO CONDUCTIVE ELEMENTS IN THE FABRICATION OF SEMICONDUCTOR INTEGRATED CIRCUITS
74
Patent #:
Issue Dt:
02/29/2000
Application #:
09253062
Filing Dt:
02/19/1999
Title:
ALIGNMENT METHOD FOR FIELD EMISSION AND PLASMA DISPLAYS
75
Patent #:
Issue Dt:
02/15/2005
Application #:
09253227
Filing Dt:
02/19/1999
Title:
INTEGRATED CIRCUIT PACKAGES, BALL-GRID ARRAY INTEGRATED CIRCUIT PACKAGES AND METHODS OF PACKAGING AN INTEGRATED CIRCUIT
76
Patent #:
Issue Dt:
08/29/2000
Application #:
09253323
Filing Dt:
02/19/1999
Title:
EFFICIENT VCCP SUPPLY WITH REGULATION FOR VOLTAGE CONTROL
77
Patent #:
Issue Dt:
09/04/2001
Application #:
09253330
Filing Dt:
02/19/1999
Title:
TEST CARRIER WITH FORCE APPLYING MECHANISM GUIDE AND TERMINAL CONTACT PROTECTOR
78
Patent #:
Issue Dt:
01/16/2001
Application #:
09253578
Filing Dt:
02/19/1999
Title:
TEST CARRIER WITH DECOUPLING CAPACITORS FOR TESTING SEMICONDUCTOR COMPONENTS
79
Patent #:
Issue Dt:
01/18/2005
Application #:
09253611
Filing Dt:
02/19/1999
Publication #:
Pub Dt:
08/16/2001
Title:
SELECTIVE DEPOSITION OF SOLDER BALL CONTACTS
80
Patent #:
Issue Dt:
06/13/2000
Application #:
09253626
Filing Dt:
02/19/1999
Title:
MULTIPLE STAGED POWER UP OF INTEGRATED CIRCUIT
81
Patent #:
Issue Dt:
06/05/2001
Application #:
09253632
Filing Dt:
02/19/1999
Title:
INTERPOSER FOR SEMICONDUCTOR COMPONENTS HAVING CONTACT BALLS
82
Patent #:
Issue Dt:
08/01/2000
Application #:
09255069
Filing Dt:
02/22/1999
Title:
REDUNDANT ROW TOPOLOGY CIRCUIT, AND MEMORY DEVICE AND TEST SYSTEM USING SAME
83
Patent #:
Issue Dt:
11/02/1999
Application #:
09255071
Filing Dt:
02/22/1999
Title:
METHOD AND APPARATUS FOR SIGNAL TRANSITION DETECTION IN INTEGRATED CIRCUITS
84
Patent #:
Issue Dt:
04/23/2002
Application #:
09255077
Filing Dt:
02/22/1999
Publication #:
Pub Dt:
01/17/2002
Title:
PSEUDO-DIFFERENTIAL AMPLIFIERS
85
Patent #:
Issue Dt:
02/13/2001
Application #:
09255244
Filing Dt:
02/22/1999
Title:
SYSTEM AND METHOD FOR SCOPING GLOBAL NETS IN A FLAT NETLIST
86
Patent #:
Issue Dt:
08/29/2000
Application #:
09255468
Filing Dt:
02/22/1999
Title:
APPARATUS AND SYSTEM FOR FABRICATING LITHOGRAPHIC STENCIL MASKS
87
Patent #:
Issue Dt:
11/07/2000
Application #:
09255554
Filing Dt:
02/22/1999
Title:
ASYMMETRIC TRANSFER MOLDING METHOD AND AN ASYMMETRIC ENCAPSULATION MADE THEREFROM
88
Patent #:
Issue Dt:
04/10/2001
Application #:
09255667
Filing Dt:
02/23/1999
Title:
METHODS OF FORMING INTEGRATED CIRCUITRY AND INTEGRATED CIRCUITRY
89
Patent #:
Issue Dt:
11/27/2001
Application #:
09255962
Filing Dt:
02/23/1999
Title:
A METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT TOLERANCE IN MULTIPLE, SINGULATED PLUGS
90
Patent #:
Issue Dt:
08/20/2002
Application #:
09256125
Filing Dt:
02/24/1999
Title:
VARIABLE EQUILIBRATE VOLTAGE CIRCUIT FOR PAIRED DIGIT LINES
91
Patent #:
Issue Dt:
07/24/2001
Application #:
09256328
Filing Dt:
02/23/1999
Title:
VOLTAGE INDEPENDENT FUSE CIRCUIT AND METHOD
92
Patent #:
Issue Dt:
07/25/2000
Application #:
09256603
Filing Dt:
02/23/1999
Title:
SENSE AMPLIFIER FOR NON-VOLATILE MEMORY DEVICES
93
Patent #:
Issue Dt:
04/11/2000
Application #:
09256648
Filing Dt:
02/23/1999
Title:
BITLINE BIAS CIRCUIT FOR NON-VOLATILE MEMORY DEVICES
94
Patent #:
Issue Dt:
07/30/2002
Application #:
09256867
Filing Dt:
02/24/1999
Title:
RECESSED TAPE AND METHOD FOR FORMING A BGA ASSEMBLY
95
Patent #:
Issue Dt:
10/23/2001
Application #:
09256871
Filing Dt:
02/24/1999
Title:
CIRCUITS AND METHOD FOR MULTI-LEVEL DATA THROUGH A SINGLE INPUT/OUTPUT PIN
96
Patent #:
Issue Dt:
10/17/2000
Application #:
09256882
Filing Dt:
02/24/1999
Title:
FIELD EMISSION DISPLAYS WITH REDUCED LIGHT LEAKAGE
97
Patent #:
Issue Dt:
05/01/2001
Application #:
09257401
Filing Dt:
02/25/1999
Title:
SILICON OXIDE CO-DEPOSITION/ETCHING PROCESS
98
Patent #:
Issue Dt:
04/03/2001
Application #:
09257466
Filing Dt:
02/24/1999
Title:
HOMOJUNCTION SEMICONDUCTOR DEVICES WITH LOW BARRIER TUNNEL OXIDE CONTACTS
99
Patent #:
Issue Dt:
05/09/2000
Application #:
09257567
Filing Dt:
02/25/1999
Title:
DIE PADDLE HEAT SINK WITH THERMAL POSTS
100
Patent #:
Issue Dt:
10/07/2003
Application #:
09257659
Filing Dt:
02/25/1999
Publication #:
Pub Dt:
08/16/2001
Title:
LOW TEMPERATURE SILICON WAFER BOND PROCESS WITH BULK MATERIAL BOND STRENGTH
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

Search Results as of: 05/14/2024 06:41 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT