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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
05/24/2005
Application #:
09561794
Filing Dt:
05/01/2000
Title:
MICROELECTRONIC DEVICE FABRICATING METHOD, INTEGRATED CIRCUIT, AND INTERMEDIATE CONSTRUCTION
2
Patent #:
Issue Dt:
10/22/2002
Application #:
09562046
Filing Dt:
05/01/2000
Title:
CLEANING COMPOSITION CONTAINING TETRAALKYLAMMONIUM SALT AND USE THEREOF IN SEMICONDUCTOR FABRICATION
3
Patent #:
Issue Dt:
03/25/2003
Application #:
09562380
Filing Dt:
05/01/2000
Title:
METHOD AND APPARATUS OF DIE ATTACHMENT FOR BOC AND F/C SURFACE MOUNT
4
Patent #:
Issue Dt:
07/10/2001
Application #:
09562670
Filing Dt:
05/01/2000
Title:
Semiconductor package having downset leadframe for reducing package bow
5
Patent #:
Issue Dt:
02/04/2003
Application #:
09564356
Filing Dt:
05/01/2000
Title:
LOW WORK FUNCTION EMITTERS AND METHOD FOR PRODUCTION OF FED'S
6
Patent #:
Issue Dt:
08/24/2004
Application #:
09565135
Filing Dt:
05/05/2000
Title:
THREE-LEVEL UNITARY INTERCONNECT STRUCTURE
7
Patent #:
Issue Dt:
11/05/2002
Application #:
09565197
Filing Dt:
05/04/2000
Title:
CONTACT OPENINGS, METHODS OF FORMING ELECTRICAL CONNECTIONS FOR INTERCONNECTIONS, AND INTEGRATED CIRCUITRY
8
Patent #:
Issue Dt:
03/20/2007
Application #:
09565215
Filing Dt:
05/04/2000
Title:
MULTI-WIRELESS NETWORK CONFIGURABLE BEHAVIOR
9
Patent #:
Issue Dt:
06/25/2002
Application #:
09565517
Filing Dt:
05/05/2000
Title:
Nonvolatile memory using flexible erasing methods and method and system for using same
10
Patent #:
Issue Dt:
05/06/2003
Application #:
09565638
Filing Dt:
05/04/2000
Title:
METHOD FOR PACKAGING MICROELECTRONIC SUBSTRATES
11
Patent #:
Issue Dt:
04/22/2003
Application #:
09566185
Filing Dt:
05/05/2000
Title:
FAN DUCT MODULE
12
Patent #:
Issue Dt:
07/22/2003
Application #:
09567574
Filing Dt:
05/10/2000
Publication #:
Pub Dt:
03/21/2002
Title:
STATE MACHINE HAVING EACH EXECUTION CYCLE DIRECTLY CONNECTED TO A SUSPEND CYCLE TO ACHIEVE FAST SUSPEND OF ERASE OPERATION IN FLASH MEMORIES
13
Patent #:
Issue Dt:
09/10/2002
Application #:
09567631
Filing Dt:
05/09/2000
Title:
METHOD AND APPARATUS FOR SELECTIVE REMOVAL OF MATERIAL FROM WAFER ALIGNMENT MARKS
14
Patent #:
Issue Dt:
07/03/2001
Application #:
09567632
Filing Dt:
05/09/2000
Title:
Apparatus and method for disabling and re-enabling access to ic test functions
15
Patent #:
Issue Dt:
10/22/2002
Application #:
09567649
Filing Dt:
05/09/2000
Publication #:
Pub Dt:
07/18/2002
Title:
CONTACT PLUG
16
Patent #:
Issue Dt:
08/21/2007
Application #:
09567673
Filing Dt:
05/09/2000
Title:
VERTICAL TWIST SCHEME FOR HIGH-DENSITY DRAMS
17
Patent #:
Issue Dt:
07/03/2001
Application #:
09567796
Filing Dt:
05/09/2000
Title:
Apparatus and method for disabling and re-enabling access to IC test functions
18
Patent #:
Issue Dt:
09/18/2001
Application #:
09568093
Filing Dt:
05/09/2000
Title:
Methods of forming openings and methods of controlling the degree of taper of openings
19
Patent #:
Issue Dt:
03/14/2006
Application #:
09568156
Filing Dt:
05/10/2000
Title:
METHOD OF TUNING A MULTI-PATH CIRCUIT
20
Patent #:
Issue Dt:
03/13/2001
Application #:
09568329
Filing Dt:
05/09/2000
Title:
SEMICONDUCTOR BONDING PAD
21
Patent #:
Issue Dt:
06/04/2002
Application #:
09568676
Filing Dt:
05/11/2000
Title:
MOLDED BALL GRID ARRAY
22
Patent #:
Issue Dt:
01/08/2002
Application #:
09569216
Filing Dt:
05/11/2000
Title:
Loc semiconductor assembled with room temperature adhesive
23
Patent #:
Issue Dt:
09/18/2001
Application #:
09569232
Filing Dt:
05/11/2000
Title:
Method for the in-writing verification of the threshold value in non-volatile memories
24
Patent #:
Issue Dt:
08/28/2001
Application #:
09569446
Filing Dt:
05/12/2000
Title:
SUBSTRATE STRUCTURE
25
Patent #:
Issue Dt:
01/14/2003
Application #:
09569570
Filing Dt:
05/10/2000
Title:
DOUBLE SIDED CONTAINER CAPACITOR FOR DRAM CELL ARRAY AND METHOD OF FORMING SAME
26
Patent #:
Issue Dt:
10/09/2001
Application #:
09570332
Filing Dt:
05/12/2000
Title:
Non-volatile memory device with row redundancy
27
Patent #:
Issue Dt:
09/24/2002
Application #:
09570879
Filing Dt:
05/15/2000
Title:
SUBSTANTIALLY HILLOCK-FREE ALUMINUM-CONTAINING COMPONENTS
28
Patent #:
Issue Dt:
08/28/2001
Application #:
09571074
Filing Dt:
05/15/2000
Title:
Advance metallization process
29
Patent #:
Issue Dt:
02/18/2003
Application #:
09571190
Filing Dt:
05/16/2000
Title:
BALL GRID ARRAY CHIP PACKAGES HAVING IMPROVED TESTING AND STACKING CHARACTERISTICS
30
Patent #:
Issue Dt:
08/06/2002
Application #:
09571206
Filing Dt:
05/16/2000
Title:
METHOD FOR TESTING A MEMORY DEVICE HAVING TWO OR MORE MEMORY ARRAYS
31
Patent #:
Issue Dt:
11/05/2002
Application #:
09571352
Filing Dt:
05/16/2000
Title:
FOUR F2 FOLDED BIT LINE DRAM CELL STRUCTURE HAVING BURIED BIT AND WORD LINES
32
Patent #:
Issue Dt:
04/30/2002
Application #:
09571721
Filing Dt:
05/15/2000
Title:
CENTER BOND FLIP-CHIP SEMICONDUCTOR DEVICE AND METHOD OF MAKING IT
33
Patent #:
Issue Dt:
08/07/2001
Application #:
09571788
Filing Dt:
05/16/2000
Title:
METHOD FOR FORMING OXIDE LAYER IN FIELD REGIONS FO SEMICONDUCTOR SUBSTRATES IN TWO FORMING STEPS WITH ONE STEP PERFORMED AT AN INCREASED PRESSURE
34
Patent #:
Issue Dt:
03/06/2001
Application #:
09572127
Filing Dt:
05/17/2000
Title:
Synchronous multilevel non-volatile memory and related reading method
35
Patent #:
Issue Dt:
08/07/2001
Application #:
09572738
Filing Dt:
05/17/2000
Title:
Method and stencil for extruding material on a substrate
36
Patent #:
Issue Dt:
11/19/2002
Application #:
09573074
Filing Dt:
05/16/2000
Title:
METHOD AND APPARATUS FOR TESTING AN EMBEDDED DRAM
37
Patent #:
Issue Dt:
08/27/2002
Application #:
09573450
Filing Dt:
05/16/2000
Title:
METHOD AND APPARATUS FOR DETECTING INTERCELL DEFECTS IN A MEMORY DEVICE
38
Patent #:
Issue Dt:
08/20/2002
Application #:
09573741
Filing Dt:
05/18/2000
Title:
DISPOSABLE SPACER AND METHOD OF FORMING AND USING SAME
39
Patent #:
Issue Dt:
02/11/2003
Application #:
09574471
Filing Dt:
05/19/2000
Title:
USE OF RESIDUAL ORGANIC COMPOUNDS TO FACILITATE GATE BREAK ON A CARRIER SUBSTRATE FOR A SEMICONDUCTOR DEVICE
40
Patent #:
Issue Dt:
05/08/2001
Application #:
09574678
Filing Dt:
05/17/2000
Title:
Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
41
Patent #:
Issue Dt:
02/28/2006
Application #:
09574736
Filing Dt:
05/18/2000
Title:
REMOTE COMPUTER CONTROLLER AND CONTROL METHOD
42
Patent #:
Issue Dt:
07/30/2002
Application #:
09574759
Filing Dt:
05/19/2000
Title:
METHODS EMPLOYING HYBRID ADHESIVE MATERIALS TO SECURE COMPONENTS OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES TO ONE ANOTHER AND ASSEMBLIES AND PACKAGES INCLUDING COMPONENTS SECURED TO ONE ANOTHER WITH SUCH HYBRID ADHESIVE MATERIALS
43
Patent #:
Issue Dt:
10/02/2001
Application #:
09574850
Filing Dt:
05/19/2000
Title:
Mounting multiple semiconductor dies in a package
44
Patent #:
Issue Dt:
10/09/2001
Application #:
09575964
Filing Dt:
05/23/2000
Title:
Reduced cell voltage for memory device
45
Patent #:
Issue Dt:
07/10/2001
Application #:
09576018
Filing Dt:
05/23/2000
Title:
Electrode structures, display devices containing the same, and methods for making the same
46
Patent #:
Issue Dt:
02/27/2001
Application #:
09576399
Filing Dt:
05/22/2000
Title:
Method and apparatus for application of spray adhesive to a leadframe for chip bonding
47
Patent #:
Issue Dt:
10/16/2001
Application #:
09576445
Filing Dt:
05/22/2000
Title:
Differential correlated double sampling dram sense amplifier
48
Patent #:
Issue Dt:
05/01/2001
Application #:
09576503
Filing Dt:
05/23/2000
Title:
Method and structure for improved alignment tolerance in multiple, singularized plugs
49
Patent #:
Issue Dt:
09/17/2002
Application #:
09576881
Filing Dt:
05/22/2000
Title:
TEST INTERPOSER FOR USE WITH BALL GRID ARRAY PACKAGES, ASSEMBLIES AND BALL GRID ARRAY PACKAGES INCLUDING SAME, AND METHODS
50
Patent #:
Issue Dt:
11/12/2002
Application #:
09577390
Filing Dt:
05/25/2000
Title:
SEMICONDUCTOR STRUCTURE HAVING A PLURALITY OF GATE STACKS
51
Patent #:
Issue Dt:
07/15/2003
Application #:
09578255
Filing Dt:
05/24/2000
Title:
APPARATUS FOR REDUCING WARPAGE DURING APPLICATION AND CURING OF ENCAPSULANT MATERIALS ON A PRINTED CIRCUIT BOARD
52
Patent #:
Issue Dt:
04/16/2002
Application #:
09578778
Filing Dt:
05/25/2000
Title:
Oscillator and switch-over control circuit for a high-voltage generator
53
Patent #:
Issue Dt:
11/25/2003
Application #:
09579333
Filing Dt:
05/25/2000
Publication #:
Pub Dt:
04/10/2003
Title:
METHODS OF CLEANING SURFACES OF COPPER-CONTAINING MATERIALS, AND METHODS OF FORMING OPENINGS TO COPPER-CONTAINING SUBSTRATES
54
Patent #:
Issue Dt:
11/22/2005
Application #:
09579402
Filing Dt:
05/25/2000
Title:
GATE STACK STRUCTURE
55
Patent #:
Issue Dt:
08/21/2001
Application #:
09579538
Filing Dt:
05/24/2000
Title:
Microelectronic device fabricating method, method of forming a pair of conductive device components of different base widths from a common deposited conductive layer
56
Patent #:
Issue Dt:
06/24/2003
Application #:
09579567
Filing Dt:
05/26/2000
Title:
LEAKAGE DETECTION IN FLASH MEMORY CELL
57
Patent #:
Issue Dt:
12/04/2001
Application #:
09580392
Filing Dt:
05/26/2000
Title:
Method and apparatus for storing location identification information within non-volatile memory devices
58
Patent #:
Issue Dt:
05/08/2001
Application #:
09580662
Filing Dt:
05/26/2000
Title:
Apparatus for reducing induced switching transients
59
Patent #:
Issue Dt:
04/24/2001
Application #:
09580860
Filing Dt:
05/30/2000
Title:
Vertical gate transistors in pass transistor logic decode circuits
60
Patent #:
Issue Dt:
06/01/2004
Application #:
09580901
Filing Dt:
05/30/2000
Title:
STATIC PASS TRANSISTOR LOGIC WITH TRANSISTORS WITH MULTIPLE VERTICAL GATES
61
Patent #:
Issue Dt:
09/11/2001
Application #:
09583040
Filing Dt:
05/30/2000
Title:
System for improved memory cell access
62
Patent #:
Issue Dt:
07/03/2001
Application #:
09583478
Filing Dt:
05/31/2000
Title:
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
63
Patent #:
Issue Dt:
07/16/2002
Application #:
09583584
Filing Dt:
05/31/2000
Title:
FIELD PROGRAMMABLE LOGIC ARRAYS WITH TRANSISTORS WITH VERTICAL GATES
64
Patent #:
Issue Dt:
11/08/2005
Application #:
09583883
Filing Dt:
05/31/2000
Title:
HIGH SPEED BUS TOPOLOGY FOR EXPANDABLE SYSTEMS
65
Patent #:
Issue Dt:
06/24/2003
Application #:
09584005
Filing Dt:
05/30/2000
Title:
SURFACE CHANNEL MOS TRANSISTORS, METHODS FOR MAKING THE SAME, AND SEMICONDUCTOR DEVICES CONTAINING THE SAME
66
Patent #:
Issue Dt:
01/06/2004
Application #:
09584157
Filing Dt:
05/31/2000
Title:
MULTILEVEL COPPER INTERCONNECT WITH DOUBLE PASSIVATION
67
Patent #:
Issue Dt:
07/03/2001
Application #:
09584240
Filing Dt:
05/30/2000
Title:
Method for removing contaminants from a semiconductor wafer
68
Patent #:
Issue Dt:
08/21/2001
Application #:
09584256
Filing Dt:
05/31/2000
Title:
Method for forming a semiconductor connection with a top surface having an enlarged recess
69
Patent #:
Issue Dt:
06/01/2010
Application #:
09584520
Filing Dt:
05/31/2000
Title:
REMOTELY MANAGING AND CONTROLLING A CONSUMER APPLIANCE
70
Patent #:
Issue Dt:
11/26/2002
Application #:
09584552
Filing Dt:
05/31/2000
Title:
CLEANING COMPOSITION USEFUL IN SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
71
Patent #:
Issue Dt:
04/17/2001
Application #:
09584564
Filing Dt:
05/31/2000
Title:
Programmable memory decode circuits with transistors with vertical gates
72
Patent #:
Issue Dt:
02/06/2007
Application #:
09585682
Filing Dt:
06/01/2000
Title:
SEMICONDUCTOR DEVICE HAVING A SUBSTRATE AN UNDOPED SILICON OXIDE STRUCTURE AND AN OVERLAYING DOPED SILICON OXIDE STRUCTURE WITH A SIDEWALL TERMINATING AT THE UNDOPED SILICON OXIDE STRUCTURE
73
Patent #:
Issue Dt:
08/13/2002
Application #:
09585916
Filing Dt:
06/02/2000
Title:
CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching
74
Patent #:
Issue Dt:
10/29/2002
Application #:
09586048
Filing Dt:
06/02/2000
Title:
GATE AREA RELIEF STRIP FOR A MOLDED I/C PACKAGE
75
Patent #:
Issue Dt:
08/17/2004
Application #:
09586050
Filing Dt:
06/02/2000
Title:
STACKABLE BALL GRID ARRAY
76
Patent #:
Issue Dt:
04/06/2004
Application #:
09586243
Filing Dt:
06/02/2000
Title:
CHIP SCALE PACKAGES FORMED BY WAFER LEVEL PROCESSING
77
Patent #:
Issue Dt:
11/20/2001
Application #:
09586399
Filing Dt:
06/02/2000
Title:
Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase
78
Patent #:
Issue Dt:
07/09/2002
Application #:
09586952
Filing Dt:
06/05/2000
Title:
AUTOMATED COMBI DEPOSITION APPARATUS AND METHOD
79
Patent #:
Issue Dt:
04/03/2001
Application #:
09587105
Filing Dt:
06/01/2000
Title:
Methods of identifying defects in an array of memory cells and related integrated circuitry
80
Patent #:
Issue Dt:
08/20/2002
Application #:
09587190
Filing Dt:
06/05/2000
Title:
PD-SOI SUBSTRATE WITH SUPPRESSED FLOATING BODY EFFECT AND METHOD FOR ITS FABRICATION
81
Patent #:
Issue Dt:
04/08/2003
Application #:
09587297
Filing Dt:
06/05/2000
Title:
OVERLAY ERROR REDUCTION BY MINIMIZATION OF UNPATTERNED WAFER AREA
82
Patent #:
Issue Dt:
07/29/2003
Application #:
09589043
Filing Dt:
06/06/2000
Title:
DYNAMIC BUFFER ALLOCATION FOR A COMPUTER SYSTEM
83
Patent #:
Issue Dt:
09/09/2003
Application #:
09589671
Filing Dt:
06/07/2000
Title:
METHOD OF FORMING A CAPACITOR STRUCTURE
84
Patent #:
Issue Dt:
03/26/2002
Application #:
09589723
Filing Dt:
06/08/2000
Title:
Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method
85
Patent #:
Issue Dt:
10/08/2002
Application #:
09589848
Filing Dt:
06/08/2000
Title:
STEREOLITHOGRAPHIC METHOD AND APPARATUS FOR FABRICATING SPACERS FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES
86
Patent #:
Issue Dt:
04/15/2003
Application #:
09590023
Filing Dt:
06/07/2000
Title:
SEMICONDUCTOR PACKAGES AND METHODS FOR MAKING THE SAME
87
Patent #:
Issue Dt:
05/22/2001
Application #:
09590035
Filing Dt:
06/07/2000
Title:
Method of chemical mechanical polishing
88
Patent #:
Issue Dt:
05/27/2003
Application #:
09590418
Filing Dt:
06/08/2000
Title:
COLLAR POSITIONABLE ABOUT A PERIPHERY OF A CONTACT PAD AND AROUND A CONDUCTIVE STRUCTURE SECURED TO THE CONTACT PADS, SEMICONDUCTOR DEVICE COMPONENTS INCLUDING SAME, AND METHODS FOR FABRICATING SAME
89
Patent #:
Issue Dt:
11/21/2006
Application #:
09590527
Filing Dt:
06/08/2000
Title:
STRUCTURES FOR STABILIZING SEMICONDUCTOR DEVICES RELATIVE TO TEST SUBSTRATES AND METHODS FOR FABRICATING THE STABILIZERS
90
Patent #:
Issue Dt:
11/12/2002
Application #:
09590612
Filing Dt:
06/09/2000
Title:
METHOD FOR USE OF BUS PARKING STATES TO COMMUNICATE DIAGNOSTIC INFORMATION
91
Patent #:
Issue Dt:
07/07/2009
Application #:
09590646
Filing Dt:
06/08/2000
Title:
REINFORCED, SELF-ALIGNING CONDUCTIVE STRUCTURES FOR SEMICONDUCTOR DEVICE COMPONENTS AND METHODS FOR FABRICATING SAME
92
Patent #:
Issue Dt:
11/19/2002
Application #:
09590791
Filing Dt:
06/08/2000
Title:
METHODS FOR FORMING AND INTEGRATED CIRCUIT STRUCTURES CONTAINING ENHANCED-SURFACE-AREA CONDUCTIVE LAYERS
93
Patent #:
Issue Dt:
12/31/2002
Application #:
09591144
Filing Dt:
06/09/2000
Title:
PRE-APPLIED ADHESION PROMOTER
94
Patent #:
Issue Dt:
12/11/2001
Application #:
09591969
Filing Dt:
06/12/2000
Title:
SEMICONDUCTOR DEVICES COMPRISING SEMICONDUCTIVE MATERIAL SUBSTRATES AND INSULATOR LAYERS OVER THE SUBSTRATES
95
Patent #:
Issue Dt:
05/08/2001
Application #:
09592057
Filing Dt:
06/12/2000
Title:
Method of constructing a wafer carrier
96
Patent #:
Issue Dt:
05/29/2001
Application #:
09592356
Filing Dt:
06/12/2000
Title:
Wafer carrier having both a rigid structure and resistance to corrosive environments
97
Patent #:
Issue Dt:
07/23/2002
Application #:
09592441
Filing Dt:
06/12/2000
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY
98
Patent #:
Issue Dt:
10/21/2003
Application #:
09592604
Filing Dt:
06/12/2000
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
99
Patent #:
Issue Dt:
11/11/2003
Application #:
09592933
Filing Dt:
06/13/2000
Title:
REFERENCE VOLTAGE FILTER FOR MEMORY MODULES
100
Patent #:
Issue Dt:
08/13/2002
Application #:
09593046
Filing Dt:
06/12/2000
Title:
FIXED ABRASIVE POLISHING PAD
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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