skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 18018
Page 54 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
6556483
Issue Dt:
04/29/2003
Application #:
09973999
Filing Dt:
10/09/2001
Publication #:
US20020023200
Pub Dt:
02/21/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
2
Patent #:
6514795
Issue Dt:
02/04/2003
Application #:
09974192
Filing Dt:
10/10/2001
Title:
PACKAGED STACKED SEMICONDUCTOR DIE AND METHOD OF PREPARING SAME
3
Patent #:
6611885
Issue Dt:
08/26/2003
Application #:
09974349
Filing Dt:
10/09/2001
Publication #:
US20020016895
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
4
Patent #:
6789175
Issue Dt:
09/07/2004
Application #:
09974350
Filing Dt:
10/09/2001
Publication #:
US20020016885
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
5
Patent #:
6741253
Issue Dt:
05/25/2004
Application #:
09974364
Filing Dt:
10/09/2001
Publication #:
US20030067472
Pub Dt:
04/10/2003
Title:
EMBEDDED MEMORY SYSTEM AND METHOD INCLUDING DATA ERROR CORRECTION
6
Patent #:
6560668
Issue Dt:
05/06/2003
Application #:
09974384
Filing Dt:
10/09/2001
Publication #:
US20020016884
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR READING WRITE-MODIFIED READ DATA IN MEMORY DEVICE PROVIDING SYNCHRONOUS DATA TRANSFERS
7
Patent #:
6930524
Issue Dt:
08/16/2005
Application #:
09974386
Filing Dt:
10/09/2001
Publication #:
US20030067331
Pub Dt:
04/10/2003
Title:
DUAL-PHASE DELAY-LOCKED LOOP CIRCUIT AND METHOD
8
Patent #:
6614698
Issue Dt:
09/02/2003
Application #:
09974387
Filing Dt:
10/09/2001
Publication #:
US20020019918
Pub Dt:
02/14/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
9
Patent #:
6501700
Issue Dt:
12/31/2002
Application #:
09974737
Filing Dt:
10/09/2001
Publication #:
US20020054537
Pub Dt:
05/09/2002
Title:
INTERNAL ADDRESSING STRUCTURE OF A SEMICONDUCTOR MEMORY
10
Patent #:
6774486
Issue Dt:
08/10/2004
Application #:
09974947
Filing Dt:
10/10/2001
Publication #:
US20030067074
Pub Dt:
04/10/2003
Title:
CIRCUIT BOARDS CONTAINING VIAS AND METHODS FOR PRODUCING SAME
11
Patent #:
7264456
Issue Dt:
09/04/2007
Application #:
09974958
Filing Dt:
10/10/2001
Publication #:
US20030067061
Pub Dt:
04/10/2003
Title:
LEADFRAME AND METHOD FOR REDUCING MOLD COMPOUND ADHESION PROBLEMS
12
Patent #:
6498063
Issue Dt:
12/24/2002
Application #:
09975879
Filing Dt:
10/12/2001
Title:
EVEN NUCLEATION BETWEEN SILICON AND OXIDE SURFACES FOR THIN SILICON NITRIDE FILM GROWTH
13
Patent #:
6646298
Issue Dt:
11/11/2003
Application #:
09975884
Filing Dt:
10/11/2001
Publication #:
US20030011012
Pub Dt:
01/16/2003
Title:
CAPACITOR WITH OXYGENATED METAL ELECTRODES AND HIGH DIELECTRIC CONSTANT MATERIALS
14
Patent #:
6614072
Issue Dt:
09/02/2003
Application #:
09976000
Filing Dt:
10/15/2001
Publication #:
US20020072174
Pub Dt:
06/13/2002
Title:
HIGH COUPLING SPLIT-GATE TRANSISTOR
15
Patent #:
6646913
Issue Dt:
11/11/2003
Application #:
09976473
Filing Dt:
10/11/2001
Publication #:
US20020054505
Pub Dt:
05/09/2002
Title:
METHOD FOR STORING AND READING DATA IN A MULTILEVEL NONVOLATILE MEMORY
16
Patent #:
7081398
Issue Dt:
07/25/2006
Application #:
09976635
Filing Dt:
10/12/2001
Publication #:
US20030071356
Pub Dt:
04/17/2003
Title:
METHODS OF FORMING A CONDUCTIVE LINE
17
Patent #:
6606264
Issue Dt:
08/12/2003
Application #:
09977288
Filing Dt:
10/16/2001
Publication #:
US20020018362
Pub Dt:
02/14/2002
Title:
PROGRAMMABLE CIRCUIT AND ITS METHOD OF OPERATION
18
Patent #:
6701419
Issue Dt:
03/02/2004
Application #:
09977561
Filing Dt:
10/15/2001
Publication #:
US20020087817
Pub Dt:
07/04/2002
Title:
INTERLACED MEMORY DEVICE WITH RANDOM OR SEQUENTIAL ACCESS
19
Patent #:
6433593
Issue Dt:
08/13/2002
Application #:
09977661
Filing Dt:
10/15/2001
Publication #:
US20020024365
Pub Dt:
02/28/2002
Title:
GATE COUPLED VOLTAGE SUPPORT FOR AN OUTPUT DRIVER CIRCUIT
20
Patent #:
6442086
Issue Dt:
08/27/2002
Application #:
09977755
Filing Dt:
10/15/2001
Publication #:
US20020021607
Pub Dt:
02/21/2002
Title:
DEVICE AND METHOD FOR MARGIN TESTING A SEMICONDUCTOR MEMORY BY APPLYING A STRESSING VOLTAGE SIMULTANEOUSLY TO COMPLEMENTARY AND TRUE DIGIT LINES
21
Patent #:
6475899
Issue Dt:
11/05/2002
Application #:
09978071
Filing Dt:
10/17/2001
Publication #:
US20020063333
Pub Dt:
05/30/2002
Title:
LOW CAPACITANCE WIRING LAYOUT AND METHOD FOR MAKING SAME
22
Patent #:
6528429
Issue Dt:
03/04/2003
Application #:
09978489
Filing Dt:
10/15/2001
Publication #:
US20020025680
Pub Dt:
02/28/2002
Title:
METHODS OF ETCHING INSULATIVE MATERIALS, OF FORMING ELECTRICAL DEVICES, AND OF FORMING CAPACITORS
23
Patent #:
6831301
Issue Dt:
12/14/2004
Application #:
09978983
Filing Dt:
10/15/2001
Publication #:
US20030071334
Pub Dt:
04/17/2003
Title:
METHOD AND SYSTEM FOR ELECTRICALLY COUPLING A CHIP TO CHIP PACKAGE
24
Patent #:
6747348
Issue Dt:
06/08/2004
Application #:
09981948
Filing Dt:
10/16/2001
Publication #:
US20030071335
Pub Dt:
04/17/2003
Title:
APPARATUS AND METHOD FOR LEADLESS PACKAGING OF SEMICONDUCTOR DEVICES
25
Patent #:
6574141
Issue Dt:
06/03/2003
Application #:
09982246
Filing Dt:
10/16/2001
Publication #:
US20020085415
Pub Dt:
07/04/2002
Title:
DIFFERENTIAL REDUNDANCY MULTIPLEXOR FOR FLASH MEMORY DEVICES
26
Patent #:
6493280
Issue Dt:
12/10/2002
Application #:
09982682
Filing Dt:
10/22/2001
Publication #:
US20020121653
Pub Dt:
09/05/2002
Title:
METHOD OF REDUCING TRAPPED HOLES INDUCED BY ERASE OPERATIONS IN THE TUNNEL OXIDE OF FLASH MEMORY CELLS
27
Patent #:
6686268
Issue Dt:
02/03/2004
Application #:
09982748
Filing Dt:
10/18/2001
Publication #:
US20020025667
Pub Dt:
02/28/2002
Title:
METHOD OF FORMING OVERMOLDED CHIP SCALE PACKAGE AND RESULTING PRODUCT
28
Patent #:
7205223
Issue Dt:
04/17/2007
Application #:
09982953
Filing Dt:
10/22/2001
Publication #:
US20070042596
Pub Dt:
02/22/2007
Title:
Method of forming an interconnect structure for a semiconductor device
29
Patent #:
6656813
Issue Dt:
12/02/2003
Application #:
09982959
Filing Dt:
10/22/2001
Publication #:
US20020020895
Pub Dt:
02/21/2002
Title:
LOW LOSS HIGH Q INDUCTOR
30
Patent #:
6963142
Issue Dt:
11/08/2005
Application #:
09983983
Filing Dt:
10/26/2001
Publication #:
US20030080441
Pub Dt:
05/01/2003
Title:
FLIP CHIP INTEGRATED PACKAGE MOUNT SUPPORT
31
Patent #:
6933572
Issue Dt:
08/23/2005
Application #:
09984778
Filing Dt:
10/31/2001
Publication #:
US20040077151
Pub Dt:
04/22/2004
Title:
FIELD-SHIELDED SOI-MOS STRUCTURE FREE FROM FLOATING BODY EFFECT, AND METHOD OF FABRICATION THEREFOR
32
Patent #:
6794238
Issue Dt:
09/21/2004
Application #:
09986167
Filing Dt:
11/07/2001
Publication #:
US20030087499
Pub Dt:
05/08/2003
Title:
PROCESS FOR FORMING METALLIZED CONTACTS TO PERIPHERY TRANSISTORS
33
Patent #:
6458015
Issue Dt:
10/01/2002
Application #:
09988865
Filing Dt:
11/19/2001
Publication #:
US20020052052
Pub Dt:
05/02/2002
Title:
CHEMICAL-MECHANICAL PLANARIZATION MACHINE AND METHOD FOR UNIFORMLY PLANARIZING SEMICONDUCTOR WAFERS
34
Patent #:
6594172
Issue Dt:
07/15/2003
Application #:
09988960
Filing Dt:
11/19/2001
Publication #:
US20020114180
Pub Dt:
08/22/2002
Title:
METHOD OF SELECTIVELY FORMING LOCAL INTERCONNECTS USING DESIGN RULES
35
Patent #:
6815818
Issue Dt:
11/09/2004
Application #:
09988984
Filing Dt:
11/19/2001
Publication #:
US20030096497
Pub Dt:
05/22/2003
Title:
ELECTRODE STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT
36
Patent #:
6759911
Issue Dt:
07/06/2004
Application #:
09989209
Filing Dt:
11/19/2001
Publication #:
US20030095009
Pub Dt:
05/22/2003
Title:
DELAY-LOCKED LOOP CIRCUIT AND METHOD USING A RING OSCILLATOR AND COUNTER-BASED DELAY
37
Patent #:
6911723
Issue Dt:
06/28/2005
Application #:
09989326
Filing Dt:
11/20/2001
Publication #:
US20020030262
Pub Dt:
03/14/2002
Title:
MULTIPLE DIE STACK APPARATUS EMPLOYING T-SHAPED INTERPOSER ELEMENTS
38
Patent #:
6861326
Issue Dt:
03/01/2005
Application #:
09989931
Filing Dt:
11/21/2001
Publication #:
US20030094641
Pub Dt:
05/22/2003
Title:
METHODS OF FORMING SEMICONDUCTOR CIRCUITRY, AND SEMICONDUCTOR CONSTRUCTIONS
39
Patent #:
6512705
Issue Dt:
01/28/2003
Application #:
09989964
Filing Dt:
11/21/2001
Title:
METHOD AND APPARATUS FOR STANDBY POWER REDUCTION IN SEMICONDUCTOR DEVICES
40
Patent #:
6525399
Issue Dt:
02/25/2003
Application #:
09990022
Filing Dt:
11/21/2001
Publication #:
US20020050625
Pub Dt:
05/02/2002
Title:
APPARATUS FOR ROTATING A SUBTRATE DURING SEMICONDUCTOR PROCESSING HAVING PERMANENT MAGNETS AND ELECTROMAGNETS AND METHOD OF USING SAME
41
Patent #:
6451214
Issue Dt:
09/17/2002
Application #:
09990481
Filing Dt:
11/16/2001
Publication #:
US20020056697
Pub Dt:
05/16/2002
Title:
RUTHENIUM AND RUTHENIUM DIOXIDE REMOVAL METHOD AND MATERIAL
42
Patent #:
6454957
Issue Dt:
09/24/2002
Application #:
09990486
Filing Dt:
11/16/2001
Publication #:
US20020056701
Pub Dt:
05/16/2002
Title:
RUTHENIUM AND RUTHENIUM DIOXIDE REMOVAL METHOD AND MATERIAL
43
Patent #:
6455933
Issue Dt:
09/24/2002
Application #:
09991010
Filing Dt:
11/16/2001
Publication #:
US20020033540
Pub Dt:
03/21/2002
Title:
UNDERFILL OF A BUMPED OR RAISED DIE UTILIZING A BARRIER ADJACENT TO THE SIDE WALL OF FLIP CHIP
44
Patent #:
6904504
Issue Dt:
06/07/2005
Application #:
09991128
Filing Dt:
11/14/2001
Publication #:
US20030093641
Pub Dt:
05/15/2003
Title:
METHOD AND APPARATUS FOR SOFTWARE SELECTION OF PROTECTED REGISTER SETTINGS
45
Patent #:
6567318
Issue Dt:
05/20/2003
Application #:
09991493
Filing Dt:
11/21/2001
Publication #:
US20020093374
Pub Dt:
07/18/2002
Title:
CONTROL CIRCUIT FOR AN OUTPUT DRIVING STAGE OF AN INTEGRATED CIRCUIT
46
Patent #:
6469542
Issue Dt:
10/22/2002
Application #:
09991504
Filing Dt:
11/16/2001
Publication #:
US20020030508
Pub Dt:
03/14/2002
Title:
VOLTAGE LEVEL TRANSLATOR
47
Patent #:
6931151
Issue Dt:
08/16/2005
Application #:
09991629
Filing Dt:
11/21/2001
Publication #:
US20030095705
Pub Dt:
05/22/2003
Title:
METHOD AND APPARATUS FOR MODIFYING GRAPHICS CONTENT PRIOR TO DISPLAY FOR COLOR BLIND USE
48
Patent #:
6522008
Issue Dt:
02/18/2003
Application #:
09991666
Filing Dt:
11/26/2001
Publication #:
US20020033538
Pub Dt:
03/21/2002
Title:
SUBTRACTIVE METALLIZATION STRUCTURE WITH LOW DIELECTRIC CONSTANT INSULATING LAYERS
49
Patent #:
6716763
Issue Dt:
04/06/2004
Application #:
09991982
Filing Dt:
11/26/2001
Publication #:
US20030096506
Pub Dt:
05/22/2003
Title:
METHOD OF CONTROLLING STRIATIONS AND CD LOSS IN CONTACT OXIDE ETCH
50
Patent #:
6665207
Issue Dt:
12/16/2003
Application #:
09992203
Filing Dt:
11/14/2001
Publication #:
US20030090923
Pub Dt:
05/15/2003
Title:
ROM EMBEDDED DRAM WITH DIELECTRIC REMOVAL/SHORT
51
Patent #:
6522576
Issue Dt:
02/18/2003
Application #:
09992213
Filing Dt:
11/14/2001
Publication #:
US20020034095
Pub Dt:
03/21/2002
Title:
MAGNETO-RESISTIVE MEMORY ARRAY
52
Patent #:
6884658
Issue Dt:
04/26/2005
Application #:
09992580
Filing Dt:
11/16/2001
Publication #:
US20020137258
Pub Dt:
09/26/2002
Title:
DIE STACKING SCHEME
53
Patent #:
6577379
Issue Dt:
06/10/2003
Application #:
09993053
Filing Dt:
11/05/2001
Title:
METHOD AND APPARATUS FOR SHAPING AND/OR ORIENTING RADIATION IRRADIATING A MICROLITHOGRAPHIC SUBSTRATE
54
Patent #:
6937948
Issue Dt:
08/30/2005
Application #:
09993336
Filing Dt:
11/13/2001
Publication #:
US20030093233
Pub Dt:
05/15/2003
Title:
FLASH MEMORY PROGRAM AND ERASE OPERATIONS
55
Patent #:
6560680
Issue Dt:
05/06/2003
Application #:
09994302
Filing Dt:
11/26/2001
Publication #:
US20020099909
Pub Dt:
07/25/2002
Title:
SYSTEM CONTROLLER WITH INTEGRATED LOW LATENCY MEMORY USING NON-CACHEABLE MEMORY PHYSICALLY DISTINCT FROM MAIN MEMORY
56
Patent #:
6693345
Issue Dt:
02/17/2004
Application #:
09995372
Filing Dt:
11/26/2001
Publication #:
US20020047202
Pub Dt:
04/25/2002
Title:
SEMICONDUCTOR WAFER ASSEMBLIES COMPRISING PHOTORESIST OVER SILICON NITRIDE MATERIALS
57
Patent #:
6489226
Issue Dt:
12/03/2002
Application #:
09995373
Filing Dt:
11/26/2001
Publication #:
US20020033490
Pub Dt:
03/21/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY
58
Patent #:
6418034
Issue Dt:
07/09/2002
Application #:
09995936
Filing Dt:
11/27/2001
Publication #:
US20020034068
Pub Dt:
03/21/2002
Title:
STACKED PRINTED CIRCUIT BOARD MEMORY MODULE AND METHOD OF AUGMENTING MEMORY THEREIN
59
Patent #:
6577010
Issue Dt:
06/10/2003
Application #:
09996253
Filing Dt:
11/28/2001
Publication #:
US20020111030
Pub Dt:
08/15/2002
Title:
STEPPED PHOTORESIST PROFILE AND OPENING FORMED USING THE PROFILE
60
Patent #:
7162028
Issue Dt:
01/09/2007
Application #:
09996255
Filing Dt:
11/28/2001
Publication #:
US20030043998
Pub Dt:
03/06/2003
Title:
UNIVERSAL TELEPHONY INTERFACE POLARITY DETECTOR
61
Patent #:
6690148
Issue Dt:
02/10/2004
Application #:
09996452
Filing Dt:
11/28/2001
Publication #:
US20030098675
Pub Dt:
05/29/2003
Title:
METHOD AND CIRCUIT FOR LIMITING A PUMPED VOLTAGE
62
Patent #:
6576988
Issue Dt:
06/10/2003
Application #:
09996595
Filing Dt:
11/30/2001
Publication #:
US20020053736
Pub Dt:
05/09/2002
Title:
SEMICONDUCTOR PACKAGE
63
Patent #:
6568510
Issue Dt:
05/27/2003
Application #:
09997214
Filing Dt:
11/15/2001
Publication #:
US20020119625
Pub Dt:
08/29/2002
Title:
FLASH MEMORY INCLUDING MEANS OF CHECKING MEMORY CELL THRESHOLD VOLTAGES
64
Patent #:
6586313
Issue Dt:
07/01/2003
Application #:
09997227
Filing Dt:
11/29/2001
Publication #:
US20030100166
Pub Dt:
05/29/2003
Title:
METHOD FOR AVOIDING THE EFFECTS OF LACK OF UNIFORMITY IN TRENCH ISOLATED INTEGRATED CIRCUITS
65
Patent #:
6934953
Issue Dt:
08/23/2005
Application #:
09997669
Filing Dt:
11/28/2001
Publication #:
US20030101293
Pub Dt:
05/29/2003
Title:
DEFERRED PROCEDURE CALL IN INTERFACE DESCRIPTON LANGUAGE
66
Patent #:
6455406
Issue Dt:
09/24/2002
Application #:
09997735
Filing Dt:
11/28/2001
Title:
SEMICONDUCTOR PROCESSING METHOD OF FORMING A CONDUCTIVE CONNECTION
67
Patent #:
6501140
Issue Dt:
12/31/2002
Application #:
09997737
Filing Dt:
11/28/2001
Publication #:
US20020033512
Pub Dt:
03/21/2002
Title:
TRANSISTOR STRUCTURES
68
Patent #:
6541390
Issue Dt:
04/01/2003
Application #:
09997917
Filing Dt:
11/30/2001
Publication #:
US20020055262
Pub Dt:
05/09/2002
Title:
METHOD AND COMPOSITION FOR SELECTIVELY ETCHING AGAINST COBALT SILICIDE
69
Patent #:
7189602
Issue Dt:
03/13/2007
Application #:
09998165
Filing Dt:
12/03/2001
Publication #:
US20020055246
Pub Dt:
05/09/2002
Title:
METHOD AND APPARATUS FOR REDUCING SUBSTRATE BIAS VOLTAGE DROP
70
Patent #:
6552394
Issue Dt:
04/22/2003
Application #:
09998420
Filing Dt:
11/29/2001
Publication #:
US20020074597
Pub Dt:
06/20/2002
Title:
SEMICONDUCTOR TRANSISTOR DEVICES AND STRUCTURES WITH HALO REGIONS
71
Patent #:
6720822
Issue Dt:
04/13/2004
Application #:
09998902
Filing Dt:
10/31/2001
Publication #:
US20030080804
Pub Dt:
05/01/2003
Title:
NEGATIVE CHARGE PUMP ARCHITECTURE WITH SELF-GENERATED BOOSTED PHASES
72
Patent #:
6549486
Issue Dt:
04/15/2003
Application #:
09998903
Filing Dt:
10/31/2001
Title:
CIRCUIT FOR GENERATING A PULSE SIGNAL INDEPENDENT OF VOLTAGE AND TEMPERATURE VARIATIONS
73
Patent #:
6630372
Issue Dt:
10/07/2003
Application #:
09999113
Filing Dt:
11/01/2001
Publication #:
US20020041026
Pub Dt:
04/11/2002
Title:
Method for routing die interconnections using intermediate connection elements secured to the die face
74
Patent #:
6466047
Issue Dt:
10/15/2002
Application #:
09999502
Filing Dt:
12/04/2001
Title:
SYSTEM FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS WITH ON-BOARD MULTIPLEX CIRCUIT FOR EXPANDING TESTER RESOURCES
75
Patent #:
6645846
Issue Dt:
11/11/2003
Application #:
09999513
Filing Dt:
10/24/2001
Publication #:
US20030074787
Pub Dt:
04/24/2003
Title:
METHODS OF FORMING CONDUCTIVE CONTACTS TO CONDUCTIVE STRUCTURES
76
Patent #:
6570232
Issue Dt:
05/27/2003
Application #:
09999557
Filing Dt:
10/19/2001
Publication #:
US20020047205
Pub Dt:
04/25/2002
Title:
LOCAL INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUIT DEVICES, SOURCE STRUCTURE FOR THE SAME, AND METHOD FOR FABRICATING THE SAME
77
Patent #:
6717194
Issue Dt:
04/06/2004
Application #:
09999684
Filing Dt:
10/30/2001
Publication #:
US20030081462
Pub Dt:
05/01/2003
Title:
MAGNETO-RESISTIVE BIT STRUCTURE AND METHOD OF MANUFACTURE THEREFOR
78
Patent #:
6649444
Issue Dt:
11/18/2003
Application #:
10000438
Filing Dt:
10/24/2001
Publication #:
US20020068417
Pub Dt:
06/06/2002
Title:
STEREOLITHOGRAPHIC METHOD AND APPARATUS FOR FABRICATING SPACERS FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES
79
Patent #:
6844601
Issue Dt:
01/18/2005
Application #:
10000479
Filing Dt:
10/24/2001
Publication #:
US20020055251
Pub Dt:
05/09/2002
Title:
LOCAL INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUIT DEVICES, SOURCE STRUCTURE FOR THE SAME, AND METHOD FOR FABRICATING THE SAME
80
Patent #:
6727168
Issue Dt:
04/27/2004
Application #:
10001758
Filing Dt:
10/24/2001
Publication #:
US20030077855
Pub Dt:
04/24/2003
Title:
METHODS OF FORMING LOCAL INTERCONNECTS
81
Patent #:
6487111
Issue Dt:
11/26/2002
Application #:
10002071
Filing Dt:
10/31/2001
Publication #:
US20020039309
Pub Dt:
04/04/2002
Title:
MAGNETO-RESISTIVE MEMORY HAVING SENSE AMPLIFIER WITH OFFSET CONTROL
82
Patent #:
6673715
Issue Dt:
01/06/2004
Application #:
10002335
Filing Dt:
10/24/2001
Publication #:
US20030077890
Pub Dt:
04/24/2003
Title:
METHODS OF FORMING CONDUCTIVE CONTACTS
83
Patent #:
7093124
Issue Dt:
08/15/2006
Application #:
10002337
Filing Dt:
10/30/2001
Publication #:
US20030084342
Pub Dt:
05/01/2003
Title:
MECHANISM TO IMPROVE AUTHENTICATION FOR REMOTE MANAGEMENT OF A COMPUTER SYSTEM
84
Patent #:
7000109
Issue Dt:
02/14/2006
Application #:
10002541
Filing Dt:
11/21/2001
Publication #:
US20030097585
Pub Dt:
05/22/2003
Title:
METHOD AND APPARATUS FOR UNLOCKING A COMPUTER SYSTEM HARD DRIVE
85
Patent #:
6603681
Issue Dt:
08/05/2003
Application #:
10002599
Filing Dt:
10/31/2001
Publication #:
US20020122340
Pub Dt:
09/05/2002
Title:
METHOD OF PULSE PROGRAMMING, IN PARTICULAR FOR HIGH-PARALLELISM MEMORY DEVICES, AND A MEMORY DEVICE IMPLEMENTING THE METHOD
86
Patent #:
6560155
Issue Dt:
05/06/2003
Application #:
10002707
Filing Dt:
10/24/2001
Publication #:
US20030076725
Pub Dt:
04/24/2003
Title:
SYSTEM AND METHOD FOR POWER SAVING MEMORY REFRESH FOR DYNAMIC RANDOM ACCESS MEMORY DEVICES AFTER AN EXTENDED INTERVAL
87
Patent #:
6719920
Issue Dt:
04/13/2004
Application #:
10002855
Filing Dt:
11/30/2001
Publication #:
US20030102457
Pub Dt:
06/05/2003
Title:
SLURRY FOR POLISHING A BARRIER LAYER
88
Patent #:
6924168
Issue Dt:
08/02/2005
Application #:
10003116
Filing Dt:
12/06/2001
Publication #:
US20020050632
Pub Dt:
05/02/2002
Title:
METHOD OF FORMING A STRUCTURE FOR SUPPORTING AN INTEGRATED CIRCUIT CHIP
89
Patent #:
7323360
Issue Dt:
01/29/2008
Application #:
10003238
Filing Dt:
10/26/2001
Publication #:
US20030080437
Pub Dt:
05/01/2003
Title:
ELECTRONIC ASSEMBLIES WITH FILLED NO-FLOW UNDERFILL
90
Patent #:
6480421
Issue Dt:
11/12/2002
Application #:
10003474
Filing Dt:
10/25/2001
Publication #:
US20020099988
Pub Dt:
07/25/2002
Title:
CIRCUIT FOR READING NON-VOLATILE MEMORIES
91
Patent #:
6558517
Issue Dt:
05/06/2003
Application #:
10003575
Filing Dt:
10/29/2001
Publication #:
US20020048634
Pub Dt:
04/25/2002
Title:
PHYSICAL VAPOR DEPOSITION METHODS
92
Patent #:
7012315
Issue Dt:
03/14/2006
Application #:
10003821
Filing Dt:
10/31/2001
Title:
FRAME SCALE PACKAGE USING CONTACT LINES THROUGH THE ELEMENTS
93
Patent #:
6727538
Issue Dt:
04/27/2004
Application #:
10004656
Filing Dt:
12/04/2001
Publication #:
US20020038875
Pub Dt:
04/04/2002
Title:
METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT TOLERANCE IN MULTIPLE, SINGULARIZED PLUGS
94
Patent #:
6897529
Issue Dt:
05/24/2005
Application #:
10004661
Filing Dt:
12/04/2001
Publication #:
US20020036302
Pub Dt:
03/28/2002
Title:
STRUCTURE FOR IMPROVED ALIGNMENT TOLERANCE IN MULTIPLE, SINGULARIZED PLUGS
95
Patent #:
6525981
Issue Dt:
02/25/2003
Application #:
10004672
Filing Dt:
12/04/2001
Publication #:
US20020041535
Pub Dt:
04/11/2002
Title:
FULL PAGE INCREMENT/DECREMENT BURST FOR DDR SDRAM/SGRAM
96
Patent #:
6498740
Issue Dt:
12/24/2002
Application #:
10005087
Filing Dt:
12/04/2001
Publication #:
US20020039304
Pub Dt:
04/04/2002
Title:
DIE ARCHITECTURE ACCOMMODATING HIGH-SPEED SEMICONDUCTOR DEVICES
97
Patent #:
6637103
Issue Dt:
10/28/2003
Application #:
10005410
Filing Dt:
12/03/2001
Publication #:
US20020079124
Pub Dt:
06/27/2002
Title:
STRESS RELIEVING TAPE BONDING INTERCONNECT
98
Patent #:
6573571
Issue Dt:
06/03/2003
Application #:
10005439
Filing Dt:
12/03/2001
Publication #:
US20020041029
Pub Dt:
04/11/2002
Title:
SEMICONDUCTOR STRUCTURE INCLUDING METAL NITRIDE AND METAL SILICIDE LAYERS OVER ACTIVE AREA AND GATE STACK
99
Patent #:
6608343
Issue Dt:
08/19/2003
Application #:
10005850
Filing Dt:
12/05/2001
Publication #:
US20020038880
Pub Dt:
04/04/2002
Title:
ROUGH ELECTRODE (HIGH SURFACE AREA) FROM TI AND TIN, CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING SAME
100
Patent #:
6723599
Issue Dt:
04/20/2004
Application #:
10006032
Filing Dt:
12/03/2001
Publication #:
US20030104669
Pub Dt:
06/05/2003
Title:
METHODS OF FORMING CAPACITORS AND METHODS OF FORMING CAPACITOR DIELECTRIC LAYERS
Assignor
1
MICRON TECHNOLOGY, INC.
Exec Dt:
04/26/2016
Assignee
1
U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

Search Results as of: 05/13/2024 07:52 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT