|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10376557
|
Filing Dt:
|
02/27/2003
|
Title:
|
METHOD OF FORMING AN ARRAY OF FLASH FIELD EFFECT TRANSISTORS AND CIRCUITRY PERIPHERAL TO SUCH ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10376730
|
Filing Dt:
|
02/28/2003
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
Title:
|
ROM EMBEDDED DRAM WITH BIAS SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10376768
|
Filing Dt:
|
02/28/2003
|
Publication #:
|
|
Pub Dt:
|
07/10/2003
| | | | |
Title:
|
ROM EMBEDDED DRAM WITH BIAS SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10376769
|
Filing Dt:
|
02/28/2003
|
Publication #:
|
|
Pub Dt:
|
07/10/2003
| | | | |
Title:
|
ROM EMBEDDED DRAM WITH BIAS SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10376962
|
Filing Dt:
|
02/28/2003
|
Publication #:
|
|
Pub Dt:
|
07/24/2003
| | | | |
Title:
|
ROM EMBEDDED DRAM WITH BIAS SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10377495
|
Filing Dt:
|
02/27/2003
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
Gas passivation on nitride encapsulated devices
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10377552
|
Filing Dt:
|
02/27/2003
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR MARKING MICROELECTRONIC DIES AND MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10377904
|
Filing Dt:
|
02/27/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
SCALABLE GATE AND STORAGE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10378354
|
Filing Dt:
|
03/03/2003
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
PROCESS OF FORMING AN ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY WITH AN OXIDE LAYER EXPOSED TO HYDROGEN AND NITROGEN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10378429
|
Filing Dt:
|
03/03/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
SILICON OXIDE CO-DEPOSITION/ETCHING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10378568
|
Filing Dt:
|
03/03/2003
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A DIELECTRIC LAYER EXPOSED TO A HYDROGEN-BEARING NITROGEN SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10378573
|
Filing Dt:
|
03/03/2003
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH A DIELECTRIC LAYER EXPOSED TO A HYDROGEN-BEARING NITROGEN SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10378692
|
Filing Dt:
|
03/04/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
MEMORY SUBSYSTEM VOLTAGE CONTROL AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
10378757
|
Filing Dt:
|
03/04/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
MULTI-PARAMETER PROCESS AND CONTROL METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10378796
|
Filing Dt:
|
03/04/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
DAMASCENE PROCESSES FOR FORMING CONDUCTIVE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10378934
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
Method of forming a multi-layered copper bond pad for an integrated circuit
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10379218
|
Filing Dt:
|
03/04/2003
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
Title:
|
UNDERFILL COATING FOR LOC PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10379478
|
Filing Dt:
|
03/04/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
VERTICAL GAIN CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10379749
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
MICRO-MECHANICALLY STRAINED SEMICONDUCTOR FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10379890
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
CONDUCTIVE THROUGH WAFER VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10382019
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
METHOD TO ELIMINATE STRIATIONS AND SURFACE ROUGHNESS CAUSED BY DRY ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10382025
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
ASSEMBLIES AND PACKAGES INCLUDING DIE TO DIE CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10382680
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
THERMALLY ENHANCED ELECTRONIC FLIP-CHIP PACKAGING WITH EXTERNAL-CONNECTOR SIDE DIE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10382801
|
Filing Dt:
|
03/05/2003
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
Title:
|
PROCESSING METHODS OF FORMING AN ELECTRICALLY CONDUCTIVE PLUG TO A NODE LOCATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10382835
|
Filing Dt:
|
03/07/2003
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
METHOD OF REMOVING FREE HALOGEN FROM A HALOGENATED POLYMER INSULATING LAYER OF A SEMICONDUCTOR DEVICE AND RESULTING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10383893
|
Filing Dt:
|
03/07/2003
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
Title:
|
BULK-ISOLATED PN DIODE AND METHOD OF FORMING A BULK-ISOLATED PN DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10385004
|
Filing Dt:
|
03/10/2003
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
Title:
|
UNIVERSAL MEMORY MODULE/PCB STORAGE, TRANSPORT, AUTOMATION HANDLING TRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10385858
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
OXIDE BUFFER LAYER FOR IMPROVED MAGNETIC TUNNEL JUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10386028
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
CHALCOGENIDE GLASS CONSTANT CURRENT DEVICE, AND ITS METHOD OF FABRICATION AND OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10386254
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10386261
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
TECHNIQUES FOR PACKAGING A MULTIPLE DEVICE COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10386757
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
MICROELECTRONIC COMPONENT ASSEMBLIES HAVING LEAD FRAMES ADAPTED TO REDUCE PACKAGE BOW
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10387036
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/04/2003
| | | | |
Title:
|
APPARATUS FOR PACKAGE REDUCTION IN STACKED CHIP AND BOARD ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10387090
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
LOGIC CONSTRUCTIONS AND ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10387141
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
Title:
|
SEMICONDUCTOR MEMORY WITH SELF-REFRESH CAPABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10387150
|
Filing Dt:
|
03/11/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
LOW SKEW CLOCK INPUT BUFFER AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
10387832
|
Filing Dt:
|
03/14/2003
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
PHOTOLITHOGRAPHY PROCESS USING MULTIPLE ANTI-REFLECTIVE COATINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10388051
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
VOLTAGE CONVERTER SYSTEM AND METHOD HAVING A STABLE OUTPUT VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10388052
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
MULTI-FREQUENCY SYNCHRONIZING CLOCK SIGNAL GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10388053
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
VOLTAGE CONVERTER SYSTEM AND METHOD HAVING A STABLE OUTPUT VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10388058
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
VOLTAGE CONVERTER SYSTEM AND METHOD HAVING A STABLE OUTPUT VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10388103
|
Filing Dt:
|
03/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
TRANSISTOR DEVICES, AND METHODS OF FORMING TRANSISTOR DEVICES AND CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10388264
|
Filing Dt:
|
03/14/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
METHOD FOR FILLING VIA WITH METAL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
10389433
|
Filing Dt:
|
03/14/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
METHOD OF FABRICATING A STACKED DIE HAVING A RECESS IN A DIE BGA PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10389455
|
Filing Dt:
|
03/14/2003
|
Publication #:
|
|
Pub Dt:
|
08/14/2003
| | | | |
Title:
|
A METHOD OF FORMING A BOND PAD STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10389659
|
Filing Dt:
|
03/13/2003
|
Publication #:
|
|
Pub Dt:
|
12/04/2003
| | | | |
Title:
|
CAPACITOR CONSTRUCTIONS, SEMICONDUCTOR CONSTRUCTIONS, AND METHODS OF FORMING ELECTRICAL CONTACTS AND SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10389910
|
Filing Dt:
|
03/18/2003
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH NOVEL FILM COMPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10390556
|
Filing Dt:
|
03/14/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10390863
|
Filing Dt:
|
03/17/2003
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
Title:
|
SEMICONDUCTOR COMPONENT HAVING ENCAPSULATED, BONDED, INTERCONNECT CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10391067
|
Filing Dt:
|
03/17/2003
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
Title:
|
REDUCED TERMINAL TESTING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10391080
|
Filing Dt:
|
03/18/2003
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
Title:
|
METHOD FOR FORMING A PROTECTIVE LAYER FOR USE IN PACKAGING A SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10391267
|
Filing Dt:
|
03/18/2003
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
Title:
|
PROTECTIVE LAYERS FORMED ON SEMICONDUCTOR DEVICE COMPONENTS SO AS TO REDUCE OR ELIMINATE THE OCCURRENCE OF DELAMINATION THEREOF AND CRACKING THEREIN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10391310
|
Filing Dt:
|
03/17/2003
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
Title:
|
METHODS OF FORMING PATTERNS ACROSS PHOTORESIST AND METHODS OF FORMING RADIATION-PATTERNING TOOLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10391725
|
Filing Dt:
|
03/18/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
MICROELECTRONIC COMPONENT ASSEMBLIES HAVING EXPOSED CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10391876
|
Filing Dt:
|
03/18/2003
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
Title:
|
SEMICONDUCTOR MANUFACTURING PROCESS AND APPARATUS FOR MODIFYING IN-FILM STRESS OF THIN FILMS, AND PRODUCT FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10392047
|
Filing Dt:
|
03/18/2003
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
Title:
|
METHOD OF FORMING A SUBSTRATE HAVING A SURFACE COMPRISING AT LEAST ONE OF PT, PD, CO AND AU IN AT LEAST ONE OF ELEMENTAL AND ALLOY FORMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
10393129
|
Filing Dt:
|
03/19/2003
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
Title:
|
MEMORY TRANSISTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10393223
|
Filing Dt:
|
03/20/2003
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
Title:
|
REUSABLE, BUILT-IN SELF-TEST METHODOLOGY FOR COMPUTER SYSTEMS
|
|
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10393240
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Filing Dt:
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03/20/2003
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Publication #:
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Pub Dt:
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10/09/2003
| | | | |
Title:
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METHOD AND DEVICE TO USE MEMORY ACCESS REQUEST TAGS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
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Application #:
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10393257
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Filing Dt:
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03/21/2003
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Publication #:
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Pub Dt:
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12/25/2003
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITHOUT ADVERSE EFFECTS CAUSED BY INCLINATIONS OF WORD LINE AND BIT LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
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Application #:
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10393376
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Filing Dt:
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03/19/2003
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Publication #:
|
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Pub Dt:
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11/10/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR DECOUPLING CONDUCTIVE PORTIONS OF A MICROELECTRONIC DEVICE PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
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Application #:
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10394863
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Filing Dt:
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03/21/2003
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Publication #:
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Pub Dt:
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09/25/2003
| | | | |
Title:
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METHOD FOR ENCAPSULATING A MULTI-CHIP SUBSTRATE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
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Application #:
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10395478
|
Filing Dt:
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03/24/2003
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Publication #:
|
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Pub Dt:
|
09/11/2003
| | | | |
Title:
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DEVICE FOR A MEMORY ARRAY BY STORING EACH BIT IN MULTIPLE MEMORY CELLS IN THE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
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Application #:
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10395576
|
Filing Dt:
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03/24/2003
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Publication #:
|
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Pub Dt:
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07/31/2003
| | | | |
Title:
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MULTI-ACCESS FIFO QUEUE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10395695
|
Filing Dt:
|
03/20/2003
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Publication #:
|
|
Pub Dt:
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03/18/2004
| | | | |
Title:
|
HOST MEMORY INTERFACE FOR A PARALLEL PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
10396164
|
Filing Dt:
|
03/25/2003
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Publication #:
|
|
Pub Dt:
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10/30/2003
| | | | |
Title:
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ETCHANT WITH SELECTIVITY FOR DOPED SILICON DIOXIDE OVER UNDOPED SILICON DIOXIDE AND SILICON NITRIDE, PROCESSES WHICH EMPLOY THE ETCHANT, AND STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10396341
|
Filing Dt:
|
03/26/2003
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Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
A SEMICONDUCTOR HAVING A SUBSTANTIALLY UNIFORM LAYER OF ELECTROPLATED METAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10396849
|
Filing Dt:
|
03/25/2003
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
Title:
|
METHODS FOR FABRICATING PROTECTIVE STRUCTURES FOR BOND WIRES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10400492
|
Filing Dt:
|
03/28/2003
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
PROCESS FOR FORMING METALIZED CONTACTS TO PERIPHERY TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10400620
|
Filing Dt:
|
03/28/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
METHOD FOR REDUCING POWER CONSUMPTION WHEN SENSING A RESISTIVE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10400732
|
Filing Dt:
|
03/27/2003
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
PREVENTING JUNCTION LEAKAGE IN FIELD EMISSION DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10401209
|
Filing Dt:
|
03/27/2003
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
Title:
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METHOD FOR USING DATA REGARDING MANUFACTURING PROCEDURES INTEGRATED CIRCUITS (IC'S) HAVE UNDERGONE, SUCH AS REPAIRS, TO SELECT PROCEDURES THE IC'S UNDERGO, SUCH AS ADDITIONAL REPAIRS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10402125
|
Filing Dt:
|
03/28/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
APPARATUS AND METHOD FOR COMBINING WRITES TO I/O
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10402471
|
Filing Dt:
|
03/28/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
METHOD OF FABRICATING INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10403734
|
Filing Dt:
|
03/31/2003
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
ATOMIC LAYER DEPOSITED ZRALXOY DIELECTRIC LAYERS INCLUDING ZR4AIO9
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10404396
|
Filing Dt:
|
03/31/2003
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
Title:
|
REMOVAL OF COPPER OXIDES FROM INTEGRATED INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10404836
|
Filing Dt:
|
03/31/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
CIRCUIT AND METHOD FOR DECREASING THE REQUIRED REFRESH RATE OF DRAM DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10404859
|
Filing Dt:
|
03/31/2003
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
Title:
|
TEMPERATURE COMPENSATED T-RAM MEMORY DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10404937
|
Filing Dt:
|
03/31/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
LEAKAGE CONTROL IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2004
|
Application #:
|
10405200
|
Filing Dt:
|
04/01/2003
|
Publication #:
|
|
Pub Dt:
|
10/16/2003
| | | | |
Title:
|
METHOD OF MANUFACTURING A PORTION OF A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10405201
|
Filing Dt:
|
04/01/2003
|
Publication #:
|
|
Pub Dt:
|
09/04/2003
| | | | |
Title:
|
METHOD OF SELECTIVELY REMOVING METAL NITRIDE OR METAL OXYNITRIDE EXTRUSIONS FROM A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10405328
|
Filing Dt:
|
04/01/2003
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
Title:
|
METHOD AND SYSTEM FOR DETECTING A MODE OF OPERATION OF AN INTEGRATED CIRCUIT, AND A MEMORY DEVICE INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10405796
|
Filing Dt:
|
03/31/2003
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
INTERCONNECT ALLOYS AND METHODS AND APPARATUS USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10405940
|
Filing Dt:
|
04/02/2003
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
Title:
|
INTEGRATED CIRCUIT CHARACTERIZATION PRINTED CIRCUIT BOARD, TEST EQUIPMENT INCLUDING SAME METHOD OF FABRICATION THEREOF AND METHOD OF CHARACTERIZING AN INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
10406046
|
Filing Dt:
|
04/01/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
HYBRID ARITHMETIC LOGIC UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10406628
|
Filing Dt:
|
04/02/2003
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
Title:
|
ADJUSTABLE FREQUENCY OSCILLATOR WITH PROGRAMMABLE CALIBRATING CIRCUIT AND RELATED SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10406755
|
Filing Dt:
|
04/02/2003
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10406916
|
Filing Dt:
|
04/04/2003
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
Title:
|
METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10407625
|
Filing Dt:
|
04/03/2003
|
Title:
|
MASKING WITHOUT PHOTOLITHOGRAPHY DURING THE FORMATION OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10407957
|
Filing Dt:
|
04/04/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
STACKED LOCAL INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10408450
|
Filing Dt:
|
04/08/2003
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
Title:
|
METHOD OF FORMING SELF-ALIGNED, TRENCHLESS MAGNETORESITIVE RANDOM-ACCESS MEMORY (MRAM) STRUCTURE WITH SIDEWALL CONTAINMENT OF MRAM STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10408528
|
Filing Dt:
|
04/07/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
METHODS EMPLOYING HYBRID ADHESIVE MATERIALS TO SECURE COMPONENTS OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES TO ONE ANOTHER AND ASSEMBLIES AND PACKAGES INCLUDING COMPONENTS SECURED TO ONE ANOTHER WITH SUCH HYBRID ADHESIVE MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10408542
|
Filing Dt:
|
04/07/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
METHODS FOR USE OF PULSED VOLTAGE IN A PLASMA REACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10408972
|
Filing Dt:
|
04/08/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
BOC BGA PACKAGE FOR DIE WITH I-SHAPED BOND PAD LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10408990
|
Filing Dt:
|
04/08/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
BOC BGA PACKAGE FOR DIE WITH I-SHAPED BOND PAD LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10409008
|
Filing Dt:
|
04/08/2003
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING STACKED SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
10409108
|
Filing Dt:
|
04/09/2003
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
Title:
|
BIASING SCHEME FOR LARGE FORMAT CMOS ACTIVE PIXEL SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10409127
|
Filing Dt:
|
04/09/2003
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
Title:
|
SELF-ALIGNED, LOW-RESISTANCE, EFFICIENT MRAM READ/WRITE CONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10409145
|
Filing Dt:
|
04/09/2003
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
Title:
|
SELF-ALIGNED, TRENCHLESS MANGETORESITIVE RANDOM-ACCESS MEMORY (MRAM) STRUCTURE WITH SIDEWALL CONTAINMENT OF MRAM STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10409287
|
Filing Dt:
|
04/08/2003
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
Title:
|
USING A TRANSVERSAL FILTER TO COMPENSATE FOR DISPERSION
|
|