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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/25/2005
Application #:
10409460
Filing Dt:
04/08/2003
Publication #:
Pub Dt:
11/06/2003
Title:
VARIABLE RESISTANCE CIRCUIT
2
Patent #:
Issue Dt:
03/13/2007
Application #:
10409724
Filing Dt:
04/08/2003
Publication #:
Pub Dt:
02/05/2004
Title:
EDGE INTENSIVE ANTIFUSE
3
Patent #:
Issue Dt:
09/05/2006
Application #:
10409804
Filing Dt:
04/09/2003
Publication #:
Pub Dt:
10/14/2004
Title:
INTERPOSER SUBSTRATES WITH REINFORCED INTERCONNECT SLOTS, AND SEMICONDUCTOR DIE PACKAGES INCLUDING SAME
4
Patent #:
Issue Dt:
11/02/2004
Application #:
10410191
Filing Dt:
04/10/2003
Publication #:
Pub Dt:
10/14/2004
Title:
IMAGER LIGHT SHIELD
5
Patent #:
Issue Dt:
05/13/2008
Application #:
10410192
Filing Dt:
04/10/2003
Publication #:
Pub Dt:
10/14/2004
Title:
COMPRESSION SYSTEM FOR INTEGRATED SENSOR DEVICES
6
Patent #:
Issue Dt:
08/15/2006
Application #:
10411422
Filing Dt:
04/10/2003
Publication #:
Pub Dt:
10/14/2004
Title:
FLASH MEMORY DATA BUS FOR SYNCHRONOUS BURST READ PAGE
7
Patent #:
Issue Dt:
04/19/2005
Application #:
10411800
Filing Dt:
04/11/2003
Publication #:
Pub Dt:
11/13/2003
Title:
UNDERFILL AND ENCAPSULATION OF CARRIER SUBSTRATE-MOUNTED FLIP-CHIP COMPONENTS USING STEREOLITHOGRAPHY
8
Patent #:
Issue Dt:
08/02/2005
Application #:
10411853
Filing Dt:
04/11/2003
Publication #:
Pub Dt:
12/25/2003
Title:
SYNCHRONOUS MIRROR DELAY (SMD) CIRCUIT AND METHOD INCLUDING A COUNTER AND REDUCED SIZE BI-DIRECTIONAL DELAY LINE
9
Patent #:
Issue Dt:
05/03/2005
Application #:
10412064
Filing Dt:
04/10/2003
Publication #:
Pub Dt:
10/30/2003
Title:
Method for making an integrated circuit package having reduced bow
10
Patent #:
Issue Dt:
11/18/2008
Application #:
10412716
Filing Dt:
04/11/2003
Publication #:
Pub Dt:
03/18/2004
Title:
ROW AND COLUMN ENABLE SIGNAL ACTIVATION OF PROCESSING ARRAY ELEMENTS WITH INTERCONNECTION LOGIC TO SIMULATE BUS EFFECT
11
Patent #:
Issue Dt:
01/04/2005
Application #:
10413364
Filing Dt:
04/15/2003
Publication #:
Pub Dt:
11/06/2003
Title:
MONOTONIC DYNAMIC STATIC PSEUDO-NMOS LOGIC CIRCUITS
12
Patent #:
Issue Dt:
06/08/2004
Application #:
10413858
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
09/18/2003
Title:
GATE COUPLED VOLTAGE SUPPORT FOR AN OUTPUT DRIVER CIRCUIT
13
Patent #:
Issue Dt:
08/17/2004
Application #:
10413864
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
09/18/2003
Title:
FUSE READ SEQUENCE FOR AUTO REFRESH POWER REDUCTION
14
Patent #:
Issue Dt:
04/19/2005
Application #:
10413865
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
09/18/2003
Title:
SUPPORT RING FOR USE WITH A CONTACT PAD AND SEMICONDUCTOR DEVICE COMPONENTS INCLUDING THE SAME
15
Patent #:
Issue Dt:
05/25/2004
Application #:
10414147
Filing Dt:
04/15/2003
Title:
SURFACE BARRIERS FOR COPPER AND SILVER INTERCONNECTS
16
Patent #:
Issue Dt:
11/09/2004
Application #:
10414318
Filing Dt:
04/15/2003
Publication #:
Pub Dt:
10/30/2003
Title:
MEMORY DEVICE WITH MULTI-LEVEL STORAGE CELLS
17
Patent #:
Issue Dt:
01/25/2005
Application #:
10414818
Filing Dt:
04/15/2003
Publication #:
Pub Dt:
01/22/2004
Title:
COLUMN ADDRESS PATH CIRCUIT AND METHOD FOR MEMORY DEVICES HAVING A BURST ACCESS MODE
18
Patent #:
Issue Dt:
05/24/2005
Application #:
10417056
Filing Dt:
04/16/2003
Publication #:
Pub Dt:
02/19/2004
Title:
METHOD OF PACKAGING SEMICONDUCTOR DICE EMPLOYING AT LEAST ONE REDISTRIBUTION LAYER
19
Patent #:
Issue Dt:
03/29/2005
Application #:
10417119
Filing Dt:
04/17/2003
Publication #:
Pub Dt:
10/30/2003
Title:
FABRICATION OF SEMICONDUCTOR DEVICES WITH TRANSITION METAL BORIDE FILMS AS DIFFUSION BARRIERS
20
Patent #:
Issue Dt:
05/31/2005
Application #:
10417416
Filing Dt:
04/15/2003
Publication #:
Pub Dt:
12/18/2003
Title:
SELF-REPAIR METHOD VIA ECC FOR NONVOLATILE MEMORY DEVICES, AND RELATIVE NONVOLATILE MEMORY DEVICE
21
Patent #:
Issue Dt:
09/14/2004
Application #:
10418406
Filing Dt:
04/18/2003
Publication #:
Pub Dt:
11/06/2003
Title:
MAGNETORESISTIVE MEMORY DEVICES AND ASSEMBLIES; AND METHODS OF STORING AND RETRIEVING INFORMATION
22
Patent #:
Issue Dt:
09/28/2004
Application #:
10418530
Filing Dt:
04/17/2003
Publication #:
Pub Dt:
10/16/2003
Title:
METAL STRUCTURE FOR A PHASE-CHANGE MEMORY DEVICE
23
Patent #:
Issue Dt:
06/28/2005
Application #:
10418696
Filing Dt:
04/18/2003
Publication #:
Pub Dt:
10/21/2004
Title:
METHODS OF FORMING SEMICONDUCTIVE MATERIALS HAVING FLATTENED SURFACES; METHODS OF FORMING ISOLATION REGIONS; AND METHODS OF FORMING ELEVATED SOURCE/DRAIN REGIONS
24
Patent #:
Issue Dt:
08/16/2005
Application #:
10418945
Filing Dt:
04/18/2003
Publication #:
Pub Dt:
02/19/2004
Title:
SYSTEM AND METHOD FOR POWER SAVING MEMORY REFRESH FOR DYNAMIC RANDOM ACCESS MEMORY DEVICES AFTER AN EXTENDED INTERVAL
25
Patent #:
Issue Dt:
10/26/2010
Application #:
10419235
Filing Dt:
04/21/2003
Publication #:
Pub Dt:
10/21/2004
Title:
MULTI PATH POWER FOR CMOS IMAGERS
26
Patent #:
Issue Dt:
03/29/2005
Application #:
10419592
Filing Dt:
04/21/2003
Publication #:
Pub Dt:
11/13/2003
Title:
METHODS FOR PREPARING RUTHENIUM AND OSMIUM COMPOUNDS AND FILMS
27
Patent #:
Issue Dt:
08/16/2005
Application #:
10420246
Filing Dt:
04/21/2003
Publication #:
Pub Dt:
10/21/2004
Title:
METHOD OF DEPOSITING A SILICON DIOXIDE COMPRISING LAYER DOPED WITH AT LEAST ONE OF P, B AND GE
28
Patent #:
Issue Dt:
02/27/2007
Application #:
10420307
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
ATOMIC LAYER DEPOSITED ZRTIO4 FILMS
29
Patent #:
Issue Dt:
11/20/2007
Application #:
10420331
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
Method for controlling diffusion in semiconductor regions
30
Patent #:
Issue Dt:
12/12/2006
Application #:
10420435
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/30/2003
Title:
AUTOMATED LOAD DETERMINATION FOR PARTITIONED SIMULATION
31
Patent #:
Issue Dt:
12/07/2004
Application #:
10420533
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
12/04/2003
Title:
ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY COMPRISING AN INTERNAL SUPPLY VOLTAGE MANAGEMENT DEVICE
32
Patent #:
Issue Dt:
01/10/2006
Application #:
10421133
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
09/25/2003
Title:
A SEMICONDUCTOR PACKAGE HAVING A PARTIAL SLOT COVER FOR ENCAPSULATION PROCESS
33
Patent #:
Issue Dt:
05/23/2006
Application #:
10421157
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
10/28/2004
Title:
POLYMER-BASED FERROELECTRIC MEMORY
34
Patent #:
Issue Dt:
02/14/2006
Application #:
10421201
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
INTEGRATED CIRCUIT INCLUDING SENSOR TO SENSE ENVIRONMENTAL DATA, METHOD OF COMPENSATING AN MRAM INTEGRATED CIRCUIT FOR THE EFFECTS OF AN EXTERNAL MAGNETIC FIELD, MRAM INTEGRATED CIRCUIT, AND METHOD OF TESTING
35
Patent #:
Issue Dt:
05/01/2007
Application #:
10421287
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
SYSTEM AND METHOD TO INITIALIZE REGISTERS WITH AN EEPROM STORED BOOT SEQUENCE
36
Patent #:
Issue Dt:
12/25/2007
Application #:
10421452
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES
37
Patent #:
Issue Dt:
03/16/2004
Application #:
10422251
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
10/30/2003
Title:
METHOD OF FABRICATING STACKED DIE CONFIGURATIONS UTILIZING REDISTRIBUTION BOND PADS
38
Patent #:
Issue Dt:
05/25/2004
Application #:
10422849
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
10/23/2003
Title:
SENSING METHOD AND APPARATUS FOR RESISTANCE MEMORY DEVICE
39
Patent #:
Issue Dt:
02/15/2005
Application #:
10422850
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
02/12/2004
Title:
OFFSET COMPENSATED SENSING FOR MAGNETIC RANDOM ACCESS MEMORY
40
Patent #:
Issue Dt:
06/24/2008
Application #:
10422965
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
02/03/2005
Title:
IMAGER FLOATING DIFFUSION REGION AND PROCESS FOR FORMING SAME
41
Patent #:
Issue Dt:
04/19/2005
Application #:
10423124
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
11/06/2003
Title:
METHOD OF FORMING AN ELECTRICAL CONTACT
42
Patent #:
Issue Dt:
05/24/2005
Application #:
10423241
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
10/30/2003
Title:
TEST SYSTEM FOR SILICON HAVING ELECTRICAL CONTACTS
43
Patent #:
Issue Dt:
02/26/2008
Application #:
10423711
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
11/18/2004
Title:
METHODS FOR CONTROLLING MASS FLOW RATES AND PRESSURES IN PASSAGEWAYS COUPLED TO REACTION CHAMBERS AND SYSTEMS FOR DEPOSITING MATERIAL ONTO MICROFEATURE WORKPIECES IN REACTION CHAMBERS
44
Patent #:
Issue Dt:
07/26/2005
Application #:
10423845
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
12/25/2003
Title:
SELF-REPAIR METHOD FOR NONVOLATILE MEMORY DEVICES USING A SUPERSECURE ARCHITECTURE, AND NONVOLATILE MEMORY DEVICE
45
Patent #:
Issue Dt:
04/21/2015
Application #:
10424206
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
10/28/2004
Title:
Active memory data compression system and method
46
Patent #:
Issue Dt:
02/19/2008
Application #:
10424426
Filing Dt:
04/28/2003
Publication #:
Pub Dt:
11/06/2003
Title:
STACKED DIE IN DIE BGA PACKAGE
47
Patent #:
Issue Dt:
03/18/2008
Application #:
10424470
Filing Dt:
04/28/2003
Publication #:
Pub Dt:
11/06/2003
Title:
STACKED DIE IN DIE BGA PACKAGE
48
Patent #:
Issue Dt:
01/04/2005
Application #:
10425069
Filing Dt:
04/28/2003
Publication #:
Pub Dt:
10/28/2004
Title:
METHOD AND APPARATUS FOR IMPROVING STABILITY AND LOCK TIME FOR SYNCHRONOUS CIRCUITS
49
Patent #:
Issue Dt:
11/30/2004
Application #:
10425130
Filing Dt:
04/28/2003
Publication #:
Pub Dt:
10/02/2003
Title:
METHODS OF FABRICATING BURIED DIGIT LINES
50
Patent #:
Issue Dt:
07/06/2004
Application #:
10425378
Filing Dt:
04/28/2003
Publication #:
Pub Dt:
10/30/2003
Title:
CONSTRUCTIONS COMPRISING SOLDER BUMPS
51
Patent #:
Issue Dt:
05/03/2005
Application #:
10425483
Filing Dt:
04/29/2003
Publication #:
Pub Dt:
03/04/2004
Title:
ONE TRANSISTOR SOI NON-VOLATILE RANDOM ACCESS MEMORY CELL
52
Patent #:
Issue Dt:
05/22/2007
Application #:
10425484
Filing Dt:
04/29/2003
Publication #:
Pub Dt:
11/04/2004
Title:
STRAINED SEMICONDUCTOR BY WAFER BONDING WITH MISORIENTATION
53
Patent #:
Issue Dt:
05/09/2006
Application #:
10425797
Filing Dt:
04/29/2003
Publication #:
Pub Dt:
11/04/2004
Title:
LOCALIZED STRAINED SEMICONDUCTOR ON INSULATOR
54
Patent #:
Issue Dt:
06/21/2005
Application #:
10426380
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
10/30/2003
Title:
PHASE CHANGE MATERIAL MEMORY DEVICE
55
Patent #:
Issue Dt:
07/27/2004
Application #:
10426571
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
08/28/2003
Title:
COUPLING SPACED BOND PADS TO A CONTACT
56
Patent #:
Issue Dt:
11/30/2004
Application #:
10426924
Filing Dt:
04/29/2003
Publication #:
Pub Dt:
12/25/2003
Title:
METHOD FOR REDUCING SPURIOUS ERASING DURING PROGRAMMING OF A NONVOLATILE NROM
57
Patent #:
Issue Dt:
01/11/2005
Application #:
10427163
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
11/04/2004
Title:
STROBE THROUGH DIFFERENTIAL SIGNALING
58
Patent #:
Issue Dt:
06/17/2008
Application #:
10427168
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
06/17/2004
Title:
INTERCONNECTION DESIGNS AND MATERIALS HAVING IMPROVED STRENGTH AND FATIGUE LIFE
59
Patent #:
Issue Dt:
08/17/2004
Application #:
10427559
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
01/08/2004
Title:
METHODS OF FORMING PROGRAMMABLE MEMORY DEVICES COMPRISING TUNGSTEN
60
Patent #:
Issue Dt:
08/17/2004
Application #:
10428040
Filing Dt:
04/30/2003
Title:
METHOD AND CIRCUIT FOR ADJUSTING A VOLTAGE UPON DETECTION OF A COMMAND APPLIED TO AN INTEGRATED CIRCUIT
61
Patent #:
Issue Dt:
08/31/2004
Application #:
10428449
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
11/06/2003
Title:
MICROELECTRONIC DIE INCLUDING LOW RC UNDER-LAYER INTERCONNECTS
62
Patent #:
Issue Dt:
11/30/2004
Application #:
10429373
Filing Dt:
05/05/2003
Publication #:
Pub Dt:
10/30/2003
Title:
MULTIPLE VOLTAGE SUPPLY SWITCH
63
Patent #:
Issue Dt:
09/06/2005
Application #:
10430616
Filing Dt:
05/05/2003
Publication #:
Pub Dt:
10/23/2003
Title:
USE OF PALLADIUM IN IC MANUFACTURING WITH CONDUCTIVE POLYMER BUMP
64
Patent #:
Issue Dt:
05/03/2005
Application #:
10431061
Filing Dt:
05/07/2003
Publication #:
Pub Dt:
10/23/2003
Title:
METHOD OF FORMING A CONDUCTIVE CONTACT
65
Patent #:
Issue Dt:
01/17/2006
Application #:
10431134
Filing Dt:
05/07/2003
Publication #:
Pub Dt:
11/11/2004
Title:
STRAINED SI/SIGE STRUCTURES BY ION IMPLANTATION
66
Patent #:
Issue Dt:
10/03/2006
Application #:
10431137
Filing Dt:
05/07/2003
Publication #:
Pub Dt:
11/11/2004
Title:
MICROMECHANICAL STRAINED SEMICONDUCTOR BY WAFER BONDING
67
Patent #:
Issue Dt:
05/29/2007
Application #:
10431397
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
WIDE DYNAMIC RANGE ACTIVE PIXEL WITH KNEE RESPONSE
68
Patent #:
Issue Dt:
11/23/2004
Application #:
10431718
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
SYNCHRONOUS UP/DOWN ADDRESS GENERATOR FOR BURST MODE READ
69
Patent #:
Issue Dt:
12/26/2006
Application #:
10431748
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
METHOD FOR READING WHILE WRITING TO A SINGLE PARTITION FLASH MEMORY
70
Patent #:
Issue Dt:
05/10/2005
Application #:
10431749
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
POSITION BASED ERASE VERIFICATION LEVELS IN A FLASH MEMORY DEVICE
71
Patent #:
Issue Dt:
06/24/2008
Application #:
10431767
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/25/2004
Title:
PROGRAM FAILURE RECOVERY
72
Patent #:
Issue Dt:
12/26/2006
Application #:
10431768
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
AUTOMATIC TEST ENTRY TERMINATION IN A MEMORY DEVICE
73
Patent #:
Issue Dt:
03/30/2004
Application #:
10431822
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
10/30/2003
Title:
SEMICONDUCTOR PROCESSING METHOD
74
Patent #:
Issue Dt:
04/10/2007
Application #:
10431889
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
12/02/2004
Title:
ERROR DETECTION, DOCUMENTATION, AND CORRECTION IN A FLASH MEMORY DEVICE
75
Patent #:
Issue Dt:
05/03/2005
Application #:
10434087
Filing Dt:
05/09/2003
Publication #:
Pub Dt:
11/11/2004
Title:
SKEWED SENSE AMP FOR VARIABLE RESISTANCE MEMORY SENSING
76
Patent #:
Issue Dt:
09/19/2006
Application #:
10434380
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
12/18/2003
Title:
METHOD OF PROCESSING A STRIP OF LEAD FRAMES
77
Patent #:
Issue Dt:
01/03/2006
Application #:
10434578
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES
78
Patent #:
Issue Dt:
08/16/2005
Application #:
10435048
Filing Dt:
05/12/2003
Publication #:
Pub Dt:
12/18/2003
Title:
PHOTO-ASSISTED METHOD FOR SEMICONDUCTOR FABRICATION
79
Patent #:
Issue Dt:
01/04/2005
Application #:
10435049
Filing Dt:
05/12/2003
Publication #:
Pub Dt:
11/18/2004
Title:
FOLDED DRAM CAM CELL
80
Patent #:
Issue Dt:
08/24/2004
Application #:
10435171
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
10/23/2003
Title:
LOW DIELECTRIC CONSTANT SHALLOW TRENCH ISOLATION
81
Patent #:
Issue Dt:
01/04/2005
Application #:
10435335
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
10/23/2003
Title:
MODULE ASSEMBLY FOR STACKED BGA PACKAGES
82
Patent #:
Issue Dt:
01/04/2005
Application #:
10435336
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
10/30/2003
Title:
APPARATUS ASSOCIATABLE WITH A DEPOSITION CHAMBER TO ENHANCE UNIFORMITY OF PROPERTIES OF MATERIAL LAYERS FORMED ON SEMICONDUCTOR SUBSTRATES THEREIN
83
Patent #:
Issue Dt:
08/10/2004
Application #:
10435423
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
09/18/2003
Title:
METHODS FOR FORMING A SLOT WITH A LATERALLY RECESSED AREA AT AN END THEREOF THROUGH AN INTERPOSER OR OTHER CARRIER SUBSTRATE
84
Patent #:
Issue Dt:
09/06/2005
Application #:
10435569
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
REMOVAL OF CARBON FROM AN INSULATIVE LAYER USING OZONE
85
Patent #:
Issue Dt:
11/30/2004
Application #:
10435590
Filing Dt:
05/12/2003
Publication #:
Pub Dt:
11/20/2003
Title:
SEMICONDUCTOR MEMORY HAVING MULTIPLE REDUNDANT COLUMNS WITH OFFSET SEGMENTATION BOUNDARIES
86
Patent #:
Issue Dt:
06/13/2006
Application #:
10435791
Filing Dt:
05/12/2003
Publication #:
Pub Dt:
11/18/2004
Title:
METHODS OF FORMING INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES USING SPIN-ON, PHOTOPATTERNABLE, INTERLAYER DIELECTRIC MATERIALS
87
Patent #:
Issue Dt:
02/08/2005
Application #:
10436584
Filing Dt:
05/12/2003
Publication #:
Pub Dt:
11/18/2004
Title:
SEMICONDUCTOR COMPONENT HAVING STACKED, ENCAPSULATED DICE
88
Patent #:
Issue Dt:
09/25/2007
Application #:
10436640
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
10/30/2003
Title:
METHODS FOR FORMING PHOSPHORUS- AND/OR BORON-CONTAINING SILICA LAYERS ON SUBSTRATES
89
Patent #:
Issue Dt:
10/14/2008
Application #:
10436775
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
12/02/2004
Title:
TEST SCAN CELLS
90
Patent #:
Issue Dt:
08/09/2005
Application #:
10437214
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
10/30/2003
Title:
PROCESS FOR FABRICATING EXTERNAL CONTACTS ON SEMICONDUCTOR COMPONENTS
91
Patent #:
Issue Dt:
08/24/2004
Application #:
10437354
Filing Dt:
05/12/2003
Publication #:
Pub Dt:
10/30/2003
Title:
ELECTRICAL COMMUNICATION SYSTEM FOR CIRCUITRY
92
Patent #:
Issue Dt:
08/11/2009
Application #:
10438146
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
10/30/2003
Title:
REDUCED AREA INTERSECTION BETWEEN ELECTRODE AND PROGRAMMING ELEMENT
93
Patent #:
Issue Dt:
07/19/2005
Application #:
10438175
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
02/26/2004
Title:
PROGRAMMING METHOD OF THE MEMORY CELLS IN A MULTILEVEL NON-VOLATILE MEMORY DEVICE
94
Patent #:
Issue Dt:
04/05/2005
Application #:
10438360
Filing Dt:
05/14/2003
Publication #:
Pub Dt:
10/23/2003
Title:
ETCH STOP LAYER IN POLY-METAL STRUCTURES
95
Patent #:
Issue Dt:
10/19/2004
Application #:
10438733
Filing Dt:
05/15/2003
Publication #:
Pub Dt:
01/29/2004
Title:
PAGE-ERASABLE FLASH MEMORY
96
Patent #:
Issue Dt:
03/22/2005
Application #:
10439369
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
11/06/2003
Title:
ALIGNMENT AND ORIENTATION FEATURES FOR A SEMICONDUCTOR PACKAGE
97
Patent #:
Issue Dt:
05/11/2004
Application #:
10439729
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
10/23/2003
Title:
6F2 DRAM ARRAY WITH APPARATUS FOR STRESS TESTING AN ISOLATION GATE AND METHOD
98
Patent #:
Issue Dt:
01/04/2005
Application #:
10439774
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
11/06/2003
Title:
METHOD FOR CONTROLLING DEPOSITION OF DIELECTRIC FILMS
99
Patent #:
Issue Dt:
09/13/2005
Application #:
10440043
Filing Dt:
05/15/2003
Publication #:
Pub Dt:
01/15/2004
Title:
SELF-REPAIR METHOD FOR NONVOLATILE MEMORY DEVICES WITH ERASING/PROGRAMMING FAILURE, AND RELATIVE NONVOLATILE MEMORY DEVICE
100
Patent #:
Issue Dt:
01/04/2005
Application #:
10440575
Filing Dt:
05/19/2003
Publication #:
Pub Dt:
10/23/2003
Title:
BI-LEVEL DIGIT LINE ARCHITECTURE FOR HIGH DENSITY DRAMS
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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