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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
08/02/2005
Application #:
10724377
Filing Dt:
11/28/2003
Publication #:
Pub Dt:
07/15/2004
Title:
SEMICONDUCTOR DEVICE
2
Patent #:
Issue Dt:
09/05/2006
Application #:
10724470
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
06/10/2004
Title:
SYSTEM AND METHOD FOR MANAGING A CACHE MEMORY
3
Patent #:
Issue Dt:
10/10/2006
Application #:
10724472
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
06/10/2004
Title:
SYSTEM AND METHOD FOR MANAGING A CACHE MEMORY
4
Patent #:
Issue Dt:
05/06/2008
Application #:
10724534
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
06/10/2004
Title:
SYSTEM AND METHOD FOR MANAGING A CACHE MEMORY
5
Patent #:
Issue Dt:
08/16/2005
Application #:
10724648
Filing Dt:
12/01/2003
Publication #:
Pub Dt:
07/15/2004
Title:
SEMICONDUCTOR DEVICE
6
Patent #:
Issue Dt:
06/13/2006
Application #:
10725481
Filing Dt:
12/03/2003
Publication #:
Pub Dt:
06/10/2004
Title:
INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG
7
Patent #:
Issue Dt:
05/23/2006
Application #:
10725557
Filing Dt:
12/03/2003
Publication #:
Pub Dt:
06/09/2005
Title:
MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF
8
Patent #:
Issue Dt:
05/03/2005
Application #:
10725981
Filing Dt:
12/02/2003
Publication #:
Pub Dt:
06/10/2004
Title:
CIRCUIT BOARD SINGULATION METHODS
9
Patent #:
Issue Dt:
09/13/2005
Application #:
10726265
Filing Dt:
12/02/2003
Publication #:
Pub Dt:
01/13/2005
Title:
HIGH VOLTAGE GENERATION AND REGULATION CIRCUIT IN A MEMORY DEVICE
10
Patent #:
Issue Dt:
08/07/2007
Application #:
10726328
Filing Dt:
12/01/2003
Publication #:
Pub Dt:
06/02/2005
Title:
METHODS OF FORMING PARTICLE-CONTAINING MATERIALS
11
Patent #:
Issue Dt:
09/18/2007
Application #:
10726439
Filing Dt:
12/03/2003
Publication #:
Pub Dt:
06/09/2005
Title:
COMPENSATED REFRESH OSCILLATOR
12
Patent #:
Issue Dt:
11/22/2005
Application #:
10727087
Filing Dt:
12/02/2003
Publication #:
Pub Dt:
01/13/2005
Title:
NO-PRECHARGE FAMOS CELL AND LATCH CIRCUIT IN A MEMORY DEVICE
13
Patent #:
Issue Dt:
09/27/2005
Application #:
10727150
Filing Dt:
12/03/2003
Publication #:
Pub Dt:
07/15/2004
Title:
MEMORY DEVICE COMPOSED OF A PLURALITY OF MEMORY CHIPS IN A SINGLE PACKAGE
14
Patent #:
Issue Dt:
12/19/2006
Application #:
10727341
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
09/29/2005
Title:
NON-VOLATILE MEMORY DEVICE ARCHITECTURE, FOR INSTANCE A FLASH KIND, HAVING A SERIAL COMMUNICATION INTERFACE
15
Patent #:
Issue Dt:
08/09/2005
Application #:
10727478
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
16
Patent #:
Issue Dt:
03/29/2005
Application #:
10727742
Filing Dt:
12/04/2003
Title:
SEMICONDUCTOR DEVICE
17
Patent #:
Issue Dt:
07/12/2005
Application #:
10727887
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
06/10/2004
Title:
HIGH COUPLING FLOATING GATE TRANSISTOR
18
Patent #:
Issue Dt:
03/08/2005
Application #:
10727889
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
06/24/2004
Title:
METHOD AND APPARATUS FOR REDUCING FIXED CHARGE IN SEMICONDUCTOR DEVICE LAYERS
19
Patent #:
Issue Dt:
05/17/2005
Application #:
10728372
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
08/19/2004
Title:
NON-VOLATILE MEMORY CELL SENSING CIRCUIT, PARTICULARLY FOR LOW POWER SUPPLY VOLTAGES AND HIGH CAPACITIVE LOAD VALUES
20
Patent #:
Issue Dt:
12/11/2007
Application #:
10728395
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
06/09/2005
Title:
SMALLER AND LOWER POWER STATIC MUX CIRCUITRY IN GENERATING MULTIPLIER PARTIAL PRODUCT SIGNALS
21
Patent #:
Issue Dt:
09/19/2006
Application #:
10728413
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
04/29/2004
Title:
QUAD FLAT NO LEAD (QFN) GRID ARRAY PACKAGE
22
Patent #:
Issue Dt:
09/11/2007
Application #:
10728526
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
06/17/2004
Title:
METHOD AND APPARATUS FOR CONDITIONING A CHEMICAL-MECHANICAL POLISHING PAD
23
Patent #:
Issue Dt:
12/12/2006
Application #:
10728977
Filing Dt:
12/08/2003
Publication #:
Pub Dt:
06/17/2004
Title:
MEMORY CIRCUITRY AND METHOD OF FORMING MEMORY CIRCUITRY
24
Patent #:
Issue Dt:
07/11/2006
Application #:
10729180
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
06/17/2004
Title:
QUAD FLAT NO-LEAD (QFN) GRID ARRAY PACKAGE, METHOD OF MAKING AND MEMORY MODULE AND COMPUTER SYSTEM INCLUDING SAME
25
Patent #:
Issue Dt:
06/27/2006
Application #:
10729829
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
09/02/2004
Title:
METHOD AND DEVICE FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY
26
Patent #:
Issue Dt:
04/18/2006
Application #:
10729875
Filing Dt:
12/05/2003
Publication #:
Pub Dt:
09/02/2004
Title:
METHOD AND DEVICE FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY
27
Patent #:
Issue Dt:
04/19/2005
Application #:
10730548
Filing Dt:
12/08/2003
Publication #:
Pub Dt:
06/17/2004
Title:
PROBE CARD FOR TESTING MICROELECTRONIC COMPONENTS
28
Patent #:
Issue Dt:
10/11/2005
Application #:
10730641
Filing Dt:
12/08/2003
Publication #:
Pub Dt:
08/05/2004
Title:
A SEMICONDUCTOR DEVICE COMPRISING LOW DIELECTRIC CONSTANT STI WITH SOI DEVICES
29
Patent #:
Issue Dt:
11/28/2006
Application #:
10731177
Filing Dt:
12/09/2003
Publication #:
Pub Dt:
12/30/2004
Title:
WIRE-BONDED PACKAGE WITH ELECTRICALLY INSULATING WIRE ENCAPSULANT AND THERMALLY CONDUCTIVE OVERMOLD
30
Patent #:
Issue Dt:
05/02/2006
Application #:
10731480
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
01/20/2005
Title:
METHOD OF FORMING METAL LINE IN SEMICONDUCTOR DEVICE
31
Patent #:
Issue Dt:
02/20/2007
Application #:
10731567
Filing Dt:
12/08/2003
Publication #:
Pub Dt:
06/09/2005
Title:
METHOD AND APPARATUS FOR PREDICTION FOR FORK AND JOIN INSTRUCTIONS IN SPECULATIVE EXECUTION
32
Patent #:
Issue Dt:
12/20/2005
Application #:
10732962
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
04/14/2005
Title:
EVEN NUCLEATION BETWEEN SILICON AND OXIDE SURFACES FOR THIN SILICON NITRIDE FILM GROWTH
33
Patent #:
Issue Dt:
10/07/2008
Application #:
10733201
Filing Dt:
12/09/2003
Publication #:
Pub Dt:
06/09/2005
Title:
ATOMIC LAYER DEPOSITION METHOD OF DEPOSITING AN OXIDE ON A SUBSTRATE
34
Patent #:
Issue Dt:
12/27/2011
Application #:
10733226
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES
35
Patent #:
Issue Dt:
12/12/2006
Application #:
10733474
Filing Dt:
12/12/2003
Publication #:
Pub Dt:
06/16/2005
Title:
CURRENT MODE LOGIC SCHEME AND CIRCUIT FOR MATCHLINE SENSE AMPLIFIER DESIGN USING CONSTANT CURRENT BIAS CASCODE CURRENT MIRRORS
36
Patent #:
Issue Dt:
08/21/2007
Application #:
10733523
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
METHODS AND SYSTEMS FOR CONTROLLING TEMPERATURE DURING MICROFEATURE WORKPIECE PROCESSING, E.G., CVD DEPOSITION
37
Patent #:
Issue Dt:
09/14/2010
Application #:
10733605
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
06/16/2005
Title:
SWITCHED CAPACITOR FOR A TUNABLE DELAY CIRCUIT
38
Patent #:
Issue Dt:
01/16/2007
Application #:
10733896
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
06/24/2004
Title:
SYSTEM AND METHOD FOR MANIPULATING CACHE DATA
39
Patent #:
Issue Dt:
05/20/2008
Application #:
10734201
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
07/01/2004
Title:
DEVICE HAVING IMPROVED SURFACE PLANARITY PRIOR TO MRAM BIT MATERIAL DEPOSITION
40
Patent #:
Issue Dt:
10/04/2005
Application #:
10734202
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
07/01/2004
Title:
DEVICE WITH LAYER EDGES SEPARATED THROUGH MECHANICAL SPACING
41
Patent #:
Issue Dt:
08/28/2007
Application #:
10734260
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
07/01/2004
Title:
METAL TO POLYSILICON CONTACT IN OXYGEN ENVIRONMENT
42
Patent #:
Issue Dt:
01/03/2006
Application #:
10734339
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
06/16/2005
Title:
DIGITAL FREQUENCY-MULTIPLYING DLLS
43
Patent #:
Issue Dt:
08/30/2005
Application #:
10734438
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
07/01/2004
Title:
BIT LINE CONTACTS
44
Patent #:
Issue Dt:
07/24/2007
Application #:
10734525
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
06/16/2005
Title:
METHOD OF REMOVING RESIDUAL CONTAMINANTS FROM AN ENVIRONMENT
45
Patent #:
Issue Dt:
04/26/2005
Application #:
10734533
Filing Dt:
12/12/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
46
Patent #:
Issue Dt:
04/18/2006
Application #:
10734663
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
07/01/2004
Title:
METHOD FOR MANUFACTURE OF MAGNETO-RESISTIVE BIT STRUCTURE
47
Patent #:
Issue Dt:
09/18/2007
Application #:
10734999
Filing Dt:
12/12/2003
Publication #:
Pub Dt:
07/01/2004
Title:
DEPOSITION METHODS WITH TIME SPACED AND TIME ABUTTING PRECURSOR PULSES
48
Patent #:
Issue Dt:
05/22/2007
Application #:
10735250
Filing Dt:
12/12/2003
Publication #:
Pub Dt:
09/16/2004
Title:
MEMORY SYSTEM COMPRISING A SEMICONDUCTOR MEMORY
49
Patent #:
Issue Dt:
01/10/2006
Application #:
10735355
Filing Dt:
12/12/2003
Publication #:
Pub Dt:
07/01/2004
Title:
WAFER BONDING METHOD OF FORMING SILICON-ON-INSULATOR COMPRISING INTEGRATED CIRCUITRY
50
Patent #:
Issue Dt:
10/03/2006
Application #:
10736244
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
07/01/2004
Title:
SEMICONDUCTOR DEVICES INCLUDING PERIPHERALLY LOCATED BOND PADS, INTERMEDIATES THEREOF, ASSEMBLIES, AND PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES, AND SUPPORT ELEMENTS FOR THE SEMICONDUCTOR DEVICES
51
Patent #:
Issue Dt:
02/14/2006
Application #:
10736617
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
07/01/2004
Title:
NON-VOLATILE RESISTANCE VARIABLE DEVICES
52
Patent #:
Issue Dt:
06/07/2005
Application #:
10736719
Filing Dt:
12/16/2003
Publication #:
Pub Dt:
12/02/2004
Title:
HIGH VOLTAGE TRANSFER CIRCUIT
53
Patent #:
Issue Dt:
01/04/2005
Application #:
10736805
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
07/01/2004
Title:
METHODS OF FORMING ELECTRONIC COMPONENTS, AND A CONDUCTIVE LINE
54
Patent #:
Issue Dt:
05/22/2007
Application #:
10738408
Filing Dt:
12/16/2003
Publication #:
Pub Dt:
07/08/2004
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
55
Patent #:
Issue Dt:
12/12/2006
Application #:
10738556
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
06/23/2005
Title:
VERTICAL NAND FLASH MEMORY ARRAY
56
Patent #:
Issue Dt:
07/10/2007
Application #:
10738783
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
06/23/2005
Title:
VERTICAL NROM NAND FLASH MEMORY ARRAY
57
Patent #:
Issue Dt:
02/13/2007
Application #:
10738827
Filing Dt:
12/16/2003
Publication #:
Pub Dt:
07/08/2004
Title:
SMALL SCALE ACTUATORS AND METHODS FOR THEIR FORMATION AND USE
58
Patent #:
Issue Dt:
01/02/2007
Application #:
10739253
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
06/23/2005
Title:
FLASH MEMORY HAVING A HIGH-PERMITTIVITY TUNNEL DIELECTRIC
59
Patent #:
Issue Dt:
11/07/2006
Application #:
10739767
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
07/08/2004
Title:
WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS
60
Patent #:
Issue Dt:
09/06/2005
Application #:
10739928
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
08/26/2004
Title:
NON-VOLATILE MEMORY DEVICE WITH IMPROVED SEQUENTIAL PROGRAMMING SPEED
61
Patent #:
Issue Dt:
07/04/2006
Application #:
10740100
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD FOR READING FLASH MEMORY CELL, NAND-TYPE FLASH MEMORY APPARATUS, AND NOR-TYPE FLASH MEMORY APPARATUS
62
Patent #:
Issue Dt:
07/04/2006
Application #:
10741100
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
07/08/2004
Title:
AIR SOCKET FOR TESTING INTEGRATED CIRCUITS
63
Patent #:
Issue Dt:
05/01/2012
Application #:
10741129
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
03/10/2005
Title:
FASTER WRITE OPERATIONS TO NONVOLATILE MEMORY USING FSINFO SECTOR MANIPULATION
64
Patent #:
Issue Dt:
10/17/2006
Application #:
10741774
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
06/23/2005
Title:
COLOR IMAGE SENSOR WITH IMAGING ELEMENTS IMAGING ON RESPECTIVE REGIONS OF SENSOR ELEMENTS
65
Patent #:
Issue Dt:
08/23/2005
Application #:
10741804
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
08/19/2004
Title:
SEMICONDUCTOR DEVICE
66
Patent #:
Issue Dt:
01/13/2009
Application #:
10741815
Filing Dt:
12/18/2003
Publication #:
Pub Dt:
09/09/2004
Title:
STRUCTURE AND METHOD FOR DETECTING ERRORS IN A MULTILEVEL MEMORY DEVICE WITH IMPROVED PROGRAMMING GRANULARITY
67
Patent #:
Issue Dt:
10/11/2005
Application #:
10742181
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
07/08/2004
Title:
STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
68
Patent #:
Issue Dt:
07/04/2006
Application #:
10742429
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
07/08/2004
Title:
STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
69
Patent #:
Issue Dt:
05/05/2009
Application #:
10744206
Filing Dt:
12/22/2003
Publication #:
Pub Dt:
06/23/2005
Title:
CLOCK SIGNAL DISTRIBUTION WITH REDUCED PARASITIC LOADING EFFECTS
70
Patent #:
Issue Dt:
10/12/2004
Application #:
10744495
Filing Dt:
12/23/2003
Title:
METHOD OF FORMING GATE ELECTRODE IN FLASH MEMORY DEVICE
71
Patent #:
Issue Dt:
05/11/2010
Application #:
10744632
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
11/11/2004
Title:
METHOD FOR PACKAGING CIRCUITS AND PACKAGED CIRCUITS
72
Patent #:
Issue Dt:
10/30/2007
Application #:
10744664
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
06/23/2005
Title:
REWRITABLE FUSE MEMORY
73
Patent #:
Issue Dt:
08/22/2006
Application #:
10744778
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
07/15/2004
Title:
SENDING SIGNAL THROUGH INTEGRATED CIRCUIT DURING SETUP TIME
74
Patent #:
Issue Dt:
06/21/2005
Application #:
10744931
Filing Dt:
12/22/2003
Publication #:
Pub Dt:
09/16/2004
Title:
METHODS FOR FORMING WORDLINES, TRANSISTOR GATES, AND CONDUCTIVE INTERCONNECTS, AND WORDLINE, TRANSISTOR GATE, AND CONDUCTIVE INTERCONNECT STRUCTURES
75
Patent #:
Issue Dt:
05/01/2007
Application #:
10745008
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
05/19/2005
Title:
METHOD OF MANUFACTURING FLASH MEMORY DEVICE
76
Patent #:
Issue Dt:
07/05/2005
Application #:
10745040
Filing Dt:
12/22/2003
Publication #:
Pub Dt:
07/15/2004
Title:
SEMICONDUCTOR COMPONENT WITH ELECTRICAL CHARACTERISTIC ADJUSTMENT CIRCUITRY
77
Patent #:
Issue Dt:
04/04/2006
Application #:
10745295
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
09/30/2004
Title:
MOS DEVICE AND PROCESS FOR MANUFACTURING MOS DEVICES USING DUAL-POLYSILICON LAYER TECHNOLOGY
78
Patent #:
Issue Dt:
08/15/2006
Application #:
10745297
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
06/02/2005
Title:
MOS DEVICE AND A PROCESS FOR MANUFACTURING MOS DEVICES USING A DUAL-POLYSILICON LAYER TECHNOLOGY WITH SIDE CONTACT
79
Patent #:
Issue Dt:
03/27/2007
Application #:
10745311
Filing Dt:
12/22/2003
Publication #:
Pub Dt:
07/15/2004
Title:
METHOD AND APPARATUS FOR A DEPOSITED FILL LAYER
80
Patent #:
Issue Dt:
07/04/2006
Application #:
10745531
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
07/07/2005
Title:
MAGNETIC MEMORY HAVING SYNTHETIC ANTIFERROMAGNETIC PINNED LAYER
81
Patent #:
Issue Dt:
11/17/2009
Application #:
10745611
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
07/07/2005
Title:
POWER SAVINGS WITH MULTIPLE READOUT CIRCUITS
82
Patent #:
Issue Dt:
04/17/2007
Application #:
10745903
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
07/15/2004
Title:
BUNDLE SKEW MANAGEMENT AND CELL SYNCHRONIZATION
83
Patent #:
Issue Dt:
09/07/2004
Application #:
10746095
Filing Dt:
12/26/2003
Title:
COMPACT DECODE AND MULTIPLEXING CIRCUITRY FOR A MULTI-PORT MEMORY HAVING A COMMON MEMORY INTERFACE
84
Patent #:
Issue Dt:
04/04/2006
Application #:
10746555
Filing Dt:
12/24/2003
Publication #:
Pub Dt:
09/30/2004
Title:
SEMICONDUCTOR MEMORY SYSTEM INCLUDING SELECTION TRANSISTORS
85
Patent #:
Issue Dt:
10/24/2006
Application #:
10746878
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
10/14/2004
Title:
METHOD FOR MANUFACTURING NON-VOLATILE MEMORY CELLS ON A SEMICONDUCTOR SUBSTRATE
86
Patent #:
Issue Dt:
04/17/2007
Application #:
10746975
Filing Dt:
12/24/2003
Publication #:
Pub Dt:
07/07/2005
Title:
SECURE BOOTING AND PROVISIONING
87
Patent #:
Issue Dt:
06/14/2005
Application #:
10747586
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
07/22/2004
Title:
SOI DEVICE WITH REDUCED DRAIN INDUCED BARRIER LOWERING
88
Patent #:
Issue Dt:
01/30/2007
Application #:
10747625
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
07/07/2005
Title:
PREDICTIVE FILTERING OF REGISTER CACHE ENTRY
89
Patent #:
Issue Dt:
02/12/2008
Application #:
10747917
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
07/07/2005
Title:
SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES
90
Patent #:
Issue Dt:
04/26/2005
Application #:
10748447
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
02/24/2005
Title:
FAST PAGE PROGRAMMING ARCHITECTURE AND METHOD IN A NON-VOLATILE MEMORY DEVICE WITH AN SPI INTERFACE
91
Patent #:
Issue Dt:
04/25/2006
Application #:
10748696
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
09/02/2004
Title:
NON VOLATILE MEMORY DEVICE INCLUDING A PREDETERMINED NUMBER OF SECTORS
92
Patent #:
Issue Dt:
05/24/2005
Application #:
10748697
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
10/14/2004
Title:
VOLTAGE SUPPLY DISTRIBUTION ARCHITECTURE FOR A PLURALITY OF MEMORY MODULES
93
Patent #:
Issue Dt:
04/18/2006
Application #:
10748701
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
10/28/2004
Title:
STABILIZATION METHOD FOR DRAIN VOLTAGE IN NON-VOLATILE MULTI-LEVEL MEMORY CELLS AND RELATED MEMORY DEVICE
94
Patent #:
Issue Dt:
04/11/2006
Application #:
10748732
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
07/07/2005
Title:
ACCESS CIRCUIT AND METHOD FOR ALLOWING EXTERNAL TEST VOLTAGE TO BE APPLIED TO ISOLATED WELLS
95
Patent #:
Issue Dt:
10/24/2006
Application #:
10749020
Filing Dt:
12/29/2003
Publication #:
Pub Dt:
10/21/2004
Title:
METHOD FOR MANUFACTURING NON-VOLATILE MEMORY CELLS ON A SEMICONDUCTIVE SUBSTRATE
96
Patent #:
Issue Dt:
06/07/2005
Application #:
10749659
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
08/05/2004
Title:
SILICON-ON-INSULATOR COMPRISING INTEGRATED CIRCUITRY
97
Patent #:
Issue Dt:
09/13/2005
Application #:
10750736
Filing Dt:
12/31/2003
Publication #:
Pub Dt:
06/30/2005
Title:
DIGITAL SWITCHING TECHNIQUE FOR DETECTING DATA
98
Patent #:
Issue Dt:
12/27/2005
Application #:
10750737
Filing Dt:
12/31/2003
Publication #:
Pub Dt:
06/30/2005
Title:
MEMORY CELL HAVING IMPROVED INTERCONNECT
99
Patent #:
Issue Dt:
06/12/2007
Application #:
10751141
Filing Dt:
12/31/2003
Publication #:
Pub Dt:
07/07/2005
Title:
TRANSISTOR HAVING VERTICAL JUNCTION EDGE AND METHOD OF MANUFACTURING THE SAME
100
Patent #:
Issue Dt:
01/13/2009
Application #:
10751441
Filing Dt:
01/06/2004
Publication #:
Pub Dt:
07/14/2005
Title:
DIE PACKAGE HAVING AN ADHESIVE FLOW RESTRICTION AREA
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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