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Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
05/16/2006
Application #:
10875453
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
11/25/2004
Title:
FLASH MEMORY
2
Patent #:
Issue Dt:
02/20/2007
Application #:
10875534
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
03/03/2005
Title:
PERMEABLE CAPACITOR ELECTRODE
3
Patent #:
Issue Dt:
08/29/2006
Application #:
10876184
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
11/25/2004
Title:
METHODS FOR ERASING FLASH MEMORY
4
Patent #:
Issue Dt:
10/24/2006
Application #:
10876333
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
06/16/2005
Title:
METHOD OF FORMING ISOLATION FILM IN SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
06/28/2005
Application #:
10876664
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
11/25/2004
Title:
CHALCOGENIDE GLASS CONSTANT CURRENT DEVICE, AND ITS METHOD OF FABRICATION AND OPERATION
6
Patent #:
Issue Dt:
04/24/2007
Application #:
10876703
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
12/02/2004
Title:
CHEMICAL VAPOR DEPOSITION METHODS OF FORMING BARIUM STRONTIUM TITANATE COMPRISING DIELECTRIC LAYERS, INCLUDING SUCH LAYERS HAVING A VARIED CONCENTRATION OF BARIUM AND STRONTIUM WITHIN THE LAYER
7
Patent #:
Issue Dt:
02/26/2008
Application #:
10876878
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
12/29/2005
Title:
HANDLING DEFECTIVE MEMORY BLOCKS OF NAND MEMORY DEVICES
8
Patent #:
Issue Dt:
12/26/2006
Application #:
10877394
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
12/29/2005
Title:
CHARGE PUMP CIRCUITRY HAVING ADJUSTABLE CURRENT OUTPUTS
9
Patent #:
Issue Dt:
01/09/2007
Application #:
10877576
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
01/27/2005
Title:
SYNCHRONOUS FLASH MEMORY COMMAND SEQUENCE
10
Patent #:
Issue Dt:
09/13/2005
Application #:
10877634
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
11/18/2004
Title:
METHOD, APPARATUS, AND SYSTEM TO ENHANCE NEGATIVE VOLTAGE SWITCHING
11
Patent #:
Issue Dt:
03/04/2008
Application #:
10877720
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
12/29/2005
Title:
LOW POWER COST-EFFECTIVE ECC MEMORY SYSTEM AND METHOD
12
Patent #:
Issue Dt:
10/25/2005
Application #:
10878056
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
11/25/2004
Title:
CURRENT SWITCHING SENSOR DETECTOR
13
Patent #:
Issue Dt:
04/25/2006
Application #:
10878273
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
05/19/2005
Title:
HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
14
Patent #:
Issue Dt:
09/04/2007
Application #:
10878569
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
11/25/2004
Title:
FORMING OXIDE BUFFER LAYER FOR IMPROVED MAGNETIC TUNNEL JUNCTIONS
15
Patent #:
Issue Dt:
03/25/2008
Application #:
10878799
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
12/29/2005
Title:
FORMATION OF MEMORY CELLS AND SELECT GATES OF NAND MEMORY ARRAYS
16
Patent #:
Issue Dt:
02/19/2008
Application #:
10878805
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
12/29/2005
Title:
ISOLATION TRENCHES FOR MEMORY DEVICES
17
Patent #:
Issue Dt:
04/05/2011
Application #:
10879170
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/19/2006
Title:
SHIELDING BLACK REFERENCE PIXELS IN IMAGE SENSORS
18
Patent #:
Issue Dt:
08/23/2005
Application #:
10879366
Filing Dt:
06/28/2004
Title:
METHODS OF FORMING CONDUCTIVE INERCONNECTS, AND METHODS OF DEPOSITING NICKEL
19
Patent #:
Issue Dt:
10/10/2006
Application #:
10879367
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
12/29/2005
Title:
METHODS OF FORMING PATTERNED PHOTORESIST LAYERS OVER SEMICONDUCTOR SUBSTRATES
20
Patent #:
Issue Dt:
08/22/2006
Application #:
10879372
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
12/29/2005
Title:
SEMICONDUCTOR CONSTRUCTIONS
21
Patent #:
Issue Dt:
03/21/2006
Application #:
10879434
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
04/07/2005
Title:
CIRCUIT OF REDUNDANCY IO FUSE IN SEMICONDUCTOR DEVICE
22
Patent #:
Issue Dt:
05/30/2006
Application #:
10879848
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
06/09/2005
Title:
HIGH VOLTAGE SWITCH CIRCUIT
23
Patent #:
Issue Dt:
03/01/2011
Application #:
10880646
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
TRANSPARENT CONDUCTOR BASED PINNED PHOTODIODE
24
Patent #:
Issue Dt:
04/15/2008
Application #:
10880692
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
PROVIDING CURRENT FOR PHASE CHANGE MEMORIES
25
Patent #:
Issue Dt:
10/10/2006
Application #:
10880886
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/30/2004
Title:
ION-ASSISTED OXIDATION METHODS AND THE RESULTING STRUCTURES
26
Patent #:
Issue Dt:
02/05/2008
Application #:
10880988
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
INTERCONNECT STRUCTURE IN INTEGRATED CIRCUITS
27
Patent #:
Issue Dt:
10/17/2006
Application #:
10881002
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CAPACITOR LAYOUT TECHNIQUE FOR REDUCTION OF FIXED PATTERN NOISE IN A CMOS SENSOR
28
Patent #:
Issue Dt:
04/24/2007
Application #:
10881042
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
FLASH MEMORY CELLS WITH REDUCED DISTANCES BETWEEN CELL ELEMENTS
29
Patent #:
Issue Dt:
05/03/2005
Application #:
10881630
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/02/2004
Title:
CONDUCTOR LAYER NITRIDATION
30
Patent #:
Issue Dt:
09/25/2007
Application #:
10881636
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
REDUCTION OF ADJACENT FLOATING GATE DATA PATTERN SENSITIVITY
31
Patent #:
Issue Dt:
10/14/2008
Application #:
10881662
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
FLASH MEMORY WITH METAL-INSULATOR-METAL TUNNELING PROGRAM AND ERASE
32
Patent #:
Issue Dt:
01/29/2008
Application #:
10881664
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
INITIALIZING PHASE CHANGE MEMORIES
33
Patent #:
Issue Dt:
01/29/2008
Application #:
10881874
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/29/2005
Title:
SEMICONDUCTOR CONSTRUCTIONS COMPRISING CERIUM OXIDE AND TITANIUM OXIDE
34
Patent #:
Issue Dt:
12/19/2006
Application #:
10882563
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
Transistor structures and transistors with a germanium-containing channel
35
Patent #:
Issue Dt:
06/06/2006
Application #:
10882969
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/02/2004
Title:
EDGE INTENSIVE ANTIFUSE
36
Patent #:
Issue Dt:
06/26/2007
Application #:
10882987
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/02/2004
Title:
EDGE INTENSIVE ANTIFUSE AND METHOD FOR MAKING THE SAME
37
Patent #:
Issue Dt:
04/21/2009
Application #:
10883191
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
LOW TEMPERATURE PROCESS FOR POLYSILAZANE OXIDATION/DENSIFICATION
38
Patent #:
Issue Dt:
01/06/2009
Application #:
10883215
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD FOR FORMING CONTROLLED GEOMETRY HARDMASKS INCLUDING SUBRESOLUTION ELEMENTS
39
Patent #:
Issue Dt:
05/09/2006
Application #:
10883279
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
03/03/2005
Title:
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
40
Patent #:
Issue Dt:
02/20/2007
Application #:
10883522
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
12/02/2004
Title:
SEMICONDUCTOR DAMASCENE TRENCH AND METHODS THEREOF
41
Patent #:
Issue Dt:
10/09/2007
Application #:
10883601
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/06/2005
Title:
EDGE INTENSIVE ANTIFUSE AND METHOD FOR MAKING THE SAME
42
Patent #:
Issue Dt:
08/08/2006
Application #:
10884044
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
12/30/2004
Title:
METHODS OF FORMING LAYERS OVER SUBSTRATES
43
Patent #:
Issue Dt:
02/26/2008
Application #:
10884481
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
01/27/2005
Title:
INTEGRATED CIRCUIT DEVICE, AND METHOD OF FABRICATING SAME
44
Patent #:
Issue Dt:
10/11/2011
Application #:
10885650
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
01/12/2006
Title:
DEUTERATED STRUCTURES FOR IMAGE SENSORS AND METHODS FOR FORMING THE SAME
45
Patent #:
Issue Dt:
07/27/2010
Application #:
10885821
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
01/12/2006
Title:
PRIORITIZATION OF NETWORK TRAFFIC
46
Patent #:
Issue Dt:
04/18/2006
Application #:
10885933
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
12/30/2004
Title:
SEMICONDUCTOR CONSTRUCTIONS AND ELECTRONIC SYSTEMS COMPRISING METAL SILICIDE
47
Patent #:
Issue Dt:
04/14/2009
Application #:
10886003
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD OF GENERATING AN ENABLE SIGNAL OF A STANDARD MEMORY CORE AND RELATIVE MEMORY DEVICE
48
Patent #:
Issue Dt:
09/25/2007
Application #:
10886063
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD AND SYSTEM FOR DYNAMICALLY OPERATING MEMORY IN A POWER-SAVING ERROR CORRECTING MODE
49
Patent #:
Issue Dt:
12/26/2006
Application #:
10886078
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
01/12/2006
Title:
USE OF SELECTIVE EPITAXIAL SILICON GROWTH IN FORMATION OF FLOATING GATES
50
Patent #:
Issue Dt:
12/02/2008
Application #:
10886676
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD OF MANUFACTURE OF A PCRAM MEMORY CELL
51
Patent #:
Issue Dt:
12/12/2006
Application #:
10886771
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
01/12/2006
Title:
POWER SUPPLY VOLTAGE DETECTION CIRCUITRY AND METHODS FOR USE OF THE SAME
52
Patent #:
Issue Dt:
06/14/2005
Application #:
10886958
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
12/02/2004
Title:
MAGNETIC MEMORY CELL WITH SHAPE ANISOTROPY AND MEMORY DEVICE THEREOF
53
Patent #:
Issue Dt:
08/28/2007
Application #:
10887049
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
12/09/2004
Title:
MODIFIED FACET ETCH TO PREVENT BLOWN GATE OXIDE AND INCREASE ETCH CHAMBER LIFE
54
Patent #:
Issue Dt:
02/21/2006
Application #:
10887255
Filing Dt:
07/07/2004
Publication #:
Pub Dt:
12/02/2004
Title:
SEMICONDUCTOR COMPONENTS HAVING MULTIPLE ON BOARD CAPACITORS
55
Patent #:
Issue Dt:
03/07/2006
Application #:
10887616
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
01/12/2006
Title:
MEMORY ARRAY DECODER
56
Patent #:
Issue Dt:
01/26/2010
Application #:
10887880
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
01/12/2006
Title:
DUAL PANEL PIXEL READOUT IN AN IMAGER
57
Patent #:
Issue Dt:
12/12/2006
Application #:
10887962
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS OF FORMING METAL NITRIDE, AND METHODS OF FORMING CAPACITOR CONSTRUCTIONS
58
Patent #:
Issue Dt:
07/11/2006
Application #:
10888255
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
12/09/2004
Title:
ETCHANT AND METHOD OF USE
59
Patent #:
Issue Dt:
04/21/2009
Application #:
10889084
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
12/16/2004
Title:
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
60
Patent #:
Issue Dt:
12/25/2007
Application #:
10889201
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
12/02/2004
Title:
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
61
Patent #:
Issue Dt:
10/07/2008
Application #:
10889280
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
12/09/2004
Title:
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILM, AND METHODS OF USE
62
Patent #:
Issue Dt:
03/27/2012
Application #:
10889597
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
12/16/2004
Title:
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
63
Patent #:
Issue Dt:
02/20/2007
Application #:
10889803
Filing Dt:
07/13/2004
Publication #:
Pub Dt:
12/02/2004
Title:
ABERRATION MARK AND METHOD FOR ESTIMATING OVERLAY ERROR AND OPTICAL ABERRATIONS
64
Patent #:
Issue Dt:
10/26/2010
Application #:
10890529
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
02/24/2005
Title:
METHOD FOR MANUFACTURING DIFFERENTIAL ISOLATION STRUCTURES IN A SEMICONDUCTOR ELECTRONIC DEVICE AND CORRESPONDING STRUCTURE
65
Patent #:
Issue Dt:
09/18/2007
Application #:
10891535
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND APPARATUS FOR REDUCING DUTY CYCLE DISTORTION OF AN OUTPUT SIGNAL
66
Patent #:
Issue Dt:
09/26/2006
Application #:
10891792
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
12/09/2004
Title:
DIE STACKING SCHEME
67
Patent #:
Issue Dt:
08/02/2005
Application #:
10892048
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
12/16/2004
Title:
METHOD AND APPARATUS FOR DETECTING TOPOGRAPHICAL FEATURES OF MICROELECTRONIC SUBSTRATES
68
Patent #:
Issue Dt:
11/02/2010
Application #:
10892318
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
EXPOSURE CONTROL FOR IMAGE SENSORS
69
Patent #:
Issue Dt:
02/13/2007
Application #:
10892340
Filing Dt:
07/14/2004
Publication #:
Pub Dt:
12/30/2004
Title:
METHODS OF FORMING MEMORY CELLS HAVING DIODES AND ELECTRODE PLATES CONNECTED TO SOURCE/DRAIN REGIONS
70
Patent #:
Issue Dt:
10/03/2006
Application #:
10892651
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHODS OF GROWING EPITAXIAL SILICON
71
Patent #:
Issue Dt:
10/03/2006
Application #:
10892773
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES
72
Patent #:
Issue Dt:
10/02/2007
Application #:
10892805
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
MEASURE-CONTROLLED DELAY CIRCUITS WITH REDUCED PHASE ERROR
73
Patent #:
Issue Dt:
04/07/2009
Application #:
10892875
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND SYSTEM FOR REDUCING MISMATCH BETWEEN REFERENCE AND INTENSITY PATHS IN ANALOG TO DIGITAL CONVERTERS IN CMOS ACTIVE PIXEL SENSORS
74
Patent #:
Issue Dt:
05/27/2008
Application #:
10893015
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD, SYSTEM, AND APPARATUS FOR TRACKING DEFECTIVE CACHE LINES
75
Patent #:
Issue Dt:
02/01/2011
Application #:
10893276
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
PIXEL CELL HAVING A GRATED INTERFACE
76
Patent #:
Issue Dt:
06/10/2008
Application #:
10893293
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
CMOS FRONT END PROCESS COMPATIBLE LOW STRESS LIGHT SHIELD
77
Patent #:
Issue Dt:
03/13/2007
Application #:
10893299
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF FABRICATION
78
Patent #:
Issue Dt:
08/22/2006
Application #:
10893685
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
12/30/2004
Title:
APPARATUS FOR DEFORMING RESILIENT CONTACT STRUCTURES ON SEMICONDUCTOR COMPONENTS
79
Patent #:
Issue Dt:
09/12/2006
Application #:
10893709
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
12/23/2004
Title:
WAVELENGTH DIVISION MULTIPLEXED MEMORY MODULE, MEMORY SYSTEM AND METHOD
80
Patent #:
Issue Dt:
12/26/2006
Application #:
10893760
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
03/03/2005
Title:
REDUNDANCY SCHEME FOR A MEMORY INTEGRATED CIRCUIT
81
Patent #:
Issue Dt:
12/12/2006
Application #:
10893804
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DELAY STAGE-INTERWEAVED ANALOG DLL/PLL
82
Patent #:
Issue Dt:
03/13/2007
Application #:
10894101
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
IN-SERVICE RECONFIGURABLE DRAM AND FLASH MEMORY DEVICE
83
Patent #:
Issue Dt:
04/14/2009
Application #:
10894125
Filing Dt:
07/20/2004
Publication #:
Pub Dt:
01/26/2006
Title:
DRAM LAYOUT WITH VERTICAL FETS AND METHOD OF FORMATION
84
Patent #:
Issue Dt:
11/04/2008
Application #:
10894242
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
MEMORY DEVICE TRIMS
85
Patent #:
Issue Dt:
08/22/2006
Application #:
10894292
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
12/23/2004
Title:
ETCH STOP LAYER IN POLY-METAL STRUCTURES
86
Patent #:
Issue Dt:
10/03/2006
Application #:
10894782
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHODS OF ETCHING AN ALUMINUM OXIDE COMPRISING SUBSTRATE, AND METHODS OF FORMING A CAPACITOR
87
Patent #:
Issue Dt:
07/04/2006
Application #:
10895130
Filing Dt:
07/21/2004
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD OF FORMING A DUAL-SIDED CAPACITOR
88
Patent #:
Issue Dt:
10/24/2006
Application #:
10895502
Filing Dt:
07/20/2004
Publication #:
Pub Dt:
12/30/2004
Title:
ETCHING METHODS AND APPARATUS AND SUBSTRATE ASSEMBLIES PRODUCED THEREWITH
89
Patent #:
Issue Dt:
07/18/2006
Application #:
10895649
Filing Dt:
07/20/2004
Publication #:
Pub Dt:
01/26/2006
Title:
DELAY-LOCKED LOOP WITH FEEDBACK COMPENSATION
90
Patent #:
Issue Dt:
10/03/2006
Application #:
10896139
Filing Dt:
07/20/2004
Publication #:
Pub Dt:
01/26/2006
Title:
TEMPERATURE-COMPENSATED OUTPUT BUFFER METHOD AND CIRCUIT
91
Patent #:
Issue Dt:
02/21/2012
Application #:
10896711
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
01/06/2005
Title:
LOW DOSE SUPER DEEP SOURCE/DRAIN IMPLANT
92
Patent #:
Issue Dt:
08/05/2008
Application #:
10897165
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
12/23/2004
Title:
USE OF A DUAL-TONE RESIST TO FORM PHOTOMASKS INCLUDING ALIGNMENT MARK PROTECTION, INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES AND BULK SEMICONDUCTOR DEVICE SUBSTRATES
93
Patent #:
Issue Dt:
11/21/2006
Application #:
10897166
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
01/26/2006
Title:
METHOD AND APPARATUS TO SET A TUNING RANGE FOR AN ANALOG DELAY
94
Patent #:
Issue Dt:
07/19/2005
Application #:
10898762
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
12/30/2004
Title:
APPARATUS FOR LATENCY SPECIFIC DUTY CYCLE CORRECTION
95
Patent #:
Issue Dt:
05/03/2005
Application #:
10898765
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
12/23/2004
Title:
METHODS OF WRITING JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY DEVICES
96
Patent #:
Issue Dt:
05/03/2005
Application #:
10898867
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
01/20/2005
Title:
METHODS OF READING JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY DEVICES
97
Patent #:
Issue Dt:
05/22/2007
Application #:
10899010
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
AMORPHOUS CARBON-BASED NON-VOLATILE MEMORY
98
Patent #:
Issue Dt:
06/09/2009
Application #:
10899011
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
12/30/2004
Title:
SYSTEM INCLUDING INTEGRATED CIRCUIT STRUCTURES FORMED IN A SILICONE LADDER POLYMER LAYER
99
Patent #:
Issue Dt:
10/02/2007
Application #:
10899736
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
01/13/2005
Title:
SMALL GRAIN SIZE, CONFORMAL ALUMINUM INTERCONNECTS AND METHOD FOR THEIR FORMATION
100
Patent #:
Issue Dt:
10/10/2006
Application #:
10899892
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
01/06/2005
Title:
MEMORY DEVICE WITH NON-VOLATILE REFERENCE MEMORY CELL TRIMMING CAPABILITIES
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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