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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
04/08/2008
Application #:
11091260
Filing Dt:
03/28/2005
Publication #:
Pub Dt:
07/28/2005
Title:
MEMORY CIRCUITRY WITH OXYGEN DIFFUSION BARRIER LAYER RECEIVED OVER A WELL BASE
2
Patent #:
Issue Dt:
03/17/2009
Application #:
11091610
Filing Dt:
03/28/2005
Publication #:
Pub Dt:
08/04/2005
Title:
ELECTRODE STRUCTURES, DISPLAY DEVICES CONTAINING THE SAME
3
Patent #:
Issue Dt:
10/03/2006
Application #:
11092029
Filing Dt:
03/29/2005
Publication #:
Pub Dt:
08/25/2005
Title:
METHODS OF FORMING SEMICONDUCTOR CIRCUITRY
4
Patent #:
Issue Dt:
05/04/2010
Application #:
11092157
Filing Dt:
03/28/2005
Publication #:
Pub Dt:
08/04/2005
Title:
APPARATUSES AND METHODS FOR CONDITIONING POLISHING PADS USED IN POLISHING MICRO-DEVICE WORKPIECES
5
Patent #:
Issue Dt:
08/15/2006
Application #:
11092348
Filing Dt:
03/29/2005
Publication #:
Pub Dt:
08/04/2005
Title:
METHOD OF FORMING A STACK OF PACKAGED MEMORY DICE
6
Patent #:
Issue Dt:
02/27/2007
Application #:
11093012
Filing Dt:
03/29/2005
Publication #:
Pub Dt:
10/20/2005
Title:
SEQUENTIAL PROGRAM-VERIFY METHOD WITH RESULT BUFFERING
7
Patent #:
Issue Dt:
03/30/2010
Application #:
11093104
Filing Dt:
03/29/2005
Publication #:
Pub Dt:
10/05/2006
Title:
ATOMIC LAYER DEPOSITED TITANIUM SILICON OXIDE FILMS
8
Patent #:
Issue Dt:
08/11/2009
Application #:
11093286
Filing Dt:
03/30/2005
Publication #:
Pub Dt:
08/04/2005
Title:
PHOTODIODE WITH ULTRA-SHALLOW JUNCTION FOR HIGH QUANTUM EFFICIENCY CMOS IMAGE SENSOR AND METHOD OF FORMATION
9
Patent #:
Issue Dt:
09/13/2011
Application #:
11093907
Filing Dt:
03/30/2005
Publication #:
Pub Dt:
10/05/2006
Title:
DIFFERENTIAL DELAY COMPENSATION
10
Patent #:
Issue Dt:
11/24/2009
Application #:
11094614
Filing Dt:
03/29/2005
Publication #:
Pub Dt:
08/04/2005
Title:
ELECTRONIC APPARATUSES, SILICON-ON-INSULATOR INTEGRATED CIRCUITS, AND FABRICATION METHODS
11
Patent #:
Issue Dt:
02/05/2008
Application #:
11094687
Filing Dt:
03/30/2005
Publication #:
Pub Dt:
10/05/2006
Title:
METHODS TO PERFORM CACHE COHERENCY IN MULTIPROCESSOR SYSTEM USING RESERVE SIGNALS AND CONTROL BITS
12
Patent #:
Issue Dt:
09/11/2007
Application #:
11095186
Filing Dt:
03/30/2005
Publication #:
Pub Dt:
10/12/2006
Title:
METHODS OF FILLING OPENINGS WITH OXIDE, AND METHODS OF FORMING TRENCHED ISOLATION REGIONS
13
Patent #:
Issue Dt:
03/25/2008
Application #:
11095330
Filing Dt:
03/30/2005
Publication #:
Pub Dt:
10/12/2006
Title:
FLASH MEMORY CELL HAVING REDUCED FLOATING GATE TO FLOATING GATE COUPLING
14
Patent #:
Issue Dt:
08/01/2006
Application #:
11096970
Filing Dt:
04/01/2005
Publication #:
Pub Dt:
08/11/2005
Title:
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SAME
15
Patent #:
Issue Dt:
01/30/2007
Application #:
11097064
Filing Dt:
04/01/2005
Publication #:
Pub Dt:
10/05/2006
Title:
LAYOUT FOR NAND FLASH MEMORY ARRAY HAVING REDUCED WORD LINE IMPEDANCE
16
Patent #:
Issue Dt:
09/06/2011
Application #:
11097876
Filing Dt:
04/01/2005
Publication #:
Pub Dt:
10/05/2006
Title:
METHODS OF FORMING TRENCH ISOLATION IN THE FABRICATION OF INTEGRATED CIRCUITRY AND METHODS OF FABRICATING INTEGRATED CIRCUITRY
17
Patent #:
Issue Dt:
08/21/2007
Application #:
11098552
Filing Dt:
04/05/2005
Publication #:
Pub Dt:
08/11/2005
Title:
METHOD OF FORMING MIRRORS BY SURFACE TRANSFORMATION OF EMPTY SPACES IN SOLID STATE MATERIALS
18
Patent #:
Issue Dt:
04/03/2007
Application #:
11098747
Filing Dt:
04/04/2005
Publication #:
Pub Dt:
08/18/2005
Title:
JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY DEVICES AND SYSTEMS
19
Patent #:
Issue Dt:
09/11/2007
Application #:
11099372
Filing Dt:
04/05/2005
Publication #:
Pub Dt:
08/18/2005
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENT WITH STIFFENER AND CIRCUIT DECAL
20
Patent #:
Issue Dt:
10/03/2006
Application #:
11099374
Filing Dt:
04/05/2005
Publication #:
Pub Dt:
08/18/2005
Title:
SEMICONDUCTOR COMPONENT HAVING STIFFENER, STACKED DICE AND CIRCUIT DECALS
21
Patent #:
Issue Dt:
07/11/2006
Application #:
11099775
Filing Dt:
04/06/2005
Publication #:
Pub Dt:
08/11/2005
Title:
METHOD FOR ERASING AN NROM CELL
22
Patent #:
Issue Dt:
07/11/2006
Application #:
11099839
Filing Dt:
04/06/2005
Publication #:
Pub Dt:
08/11/2005
Title:
METHOD FOR ERASING AN NROM CELL
23
Patent #:
Issue Dt:
03/11/2008
Application #:
11099972
Filing Dt:
04/06/2005
Publication #:
Pub Dt:
10/12/2006
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
24
Patent #:
Issue Dt:
03/29/2011
Application #:
11100429
Filing Dt:
04/07/2005
Publication #:
Pub Dt:
10/12/2006
Title:
ANTI-ECLIPSE CIRCUITRY WITH TRACKING OF FLOATING DIFFUSION RESET LEVEL
25
Patent #:
Issue Dt:
06/30/2009
Application #:
11100885
Filing Dt:
04/04/2005
Publication #:
Pub Dt:
09/01/2005
Title:
METHODS OF FORMING A HIGH CONDUCTIVITY DIAMOND FILM AND STRUCTURES FORMED THEREBY
26
Patent #:
Issue Dt:
04/24/2007
Application #:
11101626
Filing Dt:
04/08/2005
Publication #:
Pub Dt:
08/11/2005
Title:
SEMICONDUCTOR PACKAGE WITH WIRE BONDED STACKED DICE AND MULTI-LAYER METAL BUMPS
27
Patent #:
Issue Dt:
08/25/2009
Application #:
11101785
Filing Dt:
04/07/2005
Publication #:
Pub Dt:
10/12/2006
Title:
LOW LOCALITY-OF-REFERENCE SUPPORT IN A MULTI-LEVEL CACHE HIERACHY
28
Patent #:
Issue Dt:
05/13/2008
Application #:
11102408
Filing Dt:
04/08/2005
Publication #:
Pub Dt:
10/12/2006
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH THROUGH WIRE INTERCONNECTS
29
Patent #:
Issue Dt:
09/09/2008
Application #:
11102844
Filing Dt:
04/11/2005
Publication #:
Pub Dt:
08/18/2005
Title:
IMAGE DEVICE AND PHOTODIODE STRUCTURE
30
Patent #:
Issue Dt:
06/02/2009
Application #:
11103019
Filing Dt:
04/11/2005
Publication #:
Pub Dt:
08/11/2005
Title:
OPTICALLY INTERACTIVE DEVICE PACKAGE ARRAY
31
Patent #:
Issue Dt:
02/18/2014
Application #:
11103188
Filing Dt:
04/11/2005
Publication #:
Pub Dt:
10/12/2006
Title:
HEATING PHASE CHANGE MATERIAL
32
Patent #:
Issue Dt:
09/18/2007
Application #:
11105148
Filing Dt:
04/12/2005
Publication #:
Pub Dt:
09/01/2005
Title:
METHOD OF FORMING A CATALYTIC SURFACE COMPRISING AT LEAST ONE OF PT, PD, CO AND AU IN AT LEAST ONE OF ELEMENTAL AND ALLOY FORMS
33
Patent #:
Issue Dt:
04/08/2008
Application #:
11105412
Filing Dt:
04/14/2005
Publication #:
Pub Dt:
08/11/2005
Title:
USE OF GATE ELECTRODE WORKFUNCTION TO IMPROVE DRAM REFRESH
34
Patent #:
Issue Dt:
12/22/2009
Application #:
11105419
Filing Dt:
04/14/2005
Publication #:
Pub Dt:
08/18/2005
Title:
WELL FOR CMOS IMAGER AND METHOD OF FORMATION
35
Patent #:
Issue Dt:
08/22/2006
Application #:
11105775
Filing Dt:
04/13/2005
Publication #:
Pub Dt:
08/11/2005
Title:
METHODS FOR MAKING SEMICONDUCTOR STRUCTURES HAVING HIGH-SPEED AREAS AND HIGH-DENSITY AREAS
36
Patent #:
Issue Dt:
10/02/2007
Application #:
11106100
Filing Dt:
04/14/2005
Publication #:
Pub Dt:
10/19/2006
Title:
CIRCUIT AND METHOD FOR STABLE FUSE DETECTION
37
Patent #:
Issue Dt:
01/27/2009
Application #:
11106465
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
10/19/2006
Title:
COLUMN-PARALLEL SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION FOR IMAGERS
38
Patent #:
Issue Dt:
07/22/2008
Application #:
11106509
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
08/11/2005
Title:
MULTILAYER DIELECTRIC TUNNEL BARRIER USED IN MAGNETIC TUNNEL JUNCTION DEVICES, AND ITS METHOD OF FABRICATION
39
Patent #:
Issue Dt:
12/19/2006
Application #:
11106716
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
03/23/2006
Title:
INTEGRATED CHARGE SENSING SCHEME FOR RESISTIVE MEMORIES
40
Patent #:
Issue Dt:
08/02/2011
Application #:
11107125
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
10/19/2006
Title:
METHODS OF MANUFACTURING NANOTUBES HAVING CONTROLLED CHARACTERISTICS
41
Patent #:
Issue Dt:
09/25/2007
Application #:
11107587
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
10/19/2006
Title:
VARIABLE DELAY LINE WITH MULTIPLE HIERARCHY
42
Patent #:
Issue Dt:
06/24/2008
Application #:
11107807
Filing Dt:
04/18/2005
Publication #:
Pub Dt:
09/08/2005
Title:
ULTRA-SHALLOW PHOTODIODE USING INDIUM
43
Patent #:
Issue Dt:
07/15/2008
Application #:
11108219
Filing Dt:
04/18/2005
Publication #:
Pub Dt:
09/01/2005
Title:
METHODS OF GAS DELIVERY FOR DEPOSITION PROCESSES AND METHODS OF DEPOSITING MATERIAL ON A SUBSTRATE
44
Patent #:
Issue Dt:
03/24/2009
Application #:
11108436
Filing Dt:
04/18/2005
Publication #:
Pub Dt:
08/18/2005
Title:
SELF-ALIGNED POLY-METAL STRUCTURES
45
Patent #:
Issue Dt:
04/24/2012
Application #:
11109531
Filing Dt:
04/19/2005
Publication #:
Pub Dt:
10/19/2006
Title:
POWER SAVINGS MODE FOR MEMORY SYSTEMS
46
Patent #:
Issue Dt:
07/31/2007
Application #:
11109535
Filing Dt:
04/19/2005
Publication #:
Pub Dt:
10/19/2006
Title:
ON-CHIP SAMPLING CIRCUIT AND METHOD
47
Patent #:
Issue Dt:
03/17/2009
Application #:
11109946
Filing Dt:
04/20/2005
Publication #:
Pub Dt:
10/26/2006
Title:
STATIC RAM MEMORY CELL WITH DNR CHALCOGENIDE DEVICES AND METHOD OF FORMING
48
Patent #:
Issue Dt:
04/08/2008
Application #:
11110431
Filing Dt:
04/20/2005
Publication #:
Pub Dt:
08/25/2005
Title:
SEMICONDUCTOR DICE HAVING BACK SIDE REDISTRIBUTION LAYER ACCESSED USING THROUGH-SILICON VIAS, METHODS
49
Patent #:
Issue Dt:
05/13/2008
Application #:
11110583
Filing Dt:
04/20/2005
Publication #:
Pub Dt:
08/25/2005
Title:
TWO DIE SEMICONDUCTOR ASSEMBLY AND SYSTEM INCLUDING SAME
50
Patent #:
Issue Dt:
05/25/2010
Application #:
11110612
Filing Dt:
04/19/2005
Title:
DIRECT SECONDARY DEVICE INTERFACE BY A HOST
51
Patent #:
Issue Dt:
02/09/2010
Application #:
11111360
Filing Dt:
04/21/2005
Publication #:
Pub Dt:
10/27/2005
Title:
METHODS OF FORMING STORAGE NODES FOR A DRAM ARRAY
52
Patent #:
Issue Dt:
10/30/2007
Application #:
11111605
Filing Dt:
04/21/2005
Publication #:
Pub Dt:
10/27/2005
Title:
DRAM ARRAYS
53
Patent #:
Issue Dt:
06/10/2008
Application #:
11111625
Filing Dt:
04/21/2005
Publication #:
Pub Dt:
10/27/2005
Title:
METHODS OF FORMING DRAM ARRAYS
54
Patent #:
Issue Dt:
09/23/2008
Application #:
11111836
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
MEMORY ARRAY FOR INCREASED BIT DENSITY
55
Patent #:
Issue Dt:
09/11/2007
Application #:
11111838
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
METHOD AND APPARATUS FOR ACCESSING A MEMORY ARRAY
56
Patent #:
Issue Dt:
05/04/2010
Application #:
11111917
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
MEMORY ELEMENTS HAVING PATTERNED ELECTRODES AND METHOD OF FORMING THE SAME
57
Patent #:
Issue Dt:
05/15/2007
Application #:
11112127
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
08/25/2005
Title:
METHODS OF FORMING A CAPACITOR
58
Patent #:
Issue Dt:
06/03/2008
Application #:
11112787
Filing Dt:
04/21/2005
Publication #:
Pub Dt:
09/22/2005
Title:
METHODS AND SYSTEMS FOR PLANARIZING MICROELECTRONIC DEVICES WITH GE-SE-AG LAYERS
59
Patent #:
Issue Dt:
05/22/2007
Application #:
11113818
Filing Dt:
04/25/2005
Publication #:
Pub Dt:
11/17/2005
Title:
TRIMMING FUNCTIONAL PARAMETERS IN INTEGRATED CIRCUITS
60
Patent #:
Issue Dt:
07/25/2006
Application #:
11113833
Filing Dt:
04/25/2005
Publication #:
Pub Dt:
09/01/2005
Title:
POSITION BASED ERASE VERIFICATION LEVELS IN A FLASH MEMORY DEVICE
61
Patent #:
Issue Dt:
11/17/2009
Application #:
11114094
Filing Dt:
04/26/2005
Publication #:
Pub Dt:
10/26/2006
Title:
ROLLING SHUTTER FOR PREVENTION OF BLOOMING
62
Patent #:
Issue Dt:
07/22/2008
Application #:
11114130
Filing Dt:
04/26/2005
Publication #:
Pub Dt:
11/02/2006
Title:
METHOD OF PRODUCING BALANCED DATA OUTPUT
63
Patent #:
Issue Dt:
08/07/2007
Application #:
11114403
Filing Dt:
04/26/2005
Publication #:
Pub Dt:
10/26/2006
Title:
FLASH MEMORY DEVICE HAVING A GRADED COMPOSITION, HIGH DIELECTRIC CONSTANT GATE INSULATOR
64
Patent #:
Issue Dt:
12/02/2008
Application #:
11114589
Filing Dt:
04/26/2005
Publication #:
Pub Dt:
10/26/2006
Title:
ABSORBING BOUNDARY FOR A MULTI-LAYER CIRCUIT BOARD STRUCTURE
65
Patent #:
Issue Dt:
04/15/2008
Application #:
11115833
Filing Dt:
04/25/2005
Publication #:
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR STRUCTURES
66
Patent #:
Issue Dt:
09/25/2007
Application #:
11115854
Filing Dt:
04/25/2005
Publication #:
Pub Dt:
09/08/2005
Title:
METHODS OF FILLING GAPS USING HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
67
Patent #:
Issue Dt:
03/25/2008
Application #:
11116181
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
09/01/2005
Title:
LOW CAPACITANCE WIRING LAYOUT
68
Patent #:
Issue Dt:
07/15/2008
Application #:
11116597
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
11/02/2006
Title:
MEMORY BLOCK REALLOCATION IN A FLASH MEMORY DEVICE
69
Patent #:
Issue Dt:
10/09/2007
Application #:
11116630
Filing Dt:
04/26/2005
Publication #:
Pub Dt:
11/09/2006
Title:
SYSTEM AND METHOD FOR CAPTURING DATA SIGNALS USING A DATA STROBE SIGNAL
70
Patent #:
Issue Dt:
02/03/2009
Application #:
11116842
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
11/02/2006
Title:
METHOD OF COMPARISON BETWEEN CACHE AND DATA REGISTER FOR NON-VOLATILE MEMORY
71
Patent #:
Issue Dt:
06/24/2008
Application #:
11117121
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
11/02/2006
Title:
ATOMIC LAYER DEPOSITED ZIRCONIUM SILICON OXIDE FILMS
72
Patent #:
Issue Dt:
02/16/2010
Application #:
11117125
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
11/02/2006
Title:
ATOMIC LAYER DESPOSITION OF A RUTHENIUM LAYER TO A LANTHANIDE OXIDE DIELECTRIC LAYER
73
Patent #:
Issue Dt:
05/06/2008
Application #:
11118959
Filing Dt:
04/29/2005
Title:
SECURE PORTABLE STORAGE DEVICE
74
Patent #:
Issue Dt:
12/18/2007
Application #:
11119127
Filing Dt:
04/29/2005
Publication #:
Pub Dt:
09/01/2005
Title:
CONSTRUCTIONS COMPRISING PEROVSKITE-TYPE DIELECTRIC
75
Patent #:
Issue Dt:
09/11/2007
Application #:
11119128
Filing Dt:
04/29/2005
Publication #:
Pub Dt:
09/15/2005
Title:
MEMORY CELL WITH TRENCH-ISOLATED TRANSISTOR INCLUDING FIRST AND SECOND ISOLATION TRENCHES
76
Patent #:
Issue Dt:
01/24/2012
Application #:
11119321
Filing Dt:
04/29/2005
Publication #:
Pub Dt:
12/28/2006
Title:
CONFIGURATION FINALIZATION ON FIRST VALID NAND COMMAND
77
Patent #:
Issue Dt:
09/18/2007
Application #:
11119370
Filing Dt:
04/29/2005
Publication #:
Pub Dt:
12/01/2005
Title:
BORON INCORPORATED DIFFUSION BARRIER MATERIAL
78
Patent #:
Issue Dt:
01/20/2009
Application #:
11119589
Filing Dt:
05/02/2005
Publication #:
Pub Dt:
09/01/2005
Title:
ERASE BLOCK DATA SPLITTING
79
Patent #:
Issue Dt:
08/07/2007
Application #:
11120766
Filing Dt:
05/03/2005
Publication #:
Pub Dt:
11/10/2005
Title:
CIRCUIT FOR SELECTING/DESELECTING A BITLINE OF A NON-VOLATILE MEMORY
80
Patent #:
Issue Dt:
04/29/2008
Application #:
11121114
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD AND APPARATUS FOR SENSING FLASH MEMORY USING DELTA SIGMA MODULATION
81
Patent #:
Issue Dt:
12/14/2010
Application #:
11121119
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD AND APPARATUS FOR DARK CURRENT AND BLOOMING SUPPRESSION IN 4T CMOS IMAGER PIXEL
82
Patent #:
Issue Dt:
06/10/2008
Application #:
11121172
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/24/2005
Title:
METHOD AND APPARATUS FOR CONNECTING A MASSIVELY PARALLEL PROCESSOR ARRAY TO A MEMORY ARRAY IN A BIT SERIAL MANNER
83
Patent #:
Issue Dt:
06/24/2008
Application #:
11121276
Filing Dt:
05/03/2005
Publication #:
Pub Dt:
09/15/2005
Title:
METHOD OF FORMING COMPLIANT CONTACT STRUCTURES
84
Patent #:
Issue Dt:
02/13/2007
Application #:
11121615
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD AND CIRCUIT FOR VERIFYING AND EVENTUALLY SUBSTITUTING DEFECTIVE REFERENCE CELLS OF A MEMORY
85
Patent #:
Issue Dt:
07/13/2010
Application #:
11121868
Filing Dt:
05/03/2005
Publication #:
Pub Dt:
11/23/2006
Title:
SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
86
Patent #:
Issue Dt:
09/11/2007
Application #:
11122362
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD OF FORMING A PSEUDO SOI SUBSTRATE AND SEMICONDUCTOR DEVICES
87
Patent #:
Issue Dt:
07/22/2008
Application #:
11122409
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/09/2006
Title:
INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES
88
Patent #:
Issue Dt:
08/29/2006
Application #:
11122490
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
09/01/2005
Title:
STATIC CONTENT ADDRESSABLE MEMORY CELL
89
Patent #:
Issue Dt:
06/12/2007
Application #:
11122764
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/17/2005
Title:
VERTICAL NROM HAVING A STORAGE DENSITY OF 1 BIT PER 1F2
90
Patent #:
Issue Dt:
05/13/2008
Application #:
11122854
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/09/2006
Title:
MEMORY CELL, DEVICE, AND SYSTEM
91
Patent #:
Issue Dt:
09/25/2007
Application #:
11122929
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
09/22/2005
Title:
METHOD OF FORMING A DOUBLE-SIDED CAPACITOR
92
Patent #:
Issue Dt:
11/14/2006
Application #:
11123184
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
09/08/2005
Title:
WRITE STATE MACHINE ARCHITECTURE FOR FLASH MEMORY INTERNAL INSTRUCTIONS
93
Patent #:
Issue Dt:
07/11/2006
Application #:
11123297
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
10/06/2005
Title:
INTERPOSER INCLUDING ADHESIVE TAPE
94
Patent #:
Issue Dt:
04/24/2007
Application #:
11123466
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
09/15/2005
Title:
SEMICONDUCTOR COMPONENT ASSEMBLIES HAVING INTERCONNECTS
95
Patent #:
Issue Dt:
02/13/2007
Application #:
11123916
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
09/01/2005
Title:
MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE
96
Patent #:
Issue Dt:
05/09/2006
Application #:
11124068
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
09/22/2005
Title:
INTERMEDIATE SEMICONDUCTOR DEVICE HAVING ACTIVATED OXIDE-BASED LAYER FOR ELECTROLESS PLATING
97
Patent #:
Issue Dt:
04/08/2008
Application #:
11124743
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
11/09/2006
Title:
APPARATUS AND METHOD FOR CONTROLLING A DELAY- OR PHASE-LOCKED LOOP AS A FUNCTION OF LOOP FREQUENCY
98
Patent #:
Issue Dt:
11/25/2008
Application #:
11124744
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
11/09/2006
Title:
ADJUSTABLE BYTE LANE OFFSET FOR MEMORY MODULE TO REDUCE SKEW
99
Patent #:
Issue Dt:
07/11/2006
Application #:
11124784
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
09/22/2005
Title:
APPARATUS FOR LATENCY SPECIFIC DUTY CYCLE CORRECTION
100
Patent #:
Issue Dt:
05/06/2008
Application #:
11125096
Filing Dt:
05/10/2005
Publication #:
Pub Dt:
10/19/2006
Title:
GENERATION AND STORAGE OF COLUMN OFFSETS FOR A COLUMN PARALLEL IMAGE SENSOR
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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