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Reel/Frame:038812/0954   Pages: 18
Recorded: 05/25/2016
Attorney Dkt #:NAME CHANGE PART 1B
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 542
Page 1 of 6
Pages: 1 2 3 4 5 6
1
Patent #:
9582193
Issue Dt:
02/28/2017
Application #:
14621237
Filing Dt:
02/12/2015
Publication #:
US20160062665
Pub Dt:
03/03/2016
Title:
TRIGGERING A PROCESS TO REDUCE DECLARED CAPACITY OF A STORAGE DEVICE IN A MULTI-STORAGE-DEVICE STORAGE SYSTEM
2
Patent #:
9582212
Issue Dt:
02/28/2017
Application #:
14621253
Filing Dt:
02/12/2015
Publication #:
US20160062693
Pub Dt:
03/03/2016
Title:
Notification of Trigger Condition to Reduce Declared Capacity of a Storage Device
3
Patent #:
9582220
Issue Dt:
02/28/2017
Application #:
14621263
Filing Dt:
02/12/2015
Publication #:
US20160062699
Pub Dt:
03/03/2016
Title:
Notification of Trigger Condition to Reduce Declared Capacity of a Storage Device in a Multi-Storage-Device Storage System
4
Patent #:
9582203
Issue Dt:
02/28/2017
Application #:
14621275
Filing Dt:
02/12/2015
Publication #:
US20160062681
Pub Dt:
03/03/2016
Title:
Process and Apparatus to Reduce Declared Capacity of a Storage Device by Reducing a Range of Logical Addresses
5
Patent #:
9665311
Issue Dt:
05/30/2017
Application #:
14621289
Filing Dt:
02/12/2015
Publication #:
US20160062666
Pub Dt:
03/03/2016
Title:
Process and Apparatus to Reduce Declared Capacity of a Storage Device by Making Specific Logical Addresses Unavailable
6
Patent #:
9652153
Issue Dt:
05/16/2017
Application #:
14621292
Filing Dt:
02/12/2015
Publication #:
US20160062667
Pub Dt:
03/03/2016
Title:
PROCESS AND APPARATUS TO REDUCE DECLARED CAPACITY OF A STORAGE DEVICE BY REDUCING A COUNT OF LOGICAL ADDRESSES
7
Patent #:
9449700
Issue Dt:
09/20/2016
Application #:
14621662
Filing Dt:
02/13/2015
Publication #:
US20160240262
Pub Dt:
08/18/2016
Title:
Boundary Word Line Search and Open Block Read Methods with Reduced Read Disturb
8
Patent #:
9583615
Issue Dt:
02/28/2017
Application #:
14623843
Filing Dt:
02/17/2015
Publication #:
US20160240665
Pub Dt:
08/18/2016
Title:
VERTICAL TRANSISTOR AND LOCAL INTERCONNECT STRUCTURE
9
Patent #:
9425047
Issue Dt:
08/23/2016
Application #:
14626652
Filing Dt:
02/19/2015
Publication #:
US20160247674
Pub Dt:
08/25/2016
Title:
SELF-ALIGNED PROCESS USING VARIABLE-FLUIDITY MATERIAL
10
Patent #:
9760299
Issue Dt:
09/12/2017
Application #:
14629167
Filing Dt:
02/23/2015
Publication #:
US20150199145
Pub Dt:
07/16/2015
Title:
METHOD AND SYSTEM FOR HIJACKING WRITES TO A NON-VOLATILE MEMORY
11
Patent #:
9824007
Issue Dt:
11/21/2017
Application #:
14630552
Filing Dt:
02/24/2015
Publication #:
US20160147468
Pub Dt:
05/26/2016
Title:
Data Integrity Enhancement to Protect Against Returning Old Versions of Data
12
Patent #:
9817752
Issue Dt:
11/14/2017
Application #:
14630557
Filing Dt:
02/24/2015
Publication #:
US20160147651
Pub Dt:
05/26/2016
Title:
Data Integrity Enhancement to Protect Against Returning Old Versions of Data
13
Patent #:
9847662
Issue Dt:
12/19/2017
Application #:
14630564
Filing Dt:
02/24/2015
Publication #:
US20160118814
Pub Dt:
04/28/2016
Title:
VOLTAGE SLEW RATE THROTTLING FOR REDUCTION OF ANOMALOUS CHARGING CURRENT
14
Patent #:
NONE
Issue Dt:
Application #:
14630573
Filing Dt:
02/24/2015
Publication #:
US20160118132
Pub Dt:
04/28/2016
Title:
Low Impact Read Disturb Handling
15
Patent #:
9595566
Issue Dt:
03/14/2017
Application #:
14631616
Filing Dt:
02/25/2015
Publication #:
US20160247859
Pub Dt:
08/25/2016
Title:
Floating Staircase Word Lines and Process in a 3D Non-Volatile Memory Having Vertical Bit Lines
16
Patent #:
9424184
Issue Dt:
08/23/2016
Application #:
14631648
Filing Dt:
02/25/2015
Publication #:
US20150212936
Pub Dt:
07/30/2015
Title:
APPARATUS, SYSTEMS, AND METHODS FOR NAMELESS WRITES
17
Patent #:
NONE
Issue Dt:
Application #:
14632179
Filing Dt:
02/26/2015
Publication #:
US20160254812
Pub Dt:
09/01/2016
Title:
APPARATUS FOR CALIBRATING OFF-CHIP DRIVER/ON-DIE TERMINATION CIRCUITS
18
Patent #:
9564213
Issue Dt:
02/07/2017
Application #:
14632998
Filing Dt:
02/26/2015
Publication #:
US20160254047
Pub Dt:
09/01/2016
Title:
PROGRAM VERIFY FOR NON-VOLATILE STORAGE
19
Patent #:
9698202
Issue Dt:
07/04/2017
Application #:
14635419
Filing Dt:
03/02/2015
Publication #:
US20160260775
Pub Dt:
09/08/2016
Title:
PARALLEL BIT LINE THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY
20
Patent #:
9467150
Issue Dt:
10/11/2016
Application #:
14635584
Filing Dt:
03/02/2015
Publication #:
US20160261274
Pub Dt:
09/08/2016
Title:
DYNAMIC CLOCK RATE CONTROL FOR POWER REDUCTION
21
Patent #:
NONE
Issue Dt:
Application #:
14635723
Filing Dt:
03/02/2015
Publication #:
US20160261251
Pub Dt:
09/08/2016
Title:
DYNAMIC CLOCK RATE CONTROL FOR POWER REDUCTION
22
Patent #:
9753522
Issue Dt:
09/05/2017
Application #:
14635789
Filing Dt:
03/02/2015
Publication #:
US20160259391
Pub Dt:
09/08/2016
Title:
DYNAMIC CLOCK RATE CONTROL FOR POWER REDUCTION
23
Patent #:
9372632
Issue Dt:
06/21/2016
Application #:
14635840
Filing Dt:
03/02/2015
Publication #:
US20150169245
Pub Dt:
06/18/2015
Title:
Controller with Extended Status Register and Method of Use Therewith
24
Patent #:
9627046
Issue Dt:
04/18/2017
Application #:
14635918
Filing Dt:
03/02/2015
Publication #:
US20160260476
Pub Dt:
09/08/2016
Title:
Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
25
Patent #:
10218166
Issue Dt:
02/26/2019
Application #:
14637117
Filing Dt:
03/03/2015
Publication #:
US20160261104
Pub Dt:
09/08/2016
Title:
SYSTEM AND METHOD FOR DYNAMIC MONITORING OF CONTROLLER CURRENT CONSUMPTION
26
Patent #:
10055267
Issue Dt:
08/21/2018
Application #:
14638860
Filing Dt:
03/04/2015
Publication #:
US20160259570
Pub Dt:
09/08/2016
Title:
Block Management Scheme to Handle Cluster Failures in Non-Volatile Memory
27
Patent #:
9397648
Issue Dt:
07/19/2016
Application #:
14639720
Filing Dt:
03/05/2015
Title:
Systems, Circuitry, and Methods for Decoding Pulse Width Modulated Signal
28
Patent #:
9613715
Issue Dt:
04/04/2017
Application #:
14642611
Filing Dt:
03/09/2015
Publication #:
US20150364215
Pub Dt:
12/17/2015
Title:
Low-Test Memory Stack for Non-Volatile Storage
29
Patent #:
9515023
Issue Dt:
12/06/2016
Application #:
14643211
Filing Dt:
03/10/2015
Publication #:
US20150179577
Pub Dt:
06/25/2015
Title:
MULTILEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING THEREOF
30
Patent #:
9870945
Issue Dt:
01/16/2018
Application #:
14643280
Filing Dt:
03/10/2015
Publication #:
US20160268209
Pub Dt:
09/15/2016
Title:
CRYSTALLINE LAYER STACK FOR FORMING CONDUCTIVE LAYERS IN A THREE-DIMENSIONAL MEMORY STRUCTURE
31
Patent #:
9952784
Issue Dt:
04/24/2018
Application #:
14645102
Filing Dt:
03/11/2015
Publication #:
US20160266821
Pub Dt:
09/15/2016
Title:
Multichip Dual Write
32
Patent #:
9933950
Issue Dt:
04/03/2018
Application #:
14656345
Filing Dt:
03/12/2015
Publication #:
US20160210050
Pub Dt:
07/21/2016
Title:
STORAGE OPERATION INTERRUPT
33
Patent #:
9703629
Issue Dt:
07/11/2017
Application #:
14657677
Filing Dt:
03/13/2015
Publication #:
US20160162357
Pub Dt:
06/09/2016
Title:
APPROACH TO CORRECT ECC ERRORS USING DUPLICATE COPIES OF DATA
34
Patent #:
10338817
Issue Dt:
07/02/2019
Application #:
14659403
Filing Dt:
03/16/2015
Publication #:
US20160188219
Pub Dt:
06/30/2016
Title:
SYSTEMS AND METHODS FOR STORAGE RECOVERY
35
Patent #:
9720769
Issue Dt:
08/01/2017
Application #:
14659404
Filing Dt:
03/16/2015
Publication #:
US20160162353
Pub Dt:
06/09/2016
Title:
STORAGE PARAMETERS FOR A DATA STORAGE DEVICE
36
Patent #:
9753649
Issue Dt:
09/05/2017
Application #:
14659493
Filing Dt:
03/16/2015
Publication #:
US20160117099
Pub Dt:
04/28/2016
Title:
Tracking Intermix of Writes and Un-Map Commands Across Power Cycles
37
Patent #:
9530788
Issue Dt:
12/27/2016
Application #:
14659963
Filing Dt:
03/17/2015
Publication #:
US20160276359
Pub Dt:
09/22/2016
Title:
METALLIC ETCH STOP LAYER IN A THREE-DIMENSIONAL MEMORY STRUCTURE
38
Patent #:
9812461
Issue Dt:
11/07/2017
Application #:
14660023
Filing Dt:
03/17/2015
Publication #:
US20160276360
Pub Dt:
09/22/2016
Title:
HONEYCOMB CELL STRUCTURE THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE
39
Patent #:
9766819
Issue Dt:
09/19/2017
Application #:
14661971
Filing Dt:
03/18/2015
Publication #:
US20160188221
Pub Dt:
06/30/2016
Title:
SYSTEMS AND METHODS FOR MANAGING STORAGE ENDURANCE
40
Patent #:
9886341
Issue Dt:
02/06/2018
Application #:
14662321
Filing Dt:
03/19/2015
Publication #:
US20160188404
Pub Dt:
06/30/2016
Title:
OPTIMIZING RECLAIMED FLASH MEMORY
41
Patent #:
9704572
Issue Dt:
07/11/2017
Application #:
14663775
Filing Dt:
03/20/2015
Publication #:
US20160276023
Pub Dt:
09/22/2016
Title:
Sense Amplifier With Integrating Capacitor And Methods Of Operation
42
Patent #:
9390793
Issue Dt:
07/12/2016
Application #:
14663786
Filing Dt:
03/20/2015
Title:
Leakage Current Compensation With Reference Bit Line Sensing In Non-Volatile Memory
43
Patent #:
9904472
Issue Dt:
02/27/2018
Application #:
14664127
Filing Dt:
03/20/2015
Publication #:
US20160224253
Pub Dt:
08/04/2016
Title:
Memory System and Method for Delta Writes
44
Patent #:
9582435
Issue Dt:
02/28/2017
Application #:
14665893
Filing Dt:
03/23/2015
Publication #:
US20160283110
Pub Dt:
09/29/2016
Title:
Memory System and Method for Efficient Padding of Memory Pages
45
Patent #:
9431120
Issue Dt:
08/30/2016
Application #:
14665920
Filing Dt:
03/23/2015
Title:
Memory Die and Method for Efficient Use of Data Latches in Serving Mixed Traffic Loads
46
Patent #:
9761604
Issue Dt:
09/12/2017
Application #:
14666678
Filing Dt:
03/24/2015
Publication #:
US20160284723
Pub Dt:
09/29/2016
Title:
3D VERTICAL NAND WITH III-V CHANNEL
47
Patent #:
9685454
Issue Dt:
06/20/2017
Application #:
14666687
Filing Dt:
03/24/2015
Publication #:
US20160284724
Pub Dt:
09/29/2016
Title:
METHOD OF FORMING 3D VERTICAL NAND WITH III-V CHANNEL
48
Patent #:
9443866
Issue Dt:
09/13/2016
Application #:
14666789
Filing Dt:
03/24/2015
Publication #:
US20160284726
Pub Dt:
09/29/2016
Title:
MID-TUNNELING DIELECTRIC BAND GAP MODIFICATION FOR ENHANCED DATA RETENTION IN A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
49
Patent #:
9461059
Issue Dt:
10/04/2016
Application #:
14667076
Filing Dt:
03/24/2015
Publication #:
US20160284715
Pub Dt:
09/29/2016
Title:
PATTERNING FOR VARIABLE DEPTH STRUCTURES
50
Patent #:
NONE
Issue Dt:
Application #:
14667082
Filing Dt:
03/24/2015
Publication #:
US20160191059
Pub Dt:
06/30/2016
Title:
CROSS-COUPLED LEVEL SHIFTER WITH TRANSITION TRACKING CIRCUITS
51
Patent #:
9558125
Issue Dt:
01/31/2017
Application #:
14668690
Filing Dt:
03/25/2015
Publication #:
US20160117252
Pub Dt:
04/28/2016
Title:
Processing of Un-Map Commands to Enhance Performance and Endurance of a Storage Device
52
Patent #:
9916087
Issue Dt:
03/13/2018
Application #:
14668710
Filing Dt:
03/25/2015
Publication #:
US20160117105
Pub Dt:
04/28/2016
Title:
Method and System for Throttling Bandwidth Based on Temperature
53
Patent #:
9880605
Issue Dt:
01/30/2018
Application #:
14668722
Filing Dt:
03/25/2015
Publication #:
US20160116968
Pub Dt:
04/28/2016
Title:
Method and System for Throttling Power Consumption
54
Patent #:
9443597
Issue Dt:
09/13/2016
Application #:
14669267
Filing Dt:
03/26/2015
Publication #:
US20150200014
Pub Dt:
07/16/2015
Title:
Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory
55
Patent #:
9947399
Issue Dt:
04/17/2018
Application #:
14669731
Filing Dt:
03/26/2015
Publication #:
US20160284403
Pub Dt:
09/29/2016
Title:
UPDATING RESISTIVE MEMORY
56
Patent #:
9673274
Issue Dt:
06/06/2017
Application #:
14670362
Filing Dt:
03/26/2015
Publication #:
US20160284798
Pub Dt:
09/29/2016
Title:
SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY
57
Patent #:
10332770
Issue Dt:
06/25/2019
Application #:
14671414
Filing Dt:
03/27/2015
Publication #:
US20160111310
Pub Dt:
04/21/2016
Title:
Wafer Transfer System
58
Patent #:
10014060
Issue Dt:
07/03/2018
Application #:
14675107
Filing Dt:
03/31/2015
Publication #:
US20160225461
Pub Dt:
08/04/2016
Title:
MEMORY SYSTEM AND METHOD FOR REDUCING READ DISTURB ERRORS
59
Patent #:
9613975
Issue Dt:
04/04/2017
Application #:
14675162
Filing Dt:
03/31/2015
Publication #:
US20160293621
Pub Dt:
10/06/2016
Title:
BRIDGE LINE STRUCTURE FOR BIT LINE CONNECTION IN A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
60
Patent #:
10592122
Issue Dt:
03/17/2020
Application #:
14675261
Filing Dt:
03/31/2015
Publication #:
US20160291883
Pub Dt:
10/06/2016
Title:
INHERENT ADAPTIVE TRIMMING
61
Patent #:
9734098
Issue Dt:
08/15/2017
Application #:
14675353
Filing Dt:
03/31/2015
Publication #:
US20160292092
Pub Dt:
10/06/2016
Title:
Memory Bus Management
62
Patent #:
9405476
Issue Dt:
08/02/2016
Application #:
14675521
Filing Dt:
03/31/2015
Publication #:
US20160239223
Pub Dt:
08/18/2016
Title:
SYSTEMS AND METHODS FOR A FILE-LEVEL CACHE
63
Patent #:
10177128
Issue Dt:
01/08/2019
Application #:
14676628
Filing Dt:
04/01/2015
Publication #:
US20160293560
Pub Dt:
10/06/2016
Title:
SEMICONDUCTOR DEVICE INCLUDING SUPPORT PILLARS ON SOLDER MASK
64
Patent #:
9952978
Issue Dt:
04/24/2018
Application #:
14677662
Filing Dt:
04/02/2015
Publication #:
US20160117253
Pub Dt:
04/28/2016
Title:
METHOD FOR IMPROVING MIXED RANDOM PERFORMANCE IN LOW QUEUE DEPTH WORKLOADS
65
Patent #:
9819850
Issue Dt:
11/14/2017
Application #:
14678511
Filing Dt:
04/03/2015
Publication #:
US20160277649
Pub Dt:
09/22/2016
Title:
MODULAR FASHION ACCESSORY
66
Patent #:
9397669
Issue Dt:
07/19/2016
Application #:
14679345
Filing Dt:
04/06/2015
Publication #:
US20150341038
Pub Dt:
11/26/2015
Title:
System and Method for Process and Temperature Calibration of Capacitor-Based Oscillators
67
Patent #:
9799671
Issue Dt:
10/24/2017
Application #:
14680414
Filing Dt:
04/07/2015
Publication #:
US20160300848
Pub Dt:
10/13/2016
Title:
THREE-DIMENSIONAL INTEGRATION SCHEMES FOR REDUCING FLUORINE-INDUCED ELECTRICAL SHORTS
68
Patent #:
9450023
Issue Dt:
09/20/2016
Application #:
14681398
Filing Dt:
04/08/2015
Publication #:
US20160300885
Pub Dt:
10/13/2016
Title:
Vertical Bit Line Non-Volatile Memory With Recessed Word Lines
69
Patent #:
9564219
Issue Dt:
02/07/2017
Application #:
14681627
Filing Dt:
04/08/2015
Publication #:
US20160300607
Pub Dt:
10/13/2016
Title:
CURRENT BASED DETECTION AND RECORDING OF MEMORY HOLE-INTERCONNECT SPACING DEFECTS
70
Patent #:
9710325
Issue Dt:
07/18/2017
Application #:
14681800
Filing Dt:
04/08/2015
Publication #:
US20150212883
Pub Dt:
07/30/2015
Title:
ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE
71
Patent #:
10051733
Issue Dt:
08/14/2018
Application #:
14684619
Filing Dt:
04/13/2015
Publication #:
US20150223335
Pub Dt:
08/06/2015
Title:
PRINTED CIRCUIT BOARD WITH COEXTENSIVE ELECTRICAL CONNECTORS AND CONTACT PAD AREAS
72
Patent #:
10210100
Issue Dt:
02/19/2019
Application #:
14686150
Filing Dt:
04/14/2015
Publication #:
US20150347317
Pub Dt:
12/03/2015
Title:
CONTROLLING OPERATION OF A STORAGE DEVICE BASED ON AN AGE INDICATOR OF THE STORAGE DEVICE
73
Patent #:
9524977
Issue Dt:
12/20/2016
Application #:
14687403
Filing Dt:
04/15/2015
Publication #:
US20160307908
Pub Dt:
10/20/2016
Title:
METAL-SEMICONDUCTOR ALLOY REGION FOR ENHANCING ON CURRENT IN A THREE-DIMENSIONAL MEMORY STRUCTURE
74
Patent #:
9660656
Issue Dt:
05/23/2017
Application #:
14687586
Filing Dt:
04/15/2015
Publication #:
US20160308540
Pub Dt:
10/20/2016
Title:
DELAY COMPENSATION
75
Patent #:
9578779
Issue Dt:
02/21/2017
Application #:
14688954
Filing Dt:
04/16/2015
Publication #:
US20160309611
Pub Dt:
10/20/2016
Title:
FRONT RACK CABLE MANAGEMENT SYSTEM AND APPARATUS
76
Patent #:
9949400
Issue Dt:
04/17/2018
Application #:
14688957
Filing Dt:
04/16/2015
Publication #:
US20160309612
Pub Dt:
10/20/2016
Title:
FRONT RACK CABLE MANAGEMENT SYSTEM AND APPARATUS
77
Patent #:
9406693
Issue Dt:
08/02/2016
Application #:
14690863
Filing Dt:
04/20/2015
Title:
Selective Removal Of Charge-Trapping Layer For Select Gate Transistors And Dummy Memory Cells In 3D Stacked Memory
78
Patent #:
9665298
Issue Dt:
05/30/2017
Application #:
14692447
Filing Dt:
04/21/2015
Publication #:
US20160313940
Pub Dt:
10/27/2016
Title:
METHOD AND SYSTEM TO REDUCE POWER USAGE ON AN I/O INTERFACE
79
Patent #:
9502123
Issue Dt:
11/22/2016
Application #:
14692564
Filing Dt:
04/21/2015
Publication #:
US20160314847
Pub Dt:
10/27/2016
Title:
ADAPTIVE BLOCK PARAMETERS
80
Patent #:
10073714
Issue Dt:
09/11/2018
Application #:
14693685
Filing Dt:
04/22/2015
Publication #:
US20160266928
Pub Dt:
09/15/2016
Title:
TASK QUEUES
81
Patent #:
9965323
Issue Dt:
05/08/2018
Application #:
14693784
Filing Dt:
04/22/2015
Publication #:
US20160266934
Pub Dt:
09/15/2016
Title:
TASK QUEUES
82
Patent #:
9640544
Issue Dt:
05/02/2017
Application #:
14695426
Filing Dt:
04/24/2015
Publication #:
US20160315091
Pub Dt:
10/27/2016
Title:
INTEGRATED CIRCUIT WITH HYDROGEN ABSORPTION STRUCTURE
83
Patent #:
9886080
Issue Dt:
02/06/2018
Application #:
14698255
Filing Dt:
04/28/2015
Publication #:
US20160188245
Pub Dt:
06/30/2016
Title:
LOW VOLTAGE DETECTION AND INITIALIZATION FOR NON-VOLATILE MEMORY SYSTEMS
84
Patent #:
10133483
Issue Dt:
11/20/2018
Application #:
14698511
Filing Dt:
04/28/2015
Publication #:
US20160320971
Pub Dt:
11/03/2016
Title:
MEMORY SYSTEM AND METHOD FOR DIFFERENTIAL THERMAL THROTTLING
85
Patent #:
9612904
Issue Dt:
04/04/2017
Application #:
14698530
Filing Dt:
04/28/2015
Publication #:
US20160224418
Pub Dt:
08/04/2016
Title:
Memory System and Method for Securing Volatile Memory During Sleep Mode Using the Same ECC Module Used to Secure Non-Volatile Memory During Active Mode
86
Patent #:
9478303
Issue Dt:
10/25/2016
Application #:
14699388
Filing Dt:
04/29/2015
Publication #:
US20160322113
Pub Dt:
11/03/2016
Title:
SYSTEM AND METHOD FOR MEASURING DATA RETENTION IN A NON-VOLATILE MEMORY
87
Patent #:
9502428
Issue Dt:
11/22/2016
Application #:
14699506
Filing Dt:
04/29/2015
Publication #:
US20160322371
Pub Dt:
11/03/2016
Title:
Sidewall Assisted Process for Wide and Narrow Line Formation
88
Patent #:
9443867
Issue Dt:
09/13/2016
Application #:
14699631
Filing Dt:
04/29/2015
Publication #:
US20150318300
Pub Dt:
11/05/2015
Title:
METHOD OF MAKING DAMASCENE SELECT GATE IN MEMORY DEVICE
89
Patent #:
9397046
Issue Dt:
07/19/2016
Application #:
14699749
Filing Dt:
04/29/2015
Title:
FLUORINE-FREE WORD LINES FOR THREE-DIMENSIONAL MEMORY DEVICES
90
Patent #:
9934858
Issue Dt:
04/03/2018
Application #:
14700500
Filing Dt:
04/30/2015
Publication #:
US20160322108
Pub Dt:
11/03/2016
Title:
USE OF DUMMY WORD LINES FOR METADATA STORAGE
91
Patent #:
9542286
Issue Dt:
01/10/2017
Application #:
14700522
Filing Dt:
04/30/2015
Publication #:
US20160092325
Pub Dt:
03/31/2016
Title:
FAILURE LOGGING MECHANISM TO REDUCE GARBAGE COLLECTION TIME IN PARTIALLY REUSED BAD BLOCKS
92
Patent #:
9582358
Issue Dt:
02/28/2017
Application #:
14700543
Filing Dt:
04/30/2015
Publication #:
US20160092302
Pub Dt:
03/31/2016
Title:
INITIALIZATION SCHEME DURING DUAL PROGRAMMING OF A MEMORY SYSTEM
93
Patent #:
NONE
Issue Dt:
Application #:
14700716
Filing Dt:
04/30/2015
Publication #:
US20160093383
Pub Dt:
03/31/2016
Title:
METHOD AND APPARATUS FOR RELOCATING DATA IN NON-VOLATILE MEMORY
94
Patent #:
9875039
Issue Dt:
01/23/2018
Application #:
14700747
Filing Dt:
04/30/2015
Publication #:
US20160092122
Pub Dt:
03/31/2016
Title:
METHOD AND APPARATUS FOR WEAR-LEVELLING NON-VOLATILE MEMORY
95
Patent #:
NONE
Issue Dt:
Application #:
14700776
Filing Dt:
04/30/2015
Publication #:
US20160094339
Pub Dt:
03/31/2016
Title:
SCRAMBLING SCHEMES FOR SCRAMBLING AND DESCRAMBLING DATA
96
Patent #:
9841910
Issue Dt:
12/12/2017
Application #:
14700814
Filing Dt:
04/30/2015
Publication #:
US20160092128
Pub Dt:
03/31/2016
Title:
MOVING AND COMMITTING VALID DATA ON A SET-BY-SET BASIS
97
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9720612
Issue Dt:
08/01/2017
Application #:
14700950
Filing Dt:
04/30/2015
Publication #:
US20160321000
Pub Dt:
11/03/2016
Title:
BIASING SCHEMES FOR STORAGE OF BITS IN UNRELIABLE STORAGE LOCATIONS
98
Patent #:
NONE
Issue Dt:
Application #:
14701080
Filing Dt:
04/30/2015
Publication #:
US20160322965
Pub Dt:
11/03/2016
Title:
DIFFERENTIAL COMPARATOR WITH STABLE OFFSET
99
Patent #:
9780809
Issue Dt:
10/03/2017
Application #:
14701130
Filing Dt:
04/30/2015
Publication #:
US20160322990
Pub Dt:
11/03/2016
Title:
TRACKING AND USE OF TRACKED BIT VALUES FOR ENCODING AND DECODING DATA IN UNRELIABLE MEMORY
100
Patent #:
9778863
Issue Dt:
10/03/2017
Application #:
14701158
Filing Dt:
04/30/2015
Publication #:
US20160092129
Pub Dt:
03/31/2016
Title:
SYSTEM AND METHOD FOR FOLDING PARTIAL BLOCKS INTO MULTI-LEVEL CELL MEMORY BLOCKS
Assignor
1
SANDISK TECHNOLOGIES INC
Exec Dt:
05/16/2016
Assignee
1
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY
SUITE 325
PLANO, TEXAS 75024
Correspondence name and address
SANDISK
951 SANDISK DRIVE
PATENT DEPARTMENT/SIMONA BENJAMIN
MILPITAS, CA 95035

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