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Reel/Frame:038954/0001   Pages: 961
Recorded: 06/02/2016
Attorney Dkt #:065664/0012
Conveyance: PATENT SECURITY AGREEMENT
Total properties: 18021
Page 52 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
6866566
Issue Dt:
03/15/2005
Application #:
09939432
Filing Dt:
08/24/2001
Publication #:
US20030060144
Pub Dt:
03/27/2003
Title:
APPARATUS AND METHOD FOR CONDITIONING A CONTACT SURFACE OF A PROCESSING PAD USED IN PROCESSING MICROELECTRONIC WORKPIECES
2
Patent #:
6753264
Issue Dt:
06/22/2004
Application #:
09939651
Filing Dt:
08/28/2001
Publication #:
US20020019140
Pub Dt:
02/14/2002
Title:
METHOD OF CONTROLLING STRIATIONS AND CD LOSS IN CONTACT OXIDE ETCH
3
Patent #:
6429044
Issue Dt:
08/06/2002
Application #:
09939652
Filing Dt:
08/28/2001
Publication #:
US20020024116
Pub Dt:
02/28/2002
Title:
METHOD AND APPARATUS FOR MAGNETIC SHIELDING OF AN INTEGRATED CIRCUIT
4
Patent #:
6577525
Issue Dt:
06/10/2003
Application #:
09939655
Filing Dt:
08/28/2001
Publication #:
US20030043616
Pub Dt:
03/06/2003
Title:
SENSING METHOD AND APPARATUS FOR RESISTANCE MEMORY DEVICE
5
Patent #:
6436844
Issue Dt:
08/20/2002
Application #:
09939905
Filing Dt:
08/27/2001
Publication #:
US20020001970
Pub Dt:
01/03/2002
Title:
SEMICONDUCTOR STRUCTURE USEFUL IN A SELF-ALIGNED CONTACT ETCH AND METHOD FOR MAKING SAME
6
Patent #:
6424168
Issue Dt:
07/23/2002
Application #:
09940008
Filing Dt:
08/27/2001
Publication #:
US20020050836
Pub Dt:
05/02/2002
Title:
REDUCED TERMINAL TESTING SYSTEM
7
Patent #:
6546512
Issue Dt:
04/08/2003
Application #:
09940010
Filing Dt:
08/27/2001
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING COMPRESSION CIRCUITRY FOR COMPRESSING TEST DATA, AND THE TEST SYSTEM AND METHOD FOR UTILIZING THE SEMICONDUCTOR INTEGRATED CIRCUIT
8
Patent #:
6439450
Issue Dt:
08/27/2002
Application #:
09940203
Filing Dt:
08/27/2001
Publication #:
US20020023943
Pub Dt:
02/28/2002
Title:
CONCAVE FACE WIRE BOND CAPILLARY
9
Patent #:
6667554
Issue Dt:
12/23/2003
Application #:
09940229
Filing Dt:
08/27/2001
Publication #:
US20020009879
Pub Dt:
01/24/2002
Title:
EXPANDED IMPLANTATION OF CONTACT HOLES
10
Patent #:
6509245
Issue Dt:
01/21/2003
Application #:
09940328
Filing Dt:
08/27/2001
Publication #:
US20020155677
Pub Dt:
10/24/2002
Title:
ELECTRONIC DEVICE WITH INTERLEAVED PORTIONS FOR USE IN INTEGRATED CIRCUITS
11
Patent #:
6556068
Issue Dt:
04/29/2003
Application #:
09940333
Filing Dt:
08/27/2001
Publication #:
US20020024378
Pub Dt:
02/28/2002
Title:
THRESHOLD VOLTAGE COMPENSATION CIRCUITS FOR LOW VOLTAGE AND LOW POWER CMOS INTEGRATED CIRCUITS
12
Patent #:
7164188
Issue Dt:
01/16/2007
Application #:
09940792
Filing Dt:
08/29/2001
Publication #:
US20020070419
Pub Dt:
06/13/2002
Title:
BURIED CONDUCTOR PATTERNS FORMED BY SURFACE TRANSFORMATION OF EMPTY SPACES IN SOLID STATE MATERIALS
13
Patent #:
6452867
Issue Dt:
09/17/2002
Application #:
09940915
Filing Dt:
08/28/2001
Publication #:
US20020024872
Pub Dt:
02/28/2002
Title:
FULL PAGE INCREMENT/DECREMENT BURST FOR DDR SDRAM/SGRAM
14
Patent #:
6529421
Issue Dt:
03/04/2003
Application #:
09940968
Filing Dt:
08/28/2001
Publication #:
US20030043640
Pub Dt:
03/06/2003
Title:
SRAM ARRAY WITH TEMPERATURE-COMPENSATED THRESHOLD VOLTAGE
15
Patent #:
6510080
Issue Dt:
01/21/2003
Application #:
09940976
Filing Dt:
08/28/2001
Title:
THREE TERMINAL MAGNETIC RANDOM ACCESS MEMORY
16
Patent #:
6515353
Issue Dt:
02/04/2003
Application #:
09941020
Filing Dt:
08/28/2001
Publication #:
US20020024857
Pub Dt:
02/28/2002
Title:
MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE
17
Patent #:
6434066
Issue Dt:
08/13/2002
Application #:
09941021
Filing Dt:
08/28/2001
Publication #:
US20020048199
Pub Dt:
04/25/2002
Title:
DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
18
Patent #:
7117139
Issue Dt:
10/03/2006
Application #:
09941068
Filing Dt:
08/28/2001
Publication #:
US20030093584
Pub Dt:
05/15/2003
Title:
CO-SIMULATION OF VERILOG/PLI AND SYSTEM C MODULES USING REMOTE PROCEDURE CALL
19
Patent #:
6584030
Issue Dt:
06/24/2003
Application #:
09941130
Filing Dt:
08/28/2001
Publication #:
US20030043677
Pub Dt:
03/06/2003
Title:
MEMORY CIRCUIT REGULATION SYSTEM AND METHOD
20
Patent #:
6456518
Issue Dt:
09/24/2002
Application #:
09941201
Filing Dt:
08/28/2001
Publication #:
US20020024144
Pub Dt:
02/28/2002
Title:
BI-LEVEL DIGIT LINE ARCHITECTURE FOR HIGH DENSITY DRAMS
21
Patent #:
6472764
Issue Dt:
10/29/2002
Application #:
09941203
Filing Dt:
08/28/2001
Publication #:
US20020024128
Pub Dt:
02/28/2002
Title:
METHOD AND APPARATUS FOR IMPLEMENTING SELECTED FUNCTIONALITY ON AN INTEGRATED CIRCUIT DEVICE
22
Patent #:
6620648
Issue Dt:
09/16/2003
Application #:
09941315
Filing Dt:
08/29/2001
Publication #:
US20020024151
Pub Dt:
02/28/2002
Title:
MULTI-CHIP MODULE WITH EXTENSION
23
Patent #:
6512302
Issue Dt:
01/28/2003
Application #:
09941317
Filing Dt:
08/28/2001
Publication #:
US20020043658
Pub Dt:
04/18/2002
Title:
APPARATUS AND METHODS OF PACKAGING AND TESTING DIE
24
Patent #:
7941056
Issue Dt:
05/10/2011
Application #:
09941557
Filing Dt:
08/30/2001
Publication #:
US20030043426
Pub Dt:
03/06/2003
Title:
OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS
25
Patent #:
6628561
Issue Dt:
09/30/2003
Application #:
09941602
Filing Dt:
08/30/2001
Publication #:
US20030043676
Pub Dt:
03/06/2003
Title:
SMALL ANTI-FUSE CIRCUIT TO FACILITATE PARALLEL FUSE BLOWING
26
Patent #:
6441628
Issue Dt:
08/27/2002
Application #:
09941749
Filing Dt:
08/29/2001
Publication #:
US20020047720
Pub Dt:
04/25/2002
Title:
CSP BGA TEST SOCKET WITH INSERT AND METHOD
27
Patent #:
7250247
Issue Dt:
07/31/2007
Application #:
09941760
Filing Dt:
08/30/2001
Publication #:
US20020039820
Pub Dt:
04/04/2002
Title:
PHOTOLITHOGRAPHIC STRUCTURES USING MULTIPLE ANTI-REFLECTING COATINGS
28
Patent #:
6931480
Issue Dt:
08/16/2005
Application #:
09941763
Filing Dt:
08/30/2001
Publication #:
US20030046487
Pub Dt:
03/06/2003
Title:
METHOD AND APPARATUS FOR REFRESHING MEMORY TO PRESERVE DATA INTEGRITY
29
Patent #:
7129128
Issue Dt:
10/31/2006
Application #:
09941827
Filing Dt:
08/29/2001
Publication #:
US20030042526
Pub Dt:
03/06/2003
Title:
METHOD OF IMPROVED HIGH K DIELECTRIC-POLYSILICON INTERFACE FOR CMOS DEVICES
30
Patent #:
7049693
Issue Dt:
05/23/2006
Application #:
09941853
Filing Dt:
08/29/2001
Publication #:
US20030042595
Pub Dt:
03/06/2003
Title:
ELECTRICAL CONTACT ARRAY FOR SUBSTRATE ASSEMBLIES
31
Patent #:
6746952
Issue Dt:
06/08/2004
Application #:
09942108
Filing Dt:
08/29/2001
Publication #:
US20030042607
Pub Dt:
03/06/2003
Title:
DIFFUSION BARRIER LAYER FOR SEMICONDUCTOR WAFER FABRICATION
32
Patent #:
6429890
Issue Dt:
08/06/2002
Application #:
09942136
Filing Dt:
08/29/2001
Publication #:
US20020030732
Pub Dt:
03/14/2002
Title:
LASER MARKING TECHNIQUES
33
Patent #:
6653721
Issue Dt:
11/25/2003
Application #:
09942140
Filing Dt:
08/29/2001
Publication #:
US20020030253
Pub Dt:
03/14/2002
Title:
LOC SEMICONDUCTOR ASSEMBLED WITH ROOM TEMPERATURE ADHESIVE
34
Patent #:
6518098
Issue Dt:
02/11/2003
Application #:
09942178
Filing Dt:
08/29/2001
Publication #:
US20020024133
Pub Dt:
02/28/2002
Title:
IC PACKAGE WITH DUAL HEAT SPREADERS
35
Patent #:
6500697
Issue Dt:
12/31/2002
Application #:
09942182
Filing Dt:
08/29/2001
Publication #:
US20020048852
Pub Dt:
04/25/2002
Title:
LEADFRAMES INCLUDING OFFSETS EXTENDING FROM A MAJOR PLANE THEREOF, PACKAGED SEMICONDUCTOR DEVICES INCLUDING SAME, AND METHODS OF DESIGNING AND FABRICATING SUCH LEADFRAMES
36
Patent #:
6613673
Issue Dt:
09/02/2003
Application #:
09942191
Filing Dt:
08/29/2001
Publication #:
US20020004304
Pub Dt:
01/10/2002
Title:
TECHNIQUE FOR ELIMINATION OF PITTING ON SILICON SUBSTRATE DURING GATE STACK ETCH
37
Patent #:
6556467
Issue Dt:
04/29/2003
Application #:
09942207
Filing Dt:
08/29/2001
Publication #:
US20020118585
Pub Dt:
08/29/2002
Title:
GATE VOLTAGE TESTKEY FOR ISOLATION TRANSISTOR
38
Patent #:
6426484
Issue Dt:
07/30/2002
Application #:
09942221
Filing Dt:
08/29/2001
Publication #:
US20020108940
Pub Dt:
08/15/2002
Title:
CIRCUIT AND METHOD FOR HEATING AN ADHESIVE TO PACKAGE OR REWORK A SEMICONDUCTOR DIE
39
Patent #:
6612027
Issue Dt:
09/02/2003
Application #:
09942246
Filing Dt:
08/29/2001
Publication #:
US20020004981
Pub Dt:
01/17/2002
Title:
METHOD AND APPARATUS FOR FORMING METAL CONTACTS ON A SUBSTRATE
40
Patent #:
6525943
Issue Dt:
02/25/2003
Application #:
09942247
Filing Dt:
08/29/2001
Publication #:
US20020024798
Pub Dt:
02/28/2002
Title:
HEAT SINK WITH ALIGNMENT AND RETAINING FEATURES
41
Patent #:
6674672
Issue Dt:
01/06/2004
Application #:
09942284
Filing Dt:
08/27/2001
Publication #:
US20020031028
Pub Dt:
03/14/2002
Title:
THRESHOLD VOLTAGE COMPENSATION CIRCUITS FOR LOW VOLTAGE AND LOW POWER CMOS INTEGRATED CIRCUITS
42
Patent #:
6789155
Issue Dt:
09/07/2004
Application #:
09942389
Filing Dt:
08/29/2001
Publication #:
US20030046477
Pub Dt:
03/06/2003
Title:
SYSTEM AND METHOD FOR CONTROLLING MULTI-BANK EMBEDDED DRAM
43
Patent #:
6639424
Issue Dt:
10/28/2003
Application #:
09942681
Filing Dt:
08/31/2001
Publication #:
US20030042932
Pub Dt:
03/06/2003
Title:
COMBINED DYNAMIC LOGIC GATE AND LEVEL SHIFTER AND METHOD EMPLOYING SAME
44
Patent #:
7042043
Issue Dt:
05/09/2006
Application #:
09943134
Filing Dt:
08/30/2001
Publication #:
US20030042527
Pub Dt:
03/06/2003
Title:
PROGRAMMABLE ARRAY LOGIC OR MEMORY DEVICES WITH ASYMMETRICAL TUNNEL BARRIERS
45
Patent #:
6444041
Issue Dt:
09/03/2002
Application #:
09943146
Filing Dt:
08/30/2001
Publication #:
US20020151159
Pub Dt:
10/17/2002
Title:
METHODS, COMPLEXES, AND SYSTEM FOR FORMING METAL-CONTAINING FILMS
46
Patent #:
6784018
Issue Dt:
08/31/2004
Application #:
09943187
Filing Dt:
08/29/2001
Publication #:
US20030049912
Pub Dt:
03/13/2003
Title:
METHOD OF FORMING CHALCOGENIDE COMPRISING DEVICES AND METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY
47
Patent #:
6881623
Issue Dt:
04/19/2005
Application #:
09943190
Filing Dt:
08/29/2001
Publication #:
US20030045054
Pub Dt:
03/06/2003
Title:
METHOD OF FORMING CHALCOGENIDE COMPRISING DEVICES, METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY, AND A CHALCOGENIDE COMPRISING DEVICE
48
Patent #:
6955940
Issue Dt:
10/18/2005
Application #:
09943199
Filing Dt:
08/29/2001
Publication #:
US20030045049
Pub Dt:
03/06/2003
Title:
METHOD OF FORMING CHALCOGENIDE COMPRISING DEVICES
49
Patent #:
6794709
Issue Dt:
09/21/2004
Application #:
09943324
Filing Dt:
08/30/2001
Publication #:
US20020004276
Pub Dt:
01/10/2002
Title:
STRUCTURE AND METHOD FOR DUAL GATE OXIDE THICKNESSES
50
Patent #:
6621755
Issue Dt:
09/16/2003
Application #:
09943367
Filing Dt:
08/30/2001
Publication #:
US20030048685
Pub Dt:
03/13/2003
Title:
TESTMODE TO INCREASE ACCLERATION IN BURN-IN
51
Patent #:
6511906
Issue Dt:
01/28/2003
Application #:
09943381
Filing Dt:
08/30/2001
Title:
SELECTIVE CMP SCHEME
52
Patent #:
6833308
Issue Dt:
12/21/2004
Application #:
09943393
Filing Dt:
08/30/2001
Publication #:
US20020004277
Pub Dt:
01/10/2002
Title:
STRUCTURE AND METHOD FOR DUAL GATE OXIDE THICKNESSES
53
Patent #:
6720221
Issue Dt:
04/13/2004
Application #:
09943398
Filing Dt:
08/30/2001
Title:
STRUCTURE AND METHOD FOR DUAL GATE OXIDE THICKNESSES
54
Patent #:
6709958
Issue Dt:
03/23/2004
Application #:
09943426
Filing Dt:
08/30/2001
Publication #:
US20030186504
Pub Dt:
10/02/2003
Title:
INTEGRATED CIRCUIT DEVICE AND FABRICATION USING METAL-DOPED CHALCOGENIDE MATERIALS
55
Patent #:
6560161
Issue Dt:
05/06/2003
Application #:
09943473
Filing Dt:
08/30/2001
Publication #:
US20030076733
Pub Dt:
04/24/2003
Title:
SYNCHRONOUS FLASH MEMORY COMMAND SEQUENCE
56
Patent #:
6549468
Issue Dt:
04/15/2003
Application #:
09943474
Filing Dt:
08/30/2001
Publication #:
US20030043636
Pub Dt:
03/06/2003
Title:
NON-VOLATILE MEMORY WITH ADDRESS DESCRAMBLING
57
Patent #:
6444818
Issue Dt:
09/03/2002
Application #:
09943478
Filing Dt:
08/30/2001
Publication #:
US20020016065
Pub Dt:
02/07/2002
Title:
METAL COMPLEXES WITH CHELATING C-, N-DONOR LIGANDS FOR FORMING METAL-CONTAINING FILMS
58
Patent #:
7057935
Issue Dt:
06/06/2006
Application #:
09943479
Filing Dt:
08/30/2001
Publication #:
US20030048664
Pub Dt:
03/13/2003
Title:
ERASE VERIFY FOR NON-VOLATILE MEMORY
59
Patent #:
6597609
Issue Dt:
07/22/2003
Application #:
09943480
Filing Dt:
08/30/2001
Publication #:
US20030043661
Pub Dt:
03/06/2003
Title:
NON-VOLATILE MEMORY WITH TEST ROWS FOR DISTURB DETECTION
60
Patent #:
6983360
Issue Dt:
01/03/2006
Application #:
09943586
Filing Dt:
08/30/2001
Publication #:
US20030046523
Pub Dt:
03/06/2003
Title:
PROGRAM LOADING MECHANISM THROUGH A SINGLE INPUT DATA PATH
61
Patent #:
6930936
Issue Dt:
08/16/2005
Application #:
09943642
Filing Dt:
08/30/2001
Publication #:
US20020118580
Pub Dt:
08/29/2002
Title:
DATA COMPRESSION READ MODE FOR MEMORY TESTING
62
Patent #:
6654272
Issue Dt:
11/25/2003
Application #:
09943643
Filing Dt:
08/30/2001
Publication #:
US20020122331
Pub Dt:
09/05/2002
Title:
FLASH CELL FUSE CIRCUIT
63
Patent #:
6452839
Issue Dt:
09/17/2002
Application #:
09943726
Filing Dt:
08/29/2001
Publication #:
US20020041519
Pub Dt:
04/11/2002
Title:
METHOD FOR ERASING DATA FROM A SINGLE ELECTRON RESSISTOR MEMORY
64
Patent #:
6656289
Issue Dt:
12/02/2003
Application #:
09943844
Filing Dt:
08/30/2001
Publication #:
US20020023669
Pub Dt:
02/28/2002
Title:
METHOD OF REDUCING WATER SPOTTING AND OXIDE GROWTH ON A SEMICONDUCTOR STRUCTURE
65
Patent #:
6445067
Issue Dt:
09/03/2002
Application #:
09943845
Filing Dt:
08/30/2001
Publication #:
US20020027280
Pub Dt:
03/07/2002
Title:
INTEGRATED CIRCUIT PACKAGE ELECTRICAL ENHANCEMENT
66
Patent #:
6650013
Issue Dt:
11/18/2003
Application #:
09943897
Filing Dt:
08/30/2001
Publication #:
US20030049882
Pub Dt:
03/13/2003
Title:
METHOD OF MANUFACTURING WIRE BONDED MICROELECTRONIC DEVICE ASSEMBLIES
67
Patent #:
6919229
Issue Dt:
07/19/2005
Application #:
09943967
Filing Dt:
08/30/2001
Publication #:
US20020029741
Pub Dt:
03/14/2002
Title:
METHOD FOR CONTROLLING THE DEPTH OF IMMERSION OF A SEMICONDUCTOR ELEMENT IN AN EXPOSED SURFACE OF A VISCOUS FLUID
68
Patent #:
6956908
Issue Dt:
10/18/2005
Application #:
09943968
Filing Dt:
08/30/2001
Publication #:
US20030043936
Pub Dt:
03/06/2003
Title:
Technique to simultaneously distribute clock signals and data on integrated circuits, interposers and circuit boards
69
Patent #:
6495902
Issue Dt:
12/17/2002
Application #:
09943993
Filing Dt:
08/30/2001
Publication #:
US20020005564
Pub Dt:
01/17/2002
Title:
FUSE FOR USE IN A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICES INCLUDING THE FUSE
70
Patent #:
6432619
Issue Dt:
08/13/2002
Application #:
09943995
Filing Dt:
08/30/2001
Publication #:
US20020009675
Pub Dt:
01/24/2002
Title:
METHOD FOR REDUCING PHOTOLITHOGRAPHIC STEPS IN A SEMICONDUCTOR INTERCONNECT PROCESS
71
Patent #:
6624072
Issue Dt:
09/23/2003
Application #:
09944224
Filing Dt:
08/29/2001
Publication #:
US20020028570
Pub Dt:
03/07/2002
Title:
ORGANOMETALLIC COMPOUND MIXTURES IN CHEMICAL VAPOR DEPOSITION
72
Patent #:
6890384
Issue Dt:
05/10/2005
Application #:
09944233
Filing Dt:
08/30/2001
Publication #:
US20020029742
Pub Dt:
03/14/2002
Title:
APPARATUS AND METHOD FOR MODIFYING THE CONFIGURATION OF AN EXPOSED SURFACE OF A VISCOUS FLUID
73
Patent #:
6434059
Issue Dt:
08/13/2002
Application #:
09944238
Filing Dt:
08/30/2001
Publication #:
US20020048206
Pub Dt:
04/25/2002
Title:
METHOD AND APPARATUS FOR REDUCING BLEED CURRENTS WITHIN A DRAM ARRAY HAVING ROW-TO-COLUMN SHORTS
74
Patent #:
6548376
Issue Dt:
04/15/2003
Application #:
09944245
Filing Dt:
08/30/2001
Publication #:
US20030045072
Pub Dt:
03/06/2003
Title:
METHODS OF THINNING MICROELECTRONIC WORKPIECES
75
Patent #:
6876066
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Title:
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Title:
APPARATUS AND METHOD FOR GENERATING AN OSCILLATING SIGNAL
Assignor
1
MICRON TECHNOLOGY, INC.
Exec Dt:
04/26/2016
Assignee
1
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR
BALTIMORE, MARYLAND 21231
Correspondence name and address
GENEVIEVE DORMENT, ESQ.
SIMPSON THACHER & BARTLETT LLP
425 LEXINGTON AVENUE
NEW YORK, NY 10017

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