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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	039428/0845			Pages:	7
		Recorded:	07/22/2016
Attorney Dkt #:	F164428
Conveyance:	PATENT RELEASE

Total properties: 26

Patent #:	6147510	Issue Dt:	11/14/2000	Application #:	09114119	Filing Dt:	07/13/1998
Title:	INTEGRATED CIRCUIT FOR HANDLING BUFFER CONTENTION AND METHOD THEREOF

Patent #:	6111796	Issue Dt:	08/29/2000	Application #:	09259454	Filing Dt:	03/01/1999
Title:	PROGRAMMABLE DELAY CONTROL IN A MEMORY

Patent #:	5978286	Issue Dt:	11/02/1999	Application #:	09259455	Filing Dt:	03/01/1999
Title:	TIMING CONTROL OF AMPLIFIERS IN A MEMORY

Patent #:	6274478	Issue Dt:	08/14/2001	Application #:	09352136	Filing Dt:	07/13/1999
Title:	METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS

Patent #:	6108266	Issue Dt:	08/22/2000	Application #:	09428440	Filing Dt:	10/28/1999
Title:	MEMORY UTILIZING A PROGRAMMABLE DELAY TO CONTROL ADDRESS BUFFERS

Patent #:	6385101	Issue Dt:	05/07/2002	Application #:	09543532	Filing Dt:	04/06/2000
Title:	PROGRAMMABLE DELAY CONTROL FOR SENSE AMPLIFIERS IN A MEMORY

Patent #:	6380760	Issue Dt:	04/30/2002	Application #:	09636493	Filing Dt:	08/11/2000
Title:	Integrated circuit for handling buffer contention and method thereof

Patent #:	6444569	Issue Dt:	09/03/2002	Application #:	09835276	Filing Dt:	04/16/2001
Publication #:	US20010027083	Pub Dt:	10/04/2001
Title:	METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS

Patent #:	6657502	Issue Dt:	12/02/2003	Application #:	09968171	Filing Dt:	10/01/2001
Publication #:	US20030062960	Pub Dt:	04/03/2003
Title:	MULTIPHASE VOLTAGE CONTROLLED OSCILLATOR

Patent #:	6657477	Issue Dt:	12/02/2003	Application #:	10139197	Filing Dt:	05/06/2002
Publication #:	US20020163380	Pub Dt:	11/07/2002
Title:	INTEGRATED CIRCUIT

Patent #:	6573173	Issue Dt:	06/03/2003	Application #:	10175637	Filing Dt:	06/20/2002
Publication #:	US20020151167	Pub Dt:	10/17/2002
Title:	METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS

Patent #:	6765773	Issue Dt:	07/20/2004	Application #:	10222235	Filing Dt:	08/16/2002
Publication #:	US20030042499	Pub Dt:	03/06/2003
Title:	ESD PROTECTION FOR A CMOS OUTPUT STAGE

Patent #:	6778016	Issue Dt:	08/17/2004	Application #:	10287199	Filing Dt:	11/04/2002
Publication #:	US20040085130	Pub Dt:	05/06/2004
Title:	SIMPLE SELF-BIASED CASCODE AMPLIFIER CIRCUIT

Patent #:	7523331	Issue Dt:	04/21/2009	Application #:	10571636	Filing Dt:	03/13/2006
Publication #:	US20070055901	Pub Dt:	03/08/2007
Title:	POWER SAVING OPERATION OF AN APPARATUS WITH A CACHE MEMORY

Patent #:	7247552	Issue Dt:	07/24/2007	Application #:	11033009	Filing Dt:	01/11/2005
Publication #:	US20060154470	Pub Dt:	07/13/2006
Title:	INTEGRATED CIRCUIT HAVING STRUCTURAL SUPPORT FOR A FLIP-CHIP INTERCONNECT PAD AND METHOD THEREFOR

Patent #:	7246027	Issue Dt:	07/17/2007	Application #:	11078150	Filing Dt:	03/11/2005
Publication #:	US20060217920	Pub Dt:	09/28/2006
Title:	POWER OPTIMIZATION OF A MIXED-SIGNAL SYSTEM ON AN INTEGRATED CIRCUIT

Patent #:	7268588	Issue Dt:	09/11/2007	Application #:	11170398	Filing Dt:	06/29/2005
Publication #:	US20070008001	Pub Dt:	01/11/2007
Title:	CASCADABLE LEVEL SHIFTER CELL

Patent #:	7709303	Issue Dt:	05/04/2010	Application #:	11328668	Filing Dt:	01/10/2006
Publication #:	US20070161171	Pub Dt:	07/12/2007
Title:	PROCESS FOR FORMING AN ELECTRONIC DEVICE INCLUDING A FIN-TYPE STRUCTURE

Patent #:	7286423	Issue Dt:	10/23/2007	Application #:	11362694	Filing Dt:	02/27/2006
Publication #:	US20070201298	Pub Dt:	08/30/2007
Title:	BIT LINE PRECHARGE IN EMBEDDED MEMORY

Patent #:	7440354	Issue Dt:	10/21/2008	Application #:	11433998	Filing Dt:	05/15/2006
Publication #:	US20070263474	Pub Dt:	11/15/2007
Title:	MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF

Patent #:	7443745	Issue Dt:	10/28/2008	Application #:	11612626	Filing Dt:	12/19/2006
Publication #:	US20080144409	Pub Dt:	06/19/2008
Title:	BYTE WRITEABLE MEMORY WITH BIT-COLUMN VOLTAGE SELECTION AND COLUMN REDUNDANCY

Patent #:	7880516	Issue Dt:	02/01/2011	Application #:	11910062	Filing Dt:	09/28/2007
Publication #:	US20080265958	Pub Dt:	10/30/2008
Title:	METHOD FOR NOISE REDUCTION IN A PHASE LOCKED LOOP AND A DEVICE HAVING NOISE REDUCTION CAPABILITIES

Patent #:	8020014	Issue Dt:	09/13/2011	Application #:	11914079	Filing Dt:	11/09/2007
Publication #:	US20080209248	Pub Dt:	08/28/2008
Title:	METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES

Patent #:	7706207	Issue Dt:	04/27/2010	Application #:	12209477	Filing Dt:	09/12/2008
Publication #:	US20090021990	Pub Dt:	01/22/2009
Title:	MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF

Patent #:	8566836	Issue Dt:	10/22/2013	Application #:	12618311	Filing Dt:	11/13/2009
Publication #:	US20110119672	Pub Dt:	05/19/2011
Title:	Multi-Core System on Chip

Patent #:	8638161	Issue Dt:	01/28/2014	Application #:	13187302	Filing Dt:	07/20/2011
Publication #:	US20130021090	Pub Dt:	01/24/2013
Title:	POWER CONTROL DEVICE AND METHOD THEREFOR

Assignors

MORGAN STANLEY SENIOR FUNDING, INC., AS GLOBAL COLLATERAL AGENT

Exec Dt:

07/12/2016

MORGAN STANLEY SENIOR FUNDING, INC., AS RCF ADMINISTRATIVE AGENT

Exec Dt:

07/12/2016

MORGAN STANLEY SENIOR FUNDING, INC., AS THE NOTES COLLATERAL AGENT

Exec Dt:

07/12/2016

Assignee

NXP B.V.

HIGH TECH CAMPUS 60

EINDHOVEN 5656 AG, NETHERLANDS

Correspondence name and address
	JOANNA MCCALL
	1025 VERMONT AVE NW, SUITE 1130
	NATIONAL CORPORATE RESEARCH, LTD
	WASHINGTON, DC 20005

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