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Patent #:
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|
Issue Dt:
|
07/16/2002
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Application #:
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09836064
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Filing Dt:
|
04/16/2001
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|
Publication #:
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Pub Dt:
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09/20/2001
| | | | |
|
Title:
|
STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS
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|
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|
Patent #:
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|
Issue Dt:
|
11/15/2005
|
Application #:
|
09836065
|
Filing Dt:
|
04/16/2001
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|
Publication #:
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|
Pub Dt:
|
10/17/2002
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
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|
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|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09842966
|
Filing Dt:
|
04/25/2001
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|
Title:
|
PRECISION CRYSTAL OSCILLATOR CIRCUIT USED IN MICROCONTROLLER
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|
Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
|
09844692
|
Filing Dt:
|
04/27/2001
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|
Publication #:
|
|
Pub Dt:
|
10/31/2002
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR REDUCING THINNING OF FIELD ISOLATION STRUCTURES IN A FLASH MEMORY DEVICE
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|
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|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09844785
|
Filing Dt:
|
04/27/2001
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|
Title:
|
MASTER/DUAL-SLAVE D TYPE FLIP-FLOP
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|
Patent #:
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|
Issue Dt:
|
12/13/2005
|
Application #:
|
09846146
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Filing Dt:
|
04/30/2001
|
|
Title:
|
CIRCUIT FOR CORRECTION OF DIFFERENTIAL SIGNAL PATH DELAYS IN A PLL
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|
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Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
|
09848568
|
Filing Dt:
|
05/02/2001
|
|
Title:
|
FLEXIBLE INPUT STRUCTURE FOR AN EMBEDDED MEMORY
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|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
09849047
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Filing Dt:
|
05/04/2001
|
|
Title:
|
BURIED LAYER SUBSTRATE ISOLATION IN INTEGRATED CIRCUITS
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|
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|
Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
|
09849164
|
Filing Dt:
|
05/04/2001
|
|
Title:
|
REDUCED STATIC PHASE ERROR CMOS PLL CHARGE PUMP
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|
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|
Patent #:
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|
Issue Dt:
|
08/03/2004
|
Application #:
|
09849214
|
Filing Dt:
|
05/04/2001
|
|
Title:
|
BIT INTERLEAVED DATA SERIAL INTERFACE
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|
|
|
Patent #:
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|
Issue Dt:
|
06/22/2004
|
Application #:
|
09850468
|
Filing Dt:
|
05/07/2001
|
|
Title:
|
USB PERIPHERAL CONTAINING ITS OWN DEVICE DRIVER
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|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09855411
|
Filing Dt:
|
05/15/2001
|
|
Title:
|
CURRENT STEERING REDUCED BITLINE VOLTAGE SWING, SENSE AMPLIFIER
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|
Patent #:
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|
Issue Dt:
|
09/20/2005
|
Application #:
|
09861026
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Filing Dt:
|
05/17/2001
|
|
Title:
|
METHOD FOR INTERFACING A SYNCHRONOUS MEMORY TO AN ASYNCHRONOUS MEMORY INTERFACE AND LOGIC OF SAME
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|
|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
09864458
|
Filing Dt:
|
05/24/2001
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|
Publication #:
|
|
Pub Dt:
|
09/27/2001
| | | | |
|
Title:
|
Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache
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|
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|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09866957
|
Filing Dt:
|
05/29/2001
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|
Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
|
Title:
|
HOT METALLIZATION PROCESS
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|
|
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|
Patent #:
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|
Issue Dt:
|
07/30/2002
|
Application #:
|
09867132
|
Filing Dt:
|
05/29/2001
|
|
Title:
|
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
|
09873927
|
Filing Dt:
|
06/04/2001
|
|
Title:
|
METHODS AND APPARATUS FOR READING A CAM CELL USING BOOSTED AND REGULATED GATE VOLTAGE
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|
|
|
Patent #:
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|
Issue Dt:
|
07/15/2003
|
Application #:
|
09875708
|
Filing Dt:
|
06/05/2001
|
|
Title:
|
METHOD AND AN APPARATUS FOR SYNTHESIZING A PROGRAMMABLE LOGIC CIRCUIT
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|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09877657
|
Filing Dt:
|
06/07/2001
|
|
Title:
|
METASTABILITY RECOVERY CIRCUIT
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|
|
|
Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
|
09877658
|
Filing Dt:
|
06/07/2001
|
|
Title:
|
DISCRIMINATOR CIRCUIT
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|
|
|
Patent #:
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|
Issue Dt:
|
11/30/2004
|
Application #:
|
09877659
|
Filing Dt:
|
06/07/2001
|
|
Title:
|
METHOD AND APPARATUS FOR THE USE OF DISCRIMINATORS FOR PRIORITY ARBITRATION
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|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09877660
|
Filing Dt:
|
06/07/2001
|
|
Title:
|
MULTIPORT ARBITRATION USING PHASED LOCKING ARBITERS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/07/2002
|
Application #:
|
09878433
|
Filing Dt:
|
06/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2002
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FOR WRITING TO AND READING FROM THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09878434
|
Filing Dt:
|
06/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2001
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY HAVING INDEPENDENT READ PORT AND WRITE PORT AND PROCESS FOR WRITING TO AND READING FROM THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09878488
|
Filing Dt:
|
06/11/2001
|
|
Title:
|
SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE BY DOWNLOADING INFORMATION FROM A HOST AND ELECTRONICALLY SIMULATING A PHYSICAL DISCONNECTION AND RECONNECTION TO RECONFIGURE THE DEVICE
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|
Patent #:
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|
Issue Dt:
|
08/20/2002
|
Application #:
|
09879738
|
Filing Dt:
|
06/12/2001
|
|
Title:
|
NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS
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|
Patent #:
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|
Issue Dt:
|
10/22/2002
|
Application #:
|
09881354
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Filing Dt:
|
06/14/2001
|
|
Title:
|
OUTPUT BUFFER CROSSING POINT COMPENSATION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/04/2002
|
Application #:
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09882242
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Filing Dt:
|
06/15/2001
|
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Title:
|
SPECIES IMPLANTATION FOR MINIMIZING INTERFACE DEFECT DENSITY IN FLASH MEMORY DEVICES
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|
Patent #:
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|
Issue Dt:
|
03/18/2003
|
Application #:
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09882898
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Filing Dt:
|
06/15/2001
|
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Title:
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BLOCK REDUNDANCY IN ULTRA LOW POWER MEMORY CIRCUITS
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|
Patent #:
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|
Issue Dt:
|
03/11/2003
|
Application #:
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09884330
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Filing Dt:
|
06/19/2001
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Title:
|
METHOD OF PLACING DIE TO MINIMIZE DIE-TO-DIE ROUTING COMPLEXITY ON A SUBSTRATE
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|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
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09892189
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Filing Dt:
|
06/26/2001
|
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Title:
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MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
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Patent #:
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|
Issue Dt:
|
10/14/2003
|
Application #:
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09892431
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Filing Dt:
|
06/26/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
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Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
|
02/10/2004
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Application #:
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09893161
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Filing Dt:
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06/27/2001
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Title:
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ARCHITECTURE OF A PLL WITH DYNAMIC FREQUENCY CONTROL ON A PLD
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|
Patent #:
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|
Issue Dt:
|
10/22/2002
|
Application #:
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09893247
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Filing Dt:
|
06/26/2001
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Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
|
Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
|
07/16/2002
|
Application #:
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09894172
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Filing Dt:
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06/27/2001
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Title:
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COUNTER LOGIC FOR MULTIPLE MEMORY CONFIGURATION
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Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
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09894220
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Filing Dt:
|
06/27/2001
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Title:
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METHOD TO IMPROVE ROUTABILITY IN PROGRAMMABLE LOGIC DEVICES VIA PRIORITIZED AUGMENTED FLOWS
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Patent #:
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Issue Dt:
|
09/03/2002
|
Application #:
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09895305
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Filing Dt:
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06/30/2001
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Title:
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HIGH SPEED ASYNCHRONOUS AND PROGRAMMABLE STATE MACHINE FOR GENERATING ALMOST EMPTY SYNCHRONOUS FLAGS IN A SYNCHRONOUS FIFO
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Patent #:
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Issue Dt:
|
11/29/2005
|
Application #:
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09895306
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Filing Dt:
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06/29/2001
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Title:
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HIGH SPEED ASYNCHRONOUS AND PROGRAMMABLE STATE MACHINE FOR GENERATING ALMOST FULL SYNCHRONOUS FLAGS IN A SYNCHRONOUS FIFO
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Patent #:
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Issue Dt:
|
03/21/2006
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Application #:
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09899871
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Filing Dt:
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07/06/2001
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Title:
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METHOD AND SYSTEM FOR CLEANING A POLISHING PAD
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Patent #:
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Issue Dt:
|
07/13/2004
|
Application #:
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09902837
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Filing Dt:
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07/10/2001
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Title:
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METHOD AND SYSTEM FOR SPATIAL UNIFORM POLISHING
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Patent #:
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|
Issue Dt:
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08/23/2005
|
Application #:
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09904042
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Filing Dt:
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07/11/2001
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Title:
|
RECESSED TUNNEL OXIDE PROFILE FOR IMPROVED RELIABILITY IN NAND DEVICES
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Patent #:
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|
Issue Dt:
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12/23/2003
|
Application #:
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09904745
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Filing Dt:
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07/13/2001
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Title:
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METHOD FOR TRANSFERRING A PLURALITY OF INTEGRATED CIRCUIT DEVICES INTO AND/OR OUT OF A PLURALITY OF SOCKETS
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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09904750
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Filing Dt:
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07/13/2001
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Title:
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PROGRAMMABLE SERIAL INTERFACE
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|
Patent #:
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|
Issue Dt:
|
03/18/2003
|
Application #:
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09905421
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Filing Dt:
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07/13/2001
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Publication #:
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|
Pub Dt:
|
11/08/2001
| | | | |
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Title:
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MIXED MODE MULTI LEVEL MODE INDICTOR
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Patent #:
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|
Issue Dt:
|
08/05/2003
|
Application #:
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09909109
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Filing Dt:
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07/18/2001
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Title:
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CONFIGURING DIGITAL FUNCTIONS IN A DIGITAL CONFIGURABLE MACRO ARCHITECTURE
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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09912768
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Filing Dt:
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07/24/2001
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Title:
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Dual mode relaxation oscillator generating a clock signal operating at a frequency substantially same in both first and second power modes
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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09912833
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
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02/07/2002
| | | | |
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Title:
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Technique for guaranteeing the availability of per thread storage in a distributed computing environment
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09912834
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
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03/14/2002
| | | | |
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Title:
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MULTIPLE BLOCK SEQUENTIAL MEMORY MANAGEMENT
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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09912856
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Filing Dt:
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07/25/2001
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|
Publication #:
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|
Pub Dt:
|
03/07/2002
| | | | |
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Title:
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High availability shared memory system
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09912870
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
|
02/07/2002
| | | | |
|
Title:
|
RESOURCE LOCKING AND THREAD SYNCHRONIZATION IN A MULTIPROCESSOR ENVIRONMENT
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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09912872
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Filing Dt:
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07/25/2001
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|
Publication #:
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Pub Dt:
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03/14/2002
| | | | |
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Title:
|
Distributed shared memory management
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Patent #:
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|
Issue Dt:
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03/30/2004
|
Application #:
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09912898
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Filing Dt:
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07/25/2001
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|
Publication #:
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|
Pub Dt:
|
02/07/2002
| | | | |
|
Title:
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METHODS AND SYSTEMS FOR A SHARED MEMORY UNIT WITH EXTENDABLE FUNCTIONS
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|
Patent #:
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|
Issue Dt:
|
01/06/2004
|
Application #:
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09912954
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Filing Dt:
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07/25/2001
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|
Publication #:
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|
Pub Dt:
|
02/07/2002
| | | | |
|
Title:
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DEMAND USABLE ADAPTER MEMORY ACCESS MANAGEMENT
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|
|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
09915002
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Filing Dt:
|
07/25/2001
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|
Publication #:
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|
Pub Dt:
|
01/31/2002
| | | | |
|
Title:
|
Shared as needed programming model
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|
Patent #:
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|
Issue Dt:
|
03/18/2003
|
Application #:
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09915018
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Filing Dt:
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07/25/2001
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|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES
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|
Patent #:
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|
Issue Dt:
|
05/10/2005
|
Application #:
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09915109
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Filing Dt:
|
07/25/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/31/2002
| | | | |
|
Title:
|
LOAD/STORE MICROPACKET HANDLING SYSTEM
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|
|
|
Patent #:
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|
Issue Dt:
|
09/13/2005
|
Application #:
|
09915794
|
Filing Dt:
|
07/26/2001
|
|
Title:
|
ARCHITECTURE THAT CONVERTS A HALF-DUPLEX BUS TO A FULL-DUPLEX BUS WHILE KEEPING THE BANDWIDTH OF THE BUS CONSTANT
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|
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|
Patent #:
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|
Issue Dt:
|
03/25/2003
|
Application #:
|
09915823
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Filing Dt:
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07/26/2001
|
|
Title:
|
BUFFER WITH STABLE TRIP POINT
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Patent #:
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|
Issue Dt:
|
05/09/2006
|
Application #:
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09916453
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Filing Dt:
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07/27/2001
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|
Title:
|
TECHNIQUES FOR JEDEC FILE INFORMATION INTEGRITY AND PRESERVATION OF DEVICE PROGRAMMING SPECIFICATIONS
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|
Patent #:
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|
Issue Dt:
|
09/30/2003
|
Application #:
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09916978
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Filing Dt:
|
07/27/2001
|
|
Title:
|
SIGNAL SCALING SCHEME FOR A DELTA SIGMA MODULATOR
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|
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|
Patent #:
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|
Issue Dt:
|
02/25/2003
|
Application #:
|
09917178
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Filing Dt:
|
07/30/2001
|
|
Title:
|
NOR ARRAY WITH BURIED TRENCH SOURCE LINE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
09917440
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Filing Dt:
|
07/27/2001
|
|
Title:
|
N-GATE/N-SUBSTRATE OR P-GATE/P-SUBSTRATE CAPACITOR TO CHARACTERIZE POLYSILICON GATE DEPLETION EVALUATION
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|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09918583
|
Filing Dt:
|
07/31/2001
|
|
Publication #:
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|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
DIGITALLY CONTROLLED ANALOG DELAY LOCKED LOOP (DLL)
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|
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|
Patent #:
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|
Issue Dt:
|
01/18/2005
|
Application #:
|
09920374
|
Filing Dt:
|
07/31/2001
|
|
Title:
|
RETICLE REPEATER MONITOR WAFER AND METHOD FOR VERIFYING RETICLES
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09922419
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Filing Dt:
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08/03/2001
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Title:
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POWER SUPPLY PUMP CIRCUIT FOR A MICROCONTROLLER
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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09922579
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Filing Dt:
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08/03/2001
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Title:
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METHOD FOR EFFICIENT SUPPLY OF POWER TO A MICROCONTROLLER
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09922764
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Filing Dt:
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08/07/2001
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Publication #:
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Pub Dt:
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08/01/2002
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Title:
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CURRENT PULSE RECEIVING CIRCUIT
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09925205
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Filing Dt:
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08/08/2001
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Publication #:
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Pub Dt:
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03/07/2002
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Title:
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METHOD AND SYSTEM FOR ETCHING TUNNEL OXIDE TO REDUCE UNDERCUTTING DURING MEMORY ARRAY FABRICATION
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09927134
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Filing Dt:
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08/10/2001
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Title:
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PROCESS FOR TREATING ONO DIELECTRIC FILM OF A FLOATING GATE MEMORY CELL
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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09927863
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Filing Dt:
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08/10/2001
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Title:
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METHODS OF FORMING SEMICONDUCTOR STRUCTURES HAVING REDUCED DEFECTS, AND ARTICLES AND DEVICES FORMED THEREBY
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09928059
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Filing Dt:
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08/10/2001
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Title:
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DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09928355
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Filing Dt:
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08/14/2001
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Publication #:
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Pub Dt:
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03/07/2002
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Title:
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SYSTEM LSI HAVING COMMUNICATION FUNCTION
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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09928818
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Filing Dt:
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08/13/2001
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Title:
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FAIL-SAFE ZERO DELAY BUFFER WITH AUTOMATIC INTERNAL REFERENCE
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09932159
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Filing Dt:
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08/17/2001
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Title:
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ADJUSTMENT OF THRESHOLD VOLTAGES OF SELECTED NMOS AND PMOS TRANSISTORS USING FEWER MASKING STEPS
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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09933254
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Filing Dt:
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08/20/2001
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Title:
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METHOD FOR CIRCUIT RECOVERY FROM OVERSTRESS CONDITIONS
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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09935017
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Filing Dt:
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08/21/2001
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Title:
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APPARATUS FOR OPTICALLY ISOLATING A USB PERIPHERAL FROM A USB HOST
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09935454
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Filing Dt:
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08/22/2001
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Title:
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METHOD AND APPARATUS FOR LOCAL AND GLOBAL POWER MANAGEMENT IN A PROGRAMMABLE ANALOG CIRCUIT
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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09939076
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Filing Dt:
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08/24/2001
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Title:
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ARCHITECTURE,CIRCUITRY AND METHOD FOR CONTROLLING A SUBSYSTEM THROUGH A JTAG ACCESS PORT
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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09940749
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Filing Dt:
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08/28/2001
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Title:
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METHOD AND APPARATUS FOR GENERATING SUPERSET PINOUT FOR DEVICES WITH HIGH-SPEED TRANSCEIVER CHANNELS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09943149
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Filing Dt:
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08/30/2001
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Title:
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METHOD FOR PHASE LOCKING IN A PHASE LOCK LOOP
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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09943947
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Filing Dt:
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08/31/2001
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Title:
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CONFIGURABLE MATRIX ARCHITECTURE
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09944234
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Filing Dt:
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08/31/2001
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Title:
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CMP PROCESS
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09944874
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Filing Dt:
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08/31/2001
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Title:
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APPARATUS AND METHOD FOR COUPLING WITH COMPONENTS IN A SURFACE MOUNT PACKAGE
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09951369
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Filing Dt:
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09/13/2001
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Title:
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PROGRAMMABLE LATCH THAT AVOIDS A NON-DESIRED OUTPUT STATE
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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09951684
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Filing Dt:
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09/11/2001
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Title:
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HIGH PERFORMANCE CARRY CHAIN WITH REDUCED MACROCELL LOGIC AND FAST CARRY LOOKAHEAD
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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09954382
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Filing Dt:
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09/12/2001
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Title:
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METHODS OF FILLING CONSTRAINED SPACES WITH INSULATING MATERIALS AND/OR OF FORMING CONTACT HOLES AND/OR CONTACTS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09955865
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Filing Dt:
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09/19/2001
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Title:
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METHOD FOR CHARGE PUMP TRI-STATE AND POWER DOWN/UP SEQUENCE WITHOUT DISTURBING THE OUTPUT FILTER
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09957015
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Filing Dt:
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09/20/2001
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Title:
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HIGH SPEED FIFO SYNCHRONOUS PROGRAMMABLE FULL AND EMPTY FLAG GENERATION
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09957084
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Filing Dt:
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09/19/2001
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Title:
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CRYSTAL-LESS OSCILLATOR CIRCUIT WITH TRIMMABLE ANALOG CURRENT CONTROL FOR INCREASED STABILITY
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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09957587
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Filing Dt:
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09/20/2001
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Title:
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HIGH SPEED FIFO SYNCHRONOUS PROGRAMMABLE FULL AND EMPTY FLAG GENERATION
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09964716
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Filing Dt:
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09/26/2001
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Title:
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METHODS FOR PRODUCING HIGH RELIABILITY LEAD FRAME AND PACKAGING SEMICONDUCTOR DIE USING SUCH LEAD FRAME
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09964991
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Filing Dt:
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09/26/2001
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Title:
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BAND-GAP REFERENCE CIRCUIT FOR PROVIDING AN ACCURATE REFERENCE VOLTAGE COMPENSATED FOR PROCESS STATE, PROCESS VARIATIONS AND TEMPERATURE
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09965214
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Filing Dt:
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09/26/2001
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Title:
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METHODS FOR PLASTIC INJECTION MOLDING, WITH PARTICULAR APPLICABILITY IN FACILITATING USE OF HIGH DENSITY LEAD FRAMES
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09966626
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Filing Dt:
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09/28/2001
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Title:
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CIRCUIT FOR LOCKING AN OSCILLATOR TO A DATA STREAM
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09966979
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Filing Dt:
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09/28/2001
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Title:
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FLEXIBLE CONVERTER
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09967260
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Filing Dt:
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09/28/2001
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Title:
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FLEXIBLE CONVERTER ROUTING APPARATUS, SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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01/08/2008
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Application #:
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09968519
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Filing Dt:
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10/02/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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METHOD OF CONSTRUCTING NETWORK TOPOLOGY AND INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09969573
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Filing Dt:
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10/01/2001
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Title:
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FORMATION OF STI (SHALLOW TRENCH ISOLATION) STRUCTURES WITHIN CORE AND PERIPHERY AREAS OF FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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09972133
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Filing Dt:
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10/05/2001
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Title:
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METHOD FOR ENTERING CIRCUIT TEST MODE
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09972152
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Filing Dt:
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10/09/2001
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH VARIABLE GAIN AMPLIFIER
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