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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:039708/0001   Pages: 123
Recorded: 08/11/2016
Attorney Dkt #:3483.000
Conveyance: PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS
Total properties: 2101
Page 11 of 22
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
Patent #:
Issue Dt:
12/16/2003
Application #:
09973131
Filing Dt:
10/09/2001
Title:
NON SELF-ALIGNED SHALLOW TRENCH ISOLATION PROCESS WITH DISPOSABLE SPACE TO DEFINE SUB-LITHOGRAPHIC POLY SPACE
2
Patent #:
Issue Dt:
08/02/2005
Application #:
09973260
Filing Dt:
10/09/2001
Title:
METHOD OF PROGRAMMING USB MICROCONTROLLERS
3
Patent #:
Issue Dt:
08/26/2003
Application #:
09973535
Filing Dt:
10/09/2001
Title:
ARCHITECTURE FOR DECIMATION ALGORITHM
4
Patent #:
Issue Dt:
03/06/2007
Application #:
09975104
Filing Dt:
10/10/2001
Title:
CAPTURING TEST/EMULATION AND ENABLING REAL-TIME DEBUGGING USING AN FPGA FOR IN-CIRCUIT EMULATION
5
Patent #:
Issue Dt:
10/12/2004
Application #:
09975256
Filing Dt:
10/12/2001
Publication #:
Pub Dt:
04/17/2003
Title:
METHOD FOR GROWING ULTRA THIN NITRIDED OXIDE
6
Patent #:
Issue Dt:
02/20/2007
Application #:
09977111
Filing Dt:
10/11/2001
Title:
FREQUENCY DOUBLER CIRCUIT WITH TRIMMABLE CURRENT CONTROL
7
Patent #:
Issue Dt:
05/20/2003
Application #:
09981079
Filing Dt:
10/16/2001
Title:
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP WITH FEEDBACK
8
Patent #:
Issue Dt:
07/27/2004
Application #:
09987628
Filing Dt:
11/15/2001
Title:
HIGH-SPEED DIFFERENTIAL PREAMPLIFIER
9
Patent #:
Issue Dt:
11/15/2005
Application #:
09989570
Filing Dt:
11/19/2001
Title:
METHOD FOR FACILITATING MICROCONTROLLER PROGRAMMING
10
Patent #:
Issue Dt:
03/02/2004
Application #:
09989574
Filing Dt:
11/19/2001
Title:
METHOD AND SYSTEM FOR USING A GRAPHICS USER INTERFACE FOR PROGRAMMING AN ELECTRONIC DEVICE
11
Patent #:
Issue Dt:
11/29/2011
Application #:
09989765
Filing Dt:
11/19/2001
Title:
USER INTERFACE FOR EFFICIENTLY BROWSING AN ELECTRONIC DOCUMENT USING DATA-DRIVEN TABS
12
Patent #:
Issue Dt:
08/10/2010
Application #:
09989777
Filing Dt:
11/19/2001
Title:
SLEEP AND STALL IN AN IN-CIRCUIT EMULATION SYSTEM
13
Patent #:
Issue Dt:
10/21/2003
Application #:
09989781
Filing Dt:
11/19/2001
Title:
SYSTEM AND METHOD FOR DECOUPLING AND ITERATING RESOURCES ASSOCIATED WITH A MODULE
14
Patent #:
Issue Dt:
04/28/2009
Application #:
09992076
Filing Dt:
11/13/2001
Title:
SYSTEM AND A METHOD FOR CHECKING LOCK-STEP CONSISTENCY BETWEEN AN IN CIRCUIT EMULATION AND A MICROCONTROLLER
15
Patent #:
Issue Dt:
11/04/2003
Application #:
09992651
Filing Dt:
11/16/2001
Title:
METHOD OF LOCALIZED PLACEMENT MANIPULATION WITH EXTRA LATENCY
16
Patent #:
Issue Dt:
05/09/2006
Application #:
09992652
Filing Dt:
11/16/2001
Title:
METHODOLOGY FOR JEDEC FILE REPAIR THROUGH COMPRESSION FIELD TECHNIQUES
17
Patent #:
Issue Dt:
05/04/2004
Application #:
09997357
Filing Dt:
11/30/2001
Title:
METHOD AND/OR ARCHITECTURE FOR SWITCHING A PRECISION CURRENT
18
Patent #:
Issue Dt:
11/25/2003
Application #:
09998675
Filing Dt:
11/30/2001
Title:
BUS I/O PLACEMENT GUIDANCE
19
Patent #:
Issue Dt:
10/18/2005
Application #:
09998834
Filing Dt:
11/15/2001
Title:
SYSTEM AND A METHOD FOR COMMUNICATION BETWEEN AN ICE AND A PRODUCTION MICROCONTROLLER WHILE IN A HALT STATE
20
Patent #:
Issue Dt:
07/26/2005
Application #:
09998859
Filing Dt:
11/15/2001
Title:
SYSTEM AND A METHOD FOR CHECKING LOCK STEP CONSISTENCY BETWEEN AN IN CIRCUIT EMULATION AND A MICROCONTROLLER WHILE DEBUGGING PROCESS IS IN PROGRESS
21
Patent #:
Issue Dt:
05/06/2003
Application #:
09999743
Filing Dt:
10/31/2001
Title:
MULTI-MODULUS COUNTER IN MODULATED FREQUENCY SYNTHESIS
22
Patent #:
Issue Dt:
09/02/2003
Application #:
10000383
Filing Dt:
10/24/2001
Title:
SYSTEM AND METHOD OF PROVIDING A PROGRAMMABLE CLOCK ARCHITECTURE FOR AN ADVANCED MICROCONTROLLER
23
Patent #:
Issue Dt:
04/19/2005
Application #:
10001458
Filing Dt:
11/13/2001
Title:
PULSE WIDTH POSITION MODULATOR AND CLOCK SKEW SYNCHRONIZER
24
Patent #:
Issue Dt:
01/24/2012
Application #:
10001477
Filing Dt:
11/01/2001
Title:
BREAKPOINT CONTROL IN AN IN-CIRCUIT EMULATION SYSTEM
25
Patent #:
Issue Dt:
04/17/2012
Application #:
10001478
Filing Dt:
11/01/2001
Title:
IN-CIRCUIT EMULATOR AND POD SYNCHRONIZED BOOT
26
Patent #:
Issue Dt:
07/27/2010
Application #:
10002217
Filing Dt:
11/01/2001
Title:
CONDITIONAL BRANCHING IN AN IN-CIRCUIT EMULATION SYSTEM
27
Patent #:
NONE
Issue Dt:
Application #:
10003618
Filing Dt:
11/14/2001
Publication #:
Pub Dt:
05/16/2002
Title:
Automatic documentation generation tool and associated method
28
Patent #:
Issue Dt:
01/09/2007
Application #:
10004039
Filing Dt:
11/14/2001
Title:
IN-CIRCUIT EMULATOR WITH GATEKEEPER FOR WATCHDOG TIMER
29
Patent #:
Issue Dt:
12/30/2003
Application #:
10005823
Filing Dt:
12/03/2001
Title:
METHOD OF CREATING MCM PINOUTS
30
Patent #:
Issue Dt:
12/13/2011
Application #:
10008096
Filing Dt:
11/09/2001
Title:
GRAPHICAL USER INTERFACE WITH USER-SELECTABLE LIST-BOX
31
Patent #:
Issue Dt:
02/22/2005
Application #:
10010280
Filing Dt:
12/05/2001
Title:
OXIDIZING PRETREATMENT OF ONO LAYER FOR FLASH MEMORY
32
Patent #:
Issue Dt:
07/18/2006
Application #:
10010591
Filing Dt:
11/09/2001
Title:
MULTI-LEVEL QUICK CLICK ICON HIERARCHY AND/OR ACTIVATION
33
Patent #:
Issue Dt:
02/25/2003
Application #:
10010985
Filing Dt:
12/05/2001
Title:
METHOD AND APPARATUS FOR ADJUSTING ON-CHIP CURRENT REFERENCE FOR EEPROM SENSING
34
Patent #:
Issue Dt:
11/11/2003
Application #:
10011936
Filing Dt:
12/05/2001
Title:
INTERFACE SCHEME FOR CONNECTING A FIXED CIRCUITRY BLOCK TO A PROGRAMMABLE LOGIC CORE
35
Patent #:
Issue Dt:
03/02/2004
Application #:
10013902
Filing Dt:
12/11/2001
Title:
REDUCTION OF SECTOR CONNECTING LINE CAPACITANCE USING STAGGERED METAL LINES
36
Patent #:
Issue Dt:
11/25/2003
Application #:
10013993
Filing Dt:
12/11/2001
Title:
FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING AND READING THEREOF
37
Patent #:
Issue Dt:
02/21/2006
Application #:
10015033
Filing Dt:
12/11/2001
Title:
SWITCHED-CAPACITOR CONTROLLER TO CONTROL THE RISE TIMES OF ON-CHIP GENERATED HIGH VOLTAGES
38
Patent #:
Issue Dt:
12/16/2003
Application #:
10023065
Filing Dt:
12/17/2001
Title:
METHOD AND STRUCTURE FOR DETERMINING A CONCENTRATION PROFILE OF AN IMPURITY WITHIN A SEMICONDUCTOR LAYER
39
Patent #:
Issue Dt:
01/28/2003
Application #:
10024093
Filing Dt:
12/18/2001
Title:
CONFIGURABLE MEMORY FOR PROGRAMMABLE LOGIC CIRCUITS
40
Patent #:
Issue Dt:
03/08/2005
Application #:
10025511
Filing Dt:
12/19/2001
Title:
METHODS FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY
41
Patent #:
Issue Dt:
10/28/2003
Application #:
10027253
Filing Dt:
12/20/2001
Title:
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
42
Patent #:
Issue Dt:
02/07/2006
Application #:
10028029
Filing Dt:
12/21/2001
Title:
EFFICIENT PEER-TO-PEER DMA
43
Patent #:
Issue Dt:
03/14/2006
Application #:
10029530
Filing Dt:
12/20/2001
Title:
CIRCUIT AND METHOD FOR DISCHARGING HIGH VOLTAGE SIGNALS
44
Patent #:
Issue Dt:
12/30/2003
Application #:
10030117
Filing Dt:
01/23/2002
Title:
MULTIPLE-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE CHARGE TRAPPING GATE
45
Patent #:
Issue Dt:
12/13/2005
Application #:
10032757
Filing Dt:
12/27/2001
Title:
METHOD AND SYSTEM FOR FORMING DUAL GATE STRUCTURES IN A NONVOLATILE MEMORY USING A PROTECTIVE LAYER
46
Patent #:
Issue Dt:
10/14/2003
Application #:
10037247
Filing Dt:
10/23/2001
Title:
CIRCUIT TO PROVIDE A TIME DELAY
47
Patent #:
Issue Dt:
01/27/2004
Application #:
10042783
Filing Dt:
01/09/2002
Title:
ASYNCHRONOUS RANDOM ACCESS MEMORY WITH POWER OPTIMIZING CLOCK
48
Patent #:
Issue Dt:
09/05/2006
Application #:
10054329
Filing Dt:
01/22/2002
Title:
METHOD AND/OR APPARATUS FOR IMPLEMENTING USB AND AUDIO SIGNALS SHARED CONDUCTORS
49
Patent #:
Issue Dt:
02/08/2005
Application #:
10056242
Filing Dt:
01/23/2002
Title:
NON-STICK DETECTION METHOD AND MECHANISM FOR ARRAY MOLDED LAMINATE PACKAGES
50
Patent #:
Issue Dt:
02/06/2007
Application #:
10057196
Filing Dt:
01/24/2002
Title:
CLOCKING SYSTEM AND METHOD FOR A MEMORY
51
Patent #:
Issue Dt:
09/13/2005
Application #:
10057867
Filing Dt:
01/29/2002
Publication #:
Pub Dt:
12/26/2002
Title:
MICROCONTROLLER WITH DEBUG SUPPORT UNIT
52
Patent #:
NONE
Issue Dt:
Application #:
10059119
Filing Dt:
01/31/2002
Publication #:
Pub Dt:
09/26/2002
Title:
Tungsten gate MOS transistor and memory cell and method of making same
53
Patent #:
Issue Dt:
12/28/2004
Application #:
10059823
Filing Dt:
01/29/2002
Title:
METHOD OF FORMING A FLOATING METAL STRUCTURE IN AN INTEGRATED CIRCUIT
54
Patent #:
Issue Dt:
08/26/2003
Application #:
10061620
Filing Dt:
02/01/2002
Publication #:
Pub Dt:
06/13/2002
Title:
POWER-SAVING MODES FOR MEMORIES
55
Patent #:
Issue Dt:
12/26/2006
Application #:
10061906
Filing Dt:
02/01/2002
Title:
EXTRACTING COMMENT KEYWORDS FROM DISTINCT DESIGN FILES TO PRODUCE DOCUMENTATION.
56
Patent #:
Issue Dt:
02/14/2006
Application #:
10073434
Filing Dt:
02/11/2002
Title:
METHOD AND APPARATUS FOR ADDING OTG DUAL ROLE DEVICE CAPABILITY TO A USB PERIPHERAL
57
Patent #:
Issue Dt:
11/25/2003
Application #:
10073490
Filing Dt:
02/13/2002
Publication #:
Pub Dt:
01/09/2003
Title:
METHOD OF AND CIRCUIT FOR CONTROLLING A CLOCK
58
Patent #:
Issue Dt:
12/28/2004
Application #:
10074495
Filing Dt:
02/11/2002
Title:
PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
59
Patent #:
Issue Dt:
10/31/2006
Application #:
10074888
Filing Dt:
02/13/2002
Title:
REDUCING DEFECT FORMATION WITHIN AN ETCHED SEMICONDUCTOR TOPOGRAPHY
60
Patent #:
Issue Dt:
01/20/2004
Application #:
10083442
Filing Dt:
02/26/2002
Title:
METHOD/ARCHITECTURE FOR A LOW GAIN PLL WITH WIDE FREQUENCY RANGE
61
Patent #:
Issue Dt:
05/04/2004
Application #:
10085716
Filing Dt:
02/27/2002
Title:
METHOD OF PERFORMING BACK-END MANUFACTURING OF AN INTEGRATED CIRCUIT DEVICE
62
Patent #:
Issue Dt:
06/07/2005
Application #:
10085752
Filing Dt:
02/27/2002
Title:
METHOD AND SYSTEM FOR CONTROLLING THE PROCESSING OF AN INTEGRATED CIRCUIT CHIP ASSEMBLY LINE USING A CENTRAL COMPUTER SYSTEM AND A COMMON COMMUNICATION PROTOCOL
63
Patent #:
Issue Dt:
08/16/2005
Application #:
10085757
Filing Dt:
02/27/2002
Title:
INTEGRATED BACK-END INTEGRATED CIRCUIT MANUFACTURING ASSEMBLY
64
Patent #:
Issue Dt:
04/18/2006
Application #:
10086051
Filing Dt:
02/27/2002
Title:
METHOD AND SYSTEM FOR A REJECT MANAGEMENT PROTOCOL WITHIN A BACK-END INTEGRATED CIRCUIT MANUFACTURING PROCESS
65
Patent #:
Issue Dt:
03/16/2004
Application #:
10096741
Filing Dt:
03/14/2002
Title:
LASER THERMAL ANNEALING OF SILICON NITRIDE FOR INCREASED DENSITY AND ETCH SELECTIVITY
66
Patent #:
Issue Dt:
08/22/2006
Application #:
10097499
Filing Dt:
03/15/2002
Publication #:
Pub Dt:
02/27/2003
Title:
MEMORY CONTROLLER FOR MULTILEVEL CELL MEMORY
67
Patent #:
Issue Dt:
03/02/2004
Application #:
10099841
Filing Dt:
03/15/2002
Title:
GATE ETCH PROCESS
68
Patent #:
Issue Dt:
12/30/2003
Application #:
10103557
Filing Dt:
03/22/2002
Publication #:
Pub Dt:
03/20/2003
Title:
ULTRAVIOLET-LIGHT IRRADIATION APPARATUS
69
Patent #:
Issue Dt:
01/21/2003
Application #:
10103721
Filing Dt:
03/25/2002
Title:
SEMICONDUCTOR MEMORY DEVICE
70
Patent #:
Issue Dt:
11/28/2006
Application #:
10107687
Filing Dt:
03/27/2002
Title:
METHOD AND APPARATUS FOR RECOVERY FROM POWER SUPPLY TRANSIENT STRESS CONDITIONS
71
Patent #:
Issue Dt:
04/25/2006
Application #:
10109743
Filing Dt:
03/28/2002
Title:
RE-CONFIGURABLE COMBINATIONAL LOGIC DEVICE
72
Patent #:
Issue Dt:
12/12/2006
Application #:
10109979
Filing Dt:
03/29/2002
Title:
GRAPHICAL USER INTERFACE WITH LOGIC UNIFYING FUNCTIONS
73
Patent #:
Issue Dt:
10/05/2004
Application #:
10112013
Filing Dt:
03/29/2002
Title:
APPARATUS AND METHOD FOR COLOR DATA INTERPOLATION
74
Patent #:
Issue Dt:
06/22/2004
Application #:
10112383
Filing Dt:
03/29/2002
Title:
APPARATUS AND METHOD FOR COLOR DATA CONVERSION
75
Patent #:
Issue Dt:
12/07/2004
Application #:
10112833
Filing Dt:
03/29/2002
Title:
SEMICONDUCTOR TOPOGRAPHY WITH A FILL MATERIAL ARANGED WITHIN A PLURALITY OF VALLEYS ASSOCIATED WITH THE SURFACE ROUGHNESS OF THE METAL LAYER
76
Patent #:
Issue Dt:
06/29/2004
Application #:
10113017
Filing Dt:
03/28/2002
Title:
METHOD OF DETERMINING LOCATION OF GATE OXIDE BREAKDOWN OF MOSFET BY MEASURING CURRENTS
77
Patent #:
Issue Dt:
02/27/2007
Application #:
10113064
Filing Dt:
03/29/2002
Title:
METHOD AND SYSTEM FOR DEBUGGING THROUGH SUPERVISORY OPERATING CODES AND SELF MODIFYING CODES
78
Patent #:
Issue Dt:
08/29/2006
Application #:
10113065
Filing Dt:
03/29/2002
Title:
SYSTEM AND METHOD FOR AUTOMATICALLY MATCHING COMPONENTS IN A DEBUGGING SYSTEM
79
Patent #:
Issue Dt:
05/25/2004
Application #:
10113309
Filing Dt:
03/29/2002
Title:
SMOOTH METAL SEMICONDUCTOR SURFACE AND METHOD FOR MAKING THE SAME
80
Patent #:
Issue Dt:
11/25/2003
Application #:
10113580
Filing Dt:
03/28/2002
Title:
PROGRAMMABLE EVENT ENGINE
81
Patent #:
Issue Dt:
01/24/2012
Application #:
10113581
Filing Dt:
03/28/2002
Title:
EXTERNAL INTERFACE FOR EVENT ARCHITECTURE
82
Patent #:
Issue Dt:
05/11/2004
Application #:
10117428
Filing Dt:
04/05/2002
Title:
METHOD OF PROVIDING HBM PROTECTION WITH A DECOUPLED HBM STRUCTURE
83
Patent #:
Issue Dt:
07/13/2004
Application #:
10118363
Filing Dt:
04/08/2002
Title:
STACKED POLYSILICON LAYER FOR BORON PENETRATION INHIBITION
84
Patent #:
Issue Dt:
12/06/2005
Application #:
10122737
Filing Dt:
04/15/2002
Title:
METAL ETCH PROCESS SELECTIVE TO METALLIC INSULATING MATERIALS
85
Patent #:
Issue Dt:
11/23/2004
Application #:
10126193
Filing Dt:
04/19/2002
Title:
METHOD OF DETECTING AND DISTINGUISHING STACK GATE EDGE DEFECTS AT THE SOURCE OR DRAIN JUNCTION
86
Patent #:
Issue Dt:
05/27/2003
Application #:
10126330
Filing Dt:
04/19/2002
Title:
PROGRAMMING WITH FLOATING SOURCE FOR LOW POWER, LOW LEAKAGE AND HIGH DENSITY FLASH MEMORY DEVICES
87
Patent #:
Issue Dt:
11/30/2004
Application #:
10126814
Filing Dt:
04/19/2002
Title:
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
88
Patent #:
Issue Dt:
07/20/2004
Application #:
10126840
Filing Dt:
04/19/2002
Title:
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON TUNNEL OXIDES USING PARTIAL NITRIDE STRIP AND SMALL BIRD'S BEAK FORMATION FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
89
Patent #:
Issue Dt:
12/02/2003
Application #:
10132857
Filing Dt:
04/25/2002
Title:
CIRCUIT, SYSTEM, AND METHOD FOR PROGRAMMABLY SETTING AN INPUT TO A PRIORITIZER OF A LATCH TO AVOID A NON-DESIRED OUTPUT STATE OF THE LATCH
90
Patent #:
Issue Dt:
12/11/2007
Application #:
10137497
Filing Dt:
05/01/2002
Title:
RECONFIGURABLE TESTING SYSTEM AND METHOD
91
Patent #:
Issue Dt:
09/30/2003
Application #:
10139331
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/07/2002
Title:
FLOATING GATE MEMORY DEVICE USING COMPOSITE MOLECULAR MATERIAL
92
Patent #:
Issue Dt:
01/18/2005
Application #:
10139381
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/07/2002
Title:
REVERSIBLE FIELD-PROGRAMMABLE ELECTRIC INTERCONNECTS
93
Patent #:
Issue Dt:
10/26/2004
Application #:
10139746
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/07/2002
Title:
ADDRESABLE AND ELECTRICALLY REVERSIBLE MEMORY SWITCH
94
Patent #:
Issue Dt:
08/24/2004
Application #:
10139747
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/07/2002
Title:
MOLECULAR MEMORY DEVICE
95
Patent #:
Issue Dt:
03/29/2005
Application #:
10139748
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/07/2002
Title:
MOLECULAR MEMORY CELL
96
Patent #:
Issue Dt:
08/22/2006
Application #:
10142963
Filing Dt:
05/13/2002
Title:
METHOD OF FORMING NITRIDED OXIDE IN A HOT WALL SINGLE WAFER FURNACE
97
Patent #:
Issue Dt:
01/25/2005
Application #:
10144676
Filing Dt:
05/13/2002
Title:
PROBE CARD WITH AN ADAPTER LAYER FOR TESTING INTEGRATED CIRCUITS
98
Patent #:
Issue Dt:
01/24/2006
Application #:
10146074
Filing Dt:
05/16/2002
Publication #:
Pub Dt:
03/27/2003
Title:
METHOD FOR ERROR DETECTION/CORRECTION OF MULTILEVEL CELL MEMORY AND MULTILEVEL CELL MEMORY HAVING ERROR DETECTION/CORRECTION FUNCTION
99
Patent #:
Issue Dt:
08/23/2005
Application #:
10146524
Filing Dt:
05/15/2002
Title:
AMPLIFIER CIRCUIT AND METHOD
100
Patent #:
Issue Dt:
07/05/2005
Application #:
10147827
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
11/21/2002
Title:
BALL GRID ARRAY ANTENNA
Assignor
1
Exec Dt:
08/11/2016
Assignees
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
2
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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