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Patent #:
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|
Issue Dt:
|
01/05/1999
|
Application #:
|
08831571
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Filing Dt:
|
04/09/1997
|
|
Title:
|
MEMORY CELL PROGRAMMING WITH CONTROLLED CURRENT INJECTION
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Patent #:
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|
Issue Dt:
|
10/27/1998
|
Application #:
|
08834942
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Filing Dt:
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04/07/1997
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Title:
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MEMORY CELL SENSING METHOD AND CIRCUITRY FOR BIT LINE EQUALIZATION
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Patent #:
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|
Issue Dt:
|
03/30/1999
|
Application #:
|
08837556
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Filing Dt:
|
04/21/1997
|
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Title:
|
MULTILAYER FLOATING GATE FIELD EFFECT TRANSISTOR STRUCTURE FOR USE IN INTEGRATED CIRCUIT DEVICES
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Patent #:
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|
Issue Dt:
|
06/29/1999
|
Application #:
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08837782
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Filing Dt:
|
04/22/1997
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Title:
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OUTPUT VOLTAGE CONTROLLED IMPEDANCE OUTPUT BUFFER
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Patent #:
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|
Issue Dt:
|
06/06/2000
|
Application #:
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08839981
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Filing Dt:
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04/24/1997
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Title:
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FAIL SAFE METHOD AND APPARATUS FOR A USB DEVICE
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Patent #:
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|
Issue Dt:
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10/20/1998
|
Application #:
|
08845302
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Filing Dt:
|
04/25/1997
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|
Title:
|
FAST TURN-ON SILICON CONTROLLED RECTIFIER (SCR) FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
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Patent #:
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|
Issue Dt:
|
04/06/1999
|
Application #:
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08846558
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Filing Dt:
|
04/29/1997
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Title:
|
SEMICONDUCTOR NON-VOLATILE LATCH DEVICE INCLUDING EMBEDDED NON-VOLATILE ELEMENTS
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|
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Patent #:
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|
Issue Dt:
|
09/14/1999
|
Application #:
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08850511
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Filing Dt:
|
05/02/1997
|
|
Title:
|
ESD PROTECTION CIRCUIT FOR I/O BUFFERS
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Patent #:
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|
Issue Dt:
|
12/22/1998
|
Application #:
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08852695
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Filing Dt:
|
05/07/1997
|
|
Title:
|
FABRICATION SEQUENCE EMPLOYING AN OXIDE FORMED WITH MINIMIZED INDUCTED CHARGE AND/OR MAXIMIZED BREAKDOWN VOLTAGE
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Patent #:
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|
Issue Dt:
|
08/04/1998
|
Application #:
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08853185
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Filing Dt:
|
05/09/1997
|
|
Title:
|
MULTIPLE BITS- PER- CELL FLASH EEPROM MEMORY CELLS WITH WIDE PROGRAM AND ERASE VT WINDOW
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Patent #:
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|
Issue Dt:
|
05/11/1999
|
Application #:
|
08853527
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Filing Dt:
|
05/09/1997
|
|
Title:
|
DUAL-LEVEL METALIZATION METHOD FOR INTEGRATED CIRCUIT FERROELECTRIC DEVICES
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|
Patent #:
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|
Issue Dt:
|
10/20/1998
|
Application #:
|
08855040
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Filing Dt:
|
05/13/1997
|
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Title:
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METHOD AND APPARATUS FOR PREVENTING WRITE OPERATIONS IN A MEMORY DEVICE
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|
Patent #:
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|
Issue Dt:
|
12/19/2000
|
Application #:
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08857269
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Filing Dt:
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05/16/1997
|
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Title:
|
LEVEL CONVERTER AND SEMICONDUCTOR DEVICE
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|
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|
Patent #:
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|
Issue Dt:
|
08/18/1998
|
Application #:
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08858589
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Filing Dt:
|
05/19/1997
|
|
Title:
|
MEMORY DEVICE USING A REDUCED WORD LINE VOLTAGE DURING READ OPERATIONS AND A METHOD OF ACCESSING SUCH A MEMORY DEVICE
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Patent #:
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|
Issue Dt:
|
08/29/2000
|
Application #:
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08865667
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Filing Dt:
|
05/30/1997
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Title:
|
CIRCUIT, STRUCTURE AND METHOD OF TESTING A SEMICONDUCTOR, SUCH AS AN INTEGRATED CIRCUIT
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|
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Patent #:
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|
Issue Dt:
|
07/13/1999
|
Application #:
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08868062
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Filing Dt:
|
06/03/1997
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Title:
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SRAM WITH ROM FUNCTIONALITY
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Patent #:
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|
Issue Dt:
|
04/03/2001
|
Application #:
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08868079
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Filing Dt:
|
06/03/1997
|
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Title:
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MICROPROCESSOR CONTROLLED FREQUENCY LOCK LOOP FOR USE WITH AN EXTERNAL PERIODIC SIGNAL
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Patent #:
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|
Issue Dt:
|
11/09/1999
|
Application #:
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08870045
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Filing Dt:
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06/05/1997
|
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Title:
|
TUBE FOR FLASH MINIATURE CARD
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Patent #:
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|
Issue Dt:
|
08/03/1999
|
Application #:
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08871428
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Filing Dt:
|
06/09/1997
|
|
Title:
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MONITORING CLEANING EFFECTIVENESS OF A CLEANING SYSTEM
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Patent #:
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|
Issue Dt:
|
12/08/1998
|
Application #:
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08874006
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Filing Dt:
|
06/12/1997
|
|
Title:
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SEMICONDUCTOR DEVICE SUCH AS A STATIC RANDOM ACCESS MEMORY (SRAM) HAVING A LOW POWER MODE USING A CLOCK DISABLE CIRCUIT
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Patent #:
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|
Issue Dt:
|
06/08/1999
|
Application #:
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08877683
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Filing Dt:
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06/16/1997
|
|
Title:
|
CIRCUIT AND METHOD FOR DATA RECOVERY
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Patent #:
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|
Issue Dt:
|
09/07/1999
|
Application #:
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08878119
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Filing Dt:
|
06/18/1997
|
|
Title:
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METHOD OF FABRICATING AN EPROM TYPE DEVICE WITH REDUCED PROCESS RESIDUES
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Patent #:
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|
Issue Dt:
|
04/29/2003
|
Application #:
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08878728
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Filing Dt:
|
06/19/1997
|
|
Title:
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METHOD FOR CONTROLLING THE OXIDATION OF IMPLANTED SILICON
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Patent #:
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|
Issue Dt:
|
12/22/1998
|
Application #:
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08878904
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Filing Dt:
|
06/19/1997
|
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Title:
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A METHOD AND CIRCUIT FOR PREVENTING AND/OR INHIBITING CONTENTION IN A SYSTEM EMPLOYING A RANDOM ACCESS MEMORY
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Patent #:
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|
Issue Dt:
|
07/20/1999
|
Application #:
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08879287
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Filing Dt:
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06/19/1997
|
|
Title:
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PHASE DETECTOR WITH LINEAR OUTPUT RESPONSE
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|
Patent #:
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|
Issue Dt:
|
12/21/1999
|
Application #:
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08881487
|
Filing Dt:
|
06/24/1997
|
|
Title:
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METHOD AND SOFTWARE FOR OPTIMIZING AN INTERFACE BETWEEN COMPONENTS
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Patent #:
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|
Issue Dt:
|
05/11/1999
|
Application #:
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08883971
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Filing Dt:
|
06/27/1997
|
|
Title:
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LOW DISTORTION LEVEL SHIFTER
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|
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|
Patent #:
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|
Issue Dt:
|
05/19/1998
|
Application #:
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08884547
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Filing Dt:
|
06/27/1997
|
|
Title:
|
A BIT LINE DISCHARGE METHOD FOR READING A MULTIPLE BITS-PER-CELL FLASH EEPROM
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|
|
|
Patent #:
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|
Issue Dt:
|
03/09/1999
|
Application #:
|
08884561
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
READ ONLY/ RANDOM ACCESS MEMORY ARCHITECTURE AND METHODS FOR OPERATING SAME
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|
Patent #:
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|
Issue Dt:
|
01/18/2000
|
Application #:
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08884581
|
Filing Dt:
|
06/27/1997
|
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Title:
|
REFERENCE VOLTAGE GENERATOR FOR READING A ROM CELL IN AN INTEGRATED RAM/ROM MEMORY DEVICE
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|
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Patent #:
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|
Issue Dt:
|
08/07/2001
|
Application #:
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08885140
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Filing Dt:
|
06/30/1997
|
|
Title:
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METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
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Patent #:
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|
Issue Dt:
|
11/16/1999
|
Application #:
|
08885156
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
NON-VOLATILE STATIC RANDOM ACCESS MEMORY AND METHODS FOR USING SAME
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|
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|
Patent #:
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|
Issue Dt:
|
01/04/2000
|
Application #:
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08886923
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Filing Dt:
|
07/02/1997
|
|
Title:
|
SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE WHERE CONFIGURATION INFORMATION IS DOWNLOADED FROM THE HOST AND A CIRCUIT SIMULATES DISCONNECTION AND RECONNECTION OF THE PERIPHERAL DEVICE
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Patent #:
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|
Issue Dt:
|
10/05/1999
|
Application #:
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08891422
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Filing Dt:
|
07/09/1997
|
|
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE
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|
Patent #:
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|
Issue Dt:
|
06/27/2000
|
Application #:
|
08896684
|
Filing Dt:
|
07/18/1997
|
|
Title:
|
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
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|
|
|
Patent #:
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|
Issue Dt:
|
06/29/1999
|
Application #:
|
08899565
|
Filing Dt:
|
07/24/1997
|
|
Title:
|
VOLTAGE BOOSTER CIRCUIT AND A VOLTAGE DROP CIRCUIT WITH CHANGEABLE OPERATING LEVELS
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|
|
|
Patent #:
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|
Issue Dt:
|
10/06/1998
|
Application #:
|
08899762
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Filing Dt:
|
07/24/1997
|
|
Title:
|
FRACTIONAL N- FREQUENCY SYNTHESIZER AND SPURIOUS SIGNAL CANCEL CIRCUIT
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|
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|
Patent #:
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|
Issue Dt:
|
10/10/2000
|
Application #:
|
08908861
|
Filing Dt:
|
08/08/1997
|
|
Title:
|
ADJUSTABLE VERIFY AND PROGRAM VOLTAGES IN PROGRAMMABLE DEVICES
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|
|
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|
Patent #:
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|
Issue Dt:
|
01/18/2000
|
Application #:
|
08911471
|
Filing Dt:
|
08/14/1997
|
|
Title:
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INDENTIFICATION OF THE COMPOSITION OF PARTICLES IN A PROCESS CHAMBER
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|
|
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|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08914543
|
Filing Dt:
|
08/19/1997
|
|
Title:
|
HIGH VOLTAGE NMOS PASS GATE HAVING SUPPLY RANGE, AREA, AND SPEED ADVANTAGES
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|
Patent #:
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|
Issue Dt:
|
04/24/2001
|
Application #:
|
08914960
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Filing Dt:
|
08/20/1997
|
|
Title:
|
SYSTEM AND METHOD FOR INTERFACING AN INPUT/OUTPUT SYSTEM MEMORY TO A HOST COMPUTER SYSTEM
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|
|
|
Patent #:
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|
Issue Dt:
|
12/29/1998
|
Application #:
|
08915054
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
VOLTAGE BOOST CIRCUIT AND OPERATION THEREOF AT LOW POWER SUPPLY VOLTAGES
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|
|
Patent #:
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|
Issue Dt:
|
05/16/2000
|
Application #:
|
08915370
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
SYSTEM AND METHOD FOR UPDATING THE DATA STORED IN A CACHE MEMORY ATTACHED TO AN INPUT/OUTPUT SYSTEM
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|
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|
Patent #:
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|
Issue Dt:
|
05/02/2000
|
Application #:
|
08915984
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
REDUNDANCY SCHEME PROVIDING IMPROVEMENTS IN REDUNDANT CIRCUIT ACCESS TIME AND INTEGRATED CIRCUIT LAYOUT AREA
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|
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|
Patent #:
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|
Issue Dt:
|
08/17/1999
|
Application #:
|
08917149
|
Filing Dt:
|
08/25/1997
|
|
Title:
|
REDUCTION OF CHARGE LOSS IN NONVOLATILE MEMORY CELLS BY PHOSPHORUS IMPLANTATION INTO PECVD NITRIDE/OXYNITRIDE FILMS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/08/1998
|
Application #:
|
08920200
|
Filing Dt:
|
08/25/1997
|
|
Title:
|
CIRCUIT AND METHOD FOR MEASURING THE DIFFERENCE FREQUENCY BETWEEN TWO CLOCKS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/14/2000
|
Application #:
|
08920539
|
Filing Dt:
|
08/27/1997
|
|
Title:
|
MECHANISM FOR DETECTING PARTICULATE FORMATION AND/OR FAILURES IN THE REMOVAL OF GAS FROM A LIQUID
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08926611
|
Filing Dt:
|
09/10/1997
|
|
Title:
|
NON-VOLATILE RANDOM ACCESS MEMORY AND METHODS FOR MAKING AND CONFIGURING SAME
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|
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|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
08929308
|
Filing Dt:
|
09/03/1997
|
|
Title:
|
METHOD AND STRUCTURE FOR A SINGLE-SIDED NON-SELF-ALIGNED TRANSISTOR
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/05/2000
|
Application #:
|
08931989
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
SCAN PATH CIRCUITRY FOR PROGRAMMING A VARIABLE CLOCK PULSE WIDTH
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/10/1999
|
Application #:
|
08932315
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
SCAN PATH CIRCUITRY INCLUDING A PROGRAMMABLE DELAY CIRCUIT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/21/1999
|
Application #:
|
08932637
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
TEST MODE FEATURES FOR SYNCHRONOUS PIPELINED MEMORIES
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
09/14/1999
|
Application #:
|
08932638
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
SCAN PATH CIRCUITRY INCLUDING AN OUTPUT REGISTER HAVING A FLOW THROUGH MODE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
09/14/1999
|
Application #:
|
08933139
|
Filing Dt:
|
09/18/1997
|
|
Title:
|
VOLTAGE LEVEL INTERFACE CIRCUIT WITH SET UP AND HOLD CONTROL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/19/2002
|
Application #:
|
08933562
|
Filing Dt:
|
09/19/1997
|
|
Title:
|
METHOD AND APPARATUS TO PREVENT LATCH-UP IN CMOS DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08934805
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHODS, CIRCUITS AND DEVICES FOR IMPROVING CROSSOVER PERFORMANCE AND/OR MONOTONICITY, AND APPLICATIONS OF THE SAME IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/15/1999
|
Application #:
|
08934933
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHODS, CIRCUITS AND DEVICES FOR IMPROVING CROSSOVER PERFORMANCE AND/OR MONOTONICITY, AND APPLICATIONS OF THE SAME IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/27/1999
|
Application #:
|
08935350
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHODS, CIRCUITS AND DEVICES FOR REDUCING AND/OR IMPROVING CROSSOVER PERFORMANCE AND/OR MONOTONICITY, AND APPLICATIONS OF THE SAME IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/26/2000
|
Application #:
|
08935705
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
PLASMA ETCHING METHOD
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
05/09/2000
|
Application #:
|
08937597
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
VOLTAGE THRESHOLD DETECTION CIRCUIT
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
03/16/1999
|
Application #:
|
08938292
|
Filing Dt:
|
09/26/1997
|
|
Title:
|
SELECTIVE BIT LINE RECOVERY IN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
08939196
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/07/2000
|
Application #:
|
08939838
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
ISOLATION SCHEME BASED ON RECESSED LOCOS USING A SLOPED SI ETCH AND DRY FIELD OXIDATION
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
10/12/1999
|
Application #:
|
08940437
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
SYMMETRIC LOGIC BLOCK INPUT/OUTPUT SCHEME
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
06/15/1999
|
Application #:
|
08940674
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
04/08/2003
|
Application #:
|
08940682
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
HYBRID ROUTING ARCHITECTURE FOR HIGH DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08944904
|
Filing Dt:
|
10/06/1997
|
|
Title:
|
HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR AND FLASH NON-VOLATILE MEMORY DEVICE HAVING THE PASS GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
08946030
|
Filing Dt:
|
10/07/1997
|
|
Title:
|
CIRCULAR PRODUCT TERM ALLOATIONS SCHEME FOR A PROGRAMMABLE DEVICE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
03/30/1999
|
Application #:
|
08947123
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
MEMORY CELL FOR STORING AT LEAST THREE LOGIC STATES
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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08949861
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Filing Dt:
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10/14/1997
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Title:
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VOLTAGE REFERENCE SOURCE FOR AN OVERVOLTAGE-TOLERANT BUS INTERFACE
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08949863
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Filing Dt:
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10/14/1997
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Title:
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OVERVOLTAGE-TOLERANT INPUT OUTPUT BUFFERS HAVING A SWITCH CONFIGURED T TO ISOLATE A PUL-UP TRANSISTOR FROM A VOLTAGE SUPPLY
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08955794
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Filing Dt:
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10/22/1997
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Title:
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MEMORY CELL FABRICATION EMPLOYING AN INTERPOLY GATE DIELECTRIC ARRANGED UPON A POLISHED FLOATING GATE
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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08958464
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Filing Dt:
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10/27/1997
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Title:
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SYMMETRICAL NOR GATES
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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08962860
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Filing Dt:
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11/03/1997
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Title:
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STABLE ADJUSTABLE PROGRAMMING VOLTAGE SCHEME
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08963843
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Filing Dt:
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11/04/1997
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Title:
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CIRCUIT AND METHOD FOR RESETTING A MICROCONTROLLER
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08967658
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Filing Dt:
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11/10/1997
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Title:
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SKEW-REDUCTION CIRCUIT
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08970107
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Filing Dt:
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11/13/1997
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Title:
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LOW TEMPERATURE METALLIZATION PROCESS
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08970448
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Filing Dt:
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11/14/1997
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Title:
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PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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08970452
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Filing Dt:
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11/14/1997
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Title:
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REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY
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|
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08970453
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Filing Dt:
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11/14/1997
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Title:
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SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08970454
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Filing Dt:
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11/14/1997
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Title:
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COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08970518
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Filing Dt:
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11/14/1997
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Title:
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REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08970519
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Filing Dt:
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11/14/1997
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Title:
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SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08970522
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Filing Dt:
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11/14/1997
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Title:
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PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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08971627
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Filing Dt:
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11/17/1997
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Title:
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DYNAMIC PULL-UP SUPPRESSOR FOR COLUMN REDUNDANCY WRITE SCHEMES WITH REDUNDANT DATA LINES
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08974736
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Filing Dt:
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11/19/1997
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Title:
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UNIVERSAL SERIAL BUS TO PARALLEL BUS SIGNAL CONVERTER AND METHOD OF CONVERSION
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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08974971
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Filing Dt:
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11/20/1997
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Title:
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NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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08976303
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Filing Dt:
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11/21/1997
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Title:
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BIOS MEMORY AND MULTIMEDIA DATA STORAGE COMBINATION
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|
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Patent #:
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Issue Dt:
|
02/01/2000
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Application #:
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08978107
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Filing Dt:
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11/25/1997
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Title:
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METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
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|
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Patent #:
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Issue Dt:
|
02/15/2000
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Application #:
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08978398
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Filing Dt:
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11/25/1997
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Title:
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METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
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Patent #:
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Issue Dt:
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01/25/2000
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Application #:
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08982186
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Filing Dt:
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12/17/1997
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Title:
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METHOD FOR FORMING A LOW BARRIER HEIGHT OXIDE LAYER ON A SILICON SUBSTRATE
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08982730
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Filing Dt:
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12/02/1997
|
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Title:
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METHOD AND APPARATUS FOR GENERATING TEST PATTERN FOR SECQUENCE DETECTION
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|
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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08985890
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Filing Dt:
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12/05/1997
|
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Title:
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PARALLEL TEST FOR ASYNCHRONOUS MEMORY
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|
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08986160
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Filing Dt:
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12/05/1997
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Title:
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SIDEWALL SPACER FOR PROTECTING TUNNEL OXIDE DURING ISOLATION TRENCH FORMATION IN SELF-ALIGNED FLASH MEMORY CORE
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|
|
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08986371
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Filing Dt:
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12/08/1997
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Title:
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METHOD OF REDUCING IMPURITY CONTAMINATION IN SEMICONDUCTOR PROCESS CHAMBERS
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08986440
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Filing Dt:
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12/08/1997
|
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Title:
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CURRENTSENSING AMPLIFIER WITH FEEDBACK
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|
|
|
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08986860
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Filing Dt:
|
12/08/1997
|
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Title:
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METHOD OF ELIMINATING POLY STRINGER IN A MEMORY DEVICE
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|
|
|
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Patent #:
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Issue Dt:
|
04/04/2000
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Application #:
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08986951
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Filing Dt:
|
12/08/1997
|
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Title:
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ELIMINATION OF POLY STRINGERS WITH STRAIGHT POLY PROFILE
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|
|
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Patent #:
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Issue Dt:
|
08/03/1999
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Application #:
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08986953
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Filing Dt:
|
12/08/1997
|
|
Title:
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REDUCTION OF ONO FENCE DURING SELF-ALIGNED ETCH TO ELIMINATE POLY STRINGERS
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|
|
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Patent #:
|
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Issue Dt:
|
08/01/2000
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Application #:
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08988942
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Filing Dt:
|
12/11/1997
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Title:
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APPARATUS AND METHOD FOR CORRECTING DATA IN A NON- VOLATILE RANDOM ACCESS MEMORY
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