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08/22/2000
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08989707
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12/12/1997
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Title:
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12/14/1999
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08989820
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12/12/1997
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Title:
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08/17/1999
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08990126
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12/12/1997
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Title:
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11/30/1999
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08991052
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12/16/1997
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Title:
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10/05/1999
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08991231
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12/16/1997
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Title:
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05/24/2005
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08991232
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12/16/1997
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06/06/2000
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08991299
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12/16/1997
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01/12/1999
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08991466
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12/16/1997
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Title:
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PROGRAMMING OF MEMORY CELLS USING CONNECTED FLOATING GATE ANALOG REFERENCE CELL
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10/03/2000
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08991687
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12/16/1997
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Title:
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04/02/2002
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08991845
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12/16/1997
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APPARATUS AND METHOD FOR SHORTING RESTRANSMIT RECOVERY TIMES UTILIZING CACHE MEMORY IN HIGH SPEED FIFO
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05/25/1999
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08992077
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12/17/1997
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Title:
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12/21/1999
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08992199
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12/17/1997
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Title:
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CIRCUIT AND METHOD FOR INSTRUCTION CONTROLLABLE SLEW RATE OF BIT LINE DRIVER
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02/22/2000
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08992536
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12/17/1997
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Title:
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05/14/2002
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08992616
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING LOCALIZED GATE EDGE ROUNDING WITH MINIMAL ENCROACHMENT AND GATE EDGE LIFTING
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08/15/2000
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08992618
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12/17/1997
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Title:
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09/07/1999
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08992622
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR SELECTED SOURCE DURING READ AND PROGRAMMING OF FLASH MEMORY
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03/07/2000
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08992950
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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10/26/1999
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08992951
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A TAPERED FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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07/10/2001
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08992960
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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09/26/2000
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08992961
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12/18/1997
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NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
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04/25/2000
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08993036
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12/18/1997
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METHOD AND APPARATUS FOR OBTAINING TWO-OR THREE-DEMENSIONAL INFORMATION FROM SCANNING ELECTRON MICROSCOPY
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02/06/2001
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08993062
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12/18/1997
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DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
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11/30/1999
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08993343
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12/18/1997
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MANUFACTURING PROCESS TO ELIMINATE POLYSTRINGERS IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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08/28/2001
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08993344
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12/18/1997
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MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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12/23/2003
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12/18/1997
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NOVEL NAND TYPE CORE CELL STRUCTURE FOR A HIGH DENSITY FLASH MEMORY DEVICE HAVING A UNIQUE SELECT GATE TRANSISTOR CONFIGURATION
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05/16/2000
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08993409
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12/18/1997
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METHODS FOR FORMING A CONTROL GATE APPARATUS IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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09/05/2000
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08993443
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12/18/1997
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NITROGEN ION IMPLANTED AMORPHOUS SILICON TO PRODUCE OXIDATION RESISTANT AND FINER GRAIN POLYSILICON BASED FLOATING GATES
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10/31/2000
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08993444
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12/18/1997
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08/17/1999
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08993599
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12/18/1997
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METHOD AND SYSTEM FOR SOURCE ONLY REOXIDATION AFTER JUNCTION IMPLANT FOR FLASH MEMORY DEVICES
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02/15/2000
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08993600
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12/18/1997
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METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
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12/21/1999
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08993634
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12/18/1997
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06/27/2000
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12/18/1997
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METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
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01/18/2000
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08993787
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12/19/1997
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12/14/1999
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12/18/1997
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NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
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12/11/2001
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12/19/1997
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METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
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02/08/2000
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12/22/1997
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09/26/2000
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12/22/1997
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11/14/2000
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12/24/1997
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OPTIMIZED PROGRAMMING/ERASE PARAMETERS FOR PROGRAMMABLE DEVICES
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09/28/1999
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12/29/1997
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12/26/2000
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12/30/1997
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10/26/1999
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01/05/1998
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05/22/2001
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01/13/1998
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02/13/2001
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01/14/1998
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06/14/2005
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01/14/1998
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04/06/1999
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01/15/1998
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12/10/2002
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01/16/1998
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12/14/1999
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01/16/1998
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08/17/1999
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01/21/1998
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02/29/2000
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01/27/1998
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06/22/1999
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01/30/1998
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02/02/1999
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02/03/1998
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10/05/1999
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02/05/1998
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07/17/2001
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02/10/1998
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08/21/2001
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02/10/1998
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06/27/2000
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02/10/1998
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05/30/2000
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02/11/1998
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03/30/1999
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02/13/1998
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10/24/2000
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02/13/1998
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07/13/1999
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02/19/1998
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08/08/2000
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02/27/1998
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07/18/2000
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02/27/1998
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02/13/2001
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03/03/1998
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03/28/2000
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03/03/1998
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08/29/2000
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03/03/1998
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02/29/2000
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03/03/1998
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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01/02/2001
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03/06/1998
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09/12/2000
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03/10/1998
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05/01/2001
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03/17/1998
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Title:
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TRANSMISSION LINE IMPEDANCE MATCHING OUTPUT BUFFER
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09040107
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Filing Dt:
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03/17/1998
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Title:
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NEW APPROACH FOR THE FORMATION OF SEMICONDUCTOR DEVICES WHICH REDUCES BAND-TO-BAND TUNNELING CURRENT AND SHORT-CHANNEL EFFECTS
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09040823
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Filing Dt:
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03/18/1998
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Title:
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PROCESS FOR FABRICATING A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09044389
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Filing Dt:
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03/18/1998
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Title:
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STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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09045013
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Filing Dt:
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03/20/1998
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Title:
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NARROWER ERASE DISTRIBUTION FOR FLASH MEMORY BY SMALLER POLY GRAIN SIZE
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09045269
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Filing Dt:
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03/20/1998
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Title:
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INTEGRATED NON-VOLATILE AND CMOS MEMORIES HAVING SUBSTANTIALLY THE SAME THICKNESS GATES AND METHODS OF FORMING THE SAME
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09045294
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Filing Dt:
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03/20/1998
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Title:
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INTEGRATED NON-VOLATILE AND RANDOM ACCESS MEMORY AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09046757
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Filing Dt:
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03/24/1998
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Title:
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APPARATUS, METHOD AND KIT FOR ADJUSTING INTEGRATED CIRCUIT LEAD DEFLECTION UPON A TEST SOCKET CONDUCTOR
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09046960
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Filing Dt:
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03/24/1998
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Title:
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REDUCED AREA PRODUCT-TERM ARRAY
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09046962
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Filing Dt:
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03/24/1998
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Title:
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APPARATUS, METHOD AND KIT FOR ALIGNING AN INTEGRATED CIRCUIT TO A TEST SOCKET
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09047237
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Filing Dt:
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03/25/1998
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Title:
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CAPACITOR FOR USE IN A CAPACITOR DIVIDER THAT HAS A FLOATING GATE TRANSISTOR AS A CORRESPONDING CAPACITOR
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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09049517
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Filing Dt:
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03/27/1998
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Title:
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PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT WITH A SELF-ALIGNED CONTACT
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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09049823
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Filing Dt:
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03/27/1998
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Title:
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INPUT BUFFER WITH PARALLEL PULL-UP TRANSISTORS WHEREIN THE BUFFER CAN BE SELECTIVELY CONFIGURED AS A VOLTAGE REFERENCED BUFFER OF A NON-REFERENCED BUFFER
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09049887
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Filing Dt:
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03/27/1998
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Title:
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CIRCUITRY ARCHITECTURE AND METHOD FOR IMPROVING OUTPUT TRI-STATE TIME
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09049952
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Filing Dt:
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03/27/1998
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Title:
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MEMORY DEVICES OPERABLE IN BOTH A NORMAL AND A TEST MODE AND METHODS FOR TESTING SAME
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09050242
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Filing Dt:
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03/30/1998
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Title:
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CIRCUITRY, APPARATUS AND METHOD FOR EMBEDDING A TEST STATUS OUTCOME WITHIN A CIRCUIT BEING TESTED
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09050243
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Filing Dt:
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03/30/1998
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Title:
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CIRCUITRY, APPARATUS AND METHOD FOR EMBEDDING QUANTIFIABLE TEST RESULTS WITHIN A CIRCUIT BEING TESTED
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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09050521
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Filing Dt:
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03/30/1998
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Title:
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VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY GAIN COMPENSATION CIRCUIT
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Patent #:
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Issue Dt:
|
10/15/2002
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Application #:
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09050548
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Filing Dt:
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03/30/1998
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Title:
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INTEGRATED CIRCUITRY FOR DELAY GENERATION
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Patent #:
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Issue Dt:
|
12/19/2000
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Application #:
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09051700
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Filing Dt:
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04/16/1998
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Title:
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SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE HAVING A NAND CELL STRUCTURE
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Patent #:
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Issue Dt:
|
09/04/2001
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Application #:
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09052057
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
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Patent #:
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Issue Dt:
|
05/01/2001
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Application #:
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09052058
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09052060
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Filing Dt:
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03/30/1998
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Title:
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FULLY RECESSED SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
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|
|
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09052061
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Filing Dt:
|
03/30/1998
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Title:
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FULLY RECESSED SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
11/23/1999
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Application #:
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09052062
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD WITH CORNER DOPING AND SIDEWALL DOPING
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|
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09052219
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Filing Dt:
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03/31/1998
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Title:
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PLANARIZING A TRENCH DIELECTRIC HAVING AN UPPER SURFACE WITHIN A TRENCH SPACED BELOW AN ADJACENT POLISH STOP SURFACE
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|
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09052770
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Filing Dt:
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03/31/1998
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Title:
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NONVOLATILE SEMICONDUCTOR MEMORY CELL WITH SELECT GATE
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|
|
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Patent #:
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Issue Dt:
|
12/21/1999
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Application #:
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09054654
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Filing Dt:
|
04/03/1998
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Title:
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TEST MODE ENTRANCE THROUGH CLOCKED ADDRESSES
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|
|
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Patent #:
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Issue Dt:
|
09/14/1999
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Application #:
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09057783
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Filing Dt:
|
04/09/1998
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Title:
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ANTI-WAFER BREAKAGE DETECTION SYSTEM
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|
|
|
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09057798
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Filing Dt:
|
04/09/1998
|
|
Title:
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ANTI-WAFER BREAKAGE DETECTION SYSTEM
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|
|
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Patent #:
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|
Issue Dt:
|
03/20/2001
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Application #:
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09061362
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Filing Dt:
|
04/15/1998
|
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Title:
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FERROELECTRIC THIN FILMS AND SOLUTIONS: COMPOSITIONS
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|
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09061515
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Filing Dt:
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04/16/1998
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Title:
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ELIMINATION OF POLY CAP FOR EASY POLY1 CONTACT FOR NAND PRODUCT
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|
|
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Patent #:
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|
Issue Dt:
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12/07/1999
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Application #:
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09063688
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Filing Dt:
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04/21/1998
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|
Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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