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05/30/2000
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01/27/1999
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01/27/1999
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07/17/2001
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01/27/1999
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01/16/2001
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02/09/1999
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11/09/1999
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09/19/2000
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02/18/1999
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02/18/1999
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02/22/1999
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02/22/1999
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10/17/2000
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02/24/1999
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04/24/2001
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02/25/1999
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12/18/2001
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02/26/1999
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01/30/2001
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03/04/1999
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03/12/2002
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03/05/1999
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02/06/2001
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03/05/1999
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10/30/2001
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03/05/1999
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11/29/2001
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05/23/2000
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03/18/1999
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05/15/2001
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03/19/1999
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02/20/2001
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03/24/1999
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01/09/2001
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03/24/1999
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12/05/2000
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03/25/1999
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12/07/1999
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03/26/1999
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08/08/2000
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08/20/2002
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03/30/1999
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06/05/2001
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11/07/2000
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03/31/1999
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04/16/2002
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02/18/2003
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04/08/1999
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01/16/2003
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10/16/2001
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04/27/1999
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11/19/2002
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05/06/1999
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02/13/2001
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11/12/2002
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02/07/2002
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10/24/2000
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04/02/2002
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05/08/2001
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06/24/2003
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08/20/2002
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09/03/2002
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04/30/2002
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05/22/2001
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05/28/1999
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09/12/2000
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04/10/2001
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11/22/2001
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Title:
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UNIVERSAL LOGIC CHIP
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09336057
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Filing Dt:
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06/18/1999
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Title:
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METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF-ALIGNED SOURCE FORMED AND A DEVICE PROVIDED BY SUCH A METHOD
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09339602
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Filing Dt:
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06/24/1999
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Title:
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POWER-ON-RESET CIRCUIT WITH ANALOG DELAY AND HIGH NOISE IMMUNITY
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09340506
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Filing Dt:
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07/01/1999
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Title:
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NON-CONTACTING TEMPERATURE SENSING DEVICE
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09343404
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Filing Dt:
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06/30/1999
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Title:
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VOLTAGE BOOSTING CIRCUIT
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09344514
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Filing Dt:
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06/25/1999
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Title:
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METHOD AND CIRCUITRY FOR WRITING DATA
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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09345173
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Filing Dt:
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06/30/1999
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Title:
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METHOD FOR ETCHING AND/OR PATTERNING A SILICON-CONTAINING LAYER
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09347074
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Filing Dt:
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07/02/1999
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Title:
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METHODS OF CONVERTING AND/OR TRANSLATING A LAYOUT OR CIRCUIT SCHEMATIC OR NETLIST THEREOF TO A SIMULATION SCHEMATIC OR NETLIST, AND/OR OF SIMULATING FUNCTION(S) AND/OR PERFORMANCE CHARACTERISTIC(S) OF A CIRCUIT
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09348583
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Filing Dt:
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07/07/1999
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Title:
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LIGHT FLOATING GATE DOPING TO IMPROVE TUNNEL OXIDE RELIABILITY
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09349603
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Filing Dt:
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07/09/1999
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Title:
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METHOD OF FORMING SELECT GATE TO IMPROVE RELIABILITY AND PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09351563
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Filing Dt:
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07/12/1999
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Title:
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FERROELECTRIC NON-VOLATILE LATCH CIRCUITS
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09352801
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Filing Dt:
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07/13/1999
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Title:
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THIN FLOATING GATE AND CONDUCTIVE SELECT GATE IN SITU DOPED AMORPHOUS SILICON MATERIAL FOR NAND TYPE FLASH MEMORY DEVICE APPLICATIONS
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09353267
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Filing Dt:
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07/14/1999
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Title:
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REDUCTION OF VOLTAGE STRESS ACROSS A GATE OXIDE AND ACROSS A JUNCTION WITHIN A HIGH VOLTAGE TRANSISTOR OF AN ERASABLE MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09357333
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Filing Dt:
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07/20/1999
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A SINGLE INTERPOLY DIELECTRIC LAYER IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09357716
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Filing Dt:
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07/20/1999
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Title:
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SYMMETRIC LOGIC BLOCK INPUT/OUTPUT SCHEME
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09359465
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Filing Dt:
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07/22/1999
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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OPTIMIZED I2O MESSAGING UNIT
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09364982
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Filing Dt:
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07/31/1999
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Title:
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METHOD FOR INHIBITING TUNNEL OXIDE GROWTH AT THE EDGES OF A FLOATING GATE DURING SEMICONDUCOR DEVICE PROCESSING
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09366369
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Filing Dt:
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08/03/1999
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Title:
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DEVICE MODELING AND CHARACTERIZATION STRUCTURE WITH MULTIPLEXED PADS
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09368073
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Filing Dt:
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08/03/1999
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Title:
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METHOD FOR REDUCED GATE ASPECT RATIO TO IMPROVE GAP-FILL AFTER SPACER ETCH
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09368247
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Filing Dt:
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08/03/1999
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Title:
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METHOD FOR MONITORING SECOND GATE OVER-ETCH IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09369600
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Filing Dt:
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08/06/1999
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Title:
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MULTI STATE SENSING OF NAND MEMORY CELLS BY VARYING SOURCE BIAS
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09369638
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Filing Dt:
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08/06/1999
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Title:
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METHOD FOR PROVIDING A DOPANT LEVEL FOR POLYSILICON FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09370010
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Filing Dt:
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08/06/1999
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Title:
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MULTI STATE SENSING OF NAND MEMORY CELLS BY APPLYING REVERSE-BIAS VOLTAGE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09370380
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Filing Dt:
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08/09/1999
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Title:
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RAMPED GATE TECHNIQUE FOR SOFT PROGRAMMING TO TIGHTEN THE VT DISTRIBUTION
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09370411
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Filing Dt:
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08/09/1999
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Title:
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TUBE PROTECTION DEVICES AND METHODS
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09370669
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Filing Dt:
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08/09/1999
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Title:
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DUAL-FUNCTION METHOD AND CIRCUIT FOR PROGRAMMABLE DEVICE
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09371237
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Filing Dt:
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08/10/1999
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Title:
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FLAG GENERATION SCHEME FOR FIFOS
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09372344
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Filing Dt:
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08/11/1999
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Title:
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UNIVERSAL SERIAL BUS TO PARALLEL BUS SIGNAL CONVERTER AND METHOD OF CONVERSION
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09372406
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Filing Dt:
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08/10/1999
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Title:
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METHOD OF REDUCING PROGRAM DISTURBS IN NAND TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09373870
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Filing Dt:
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08/13/1999
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Title:
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MULTIPLE POWER SUPPLY OUTPUT DRIVER
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09375504
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Filing Dt:
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08/17/1999
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Title:
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METHOD FOR ETCHING MEMORY GATE STACK USING THIN RESIST LAYER
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09376659
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Filing Dt:
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08/18/1999
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Title:
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METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
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