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Reel/Frame:039708/0001   Pages: 123
Recorded: 08/11/2016
Attorney Dkt #:3483.000
Conveyance: PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS
Total properties: 2101
Page 6 of 22
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
Patent #:
6252276
Issue Dt:
06/26/2001
Application #:
09377183
Filing Dt:
08/19/1999
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ASSYMETRICALLY NITROGEN DOPED GATE OXIDE
2
Patent #:
6088287
Issue Dt:
07/11/2000
Application #:
09379479
Filing Dt:
08/23/1999
Title:
FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT FOR WORD LINE DECODING
3
Patent #:
6323683
Issue Dt:
11/27/2001
Application #:
09384510
Filing Dt:
08/27/1999
Title:
LOW DISTORTION LOGIC LEVEL TRANSLATOR
4
Patent #:
6242790
Issue Dt:
06/05/2001
Application #:
09385550
Filing Dt:
08/30/1999
Title:
USING POLYSILICON FUSE FOR IC PROGRAMMING
5
Patent #:
6411069
Issue Dt:
06/25/2002
Application #:
09387018
Filing Dt:
08/31/1999
Title:
CONTINOUS CAPACITOR DIVIDER SAMPLED REGULATION SCHEME
6
Patent #:
6418054
Issue Dt:
07/09/2002
Application #:
09387421
Filing Dt:
08/31/1999
Title:
EMBEDDED METHODOLOGY TO PROGRAM/ERASE REFERENCE CELLS USED IN SENSING FLASH CELLS
7
Patent #:
6576949
Issue Dt:
06/10/2003
Application #:
09387710
Filing Dt:
08/30/1999
Title:
INTEGRATED CIRCUIT HAVING OPTIMIZED GATE COUPLING CAPACITANCE
8
Patent #:
6141244
Issue Dt:
10/31/2000
Application #:
09388696
Filing Dt:
09/02/1999
Title:
MULTI LEVEL SENSING OF NAND MEMORY CELLS BY EXTERNAL BIAS CURRENT
9
Patent #:
6141255
Issue Dt:
10/31/2000
Application #:
09389161
Filing Dt:
09/02/1999
Title:
1 TRANSISTOR CELL FOR EEPROM APPLICATION
10
Patent #:
6323516
Issue Dt:
11/27/2001
Application #:
09390052
Filing Dt:
09/03/1999
Title:
FLASH MEMORY DEVICE AND FABRICATION METHOD HAVING A HIGH COUPLING RATIO
11
Patent #:
6194965
Issue Dt:
02/27/2001
Application #:
09390591
Filing Dt:
09/03/1999
Title:
DIFFERENTIAL SIGNAL DETECTION CIRCUIT
12
Patent #:
6287917
Issue Dt:
09/11/2001
Application #:
09392675
Filing Dt:
09/08/1999
Title:
PROCESS FOR FABRICATING AN MNOS FLASH MEMORY DEVICE
13
Patent #:
6302766
Issue Dt:
10/16/2001
Application #:
09394819
Filing Dt:
09/13/1999
Title:
SYSTEM FOR CLEANING A SURFACE OF A DIELECTRIC MATERIAL
14
Patent #:
6327175
Issue Dt:
12/04/2001
Application #:
09395057
Filing Dt:
09/13/1999
Title:
METHOD AND APPARATUS FOR CONTROLLING A MEMORY ARRAY WITH A PROGRAMMABLE REGISTER
15
Patent #:
6292013
Issue Dt:
09/18/2001
Application #:
09396024
Filing Dt:
09/15/1999
Title:
COLUMN REDUNDANCY SCHEME FOR BUS-MATCHING FIFOS
16
Patent #:
6229345
Issue Dt:
05/08/2001
Application #:
09396344
Filing Dt:
09/15/1999
Title:
HIGH SPEED CHARGE-PUMP
17
Patent #:
6526470
Issue Dt:
02/25/2003
Application #:
09398736
Filing Dt:
09/17/1999
Title:
FIFO BUS-SIZING, BUS-MATCHING DATAPATH ARCHITECTURE
18
Patent #:
6239632
Issue Dt:
05/29/2001
Application #:
09398936
Filing Dt:
09/17/1999
Title:
METHOD, ARCHITECTURE AND/OR CIRCUITRY FOR CONTROLLING THE PULSE WIDTH IN A PHASE AND/OR FREQUENCY DETECTOR
19
Patent #:
6704381
Issue Dt:
03/09/2004
Application #:
09398956
Filing Dt:
09/17/1999
Title:
FREQUENCY ACQUISITION RATE CONTROL IN PHASE LOCK LOOP CIRCUITS
20
Patent #:
6380033
Issue Dt:
04/30/2002
Application #:
09399414
Filing Dt:
09/20/1999
Title:
PROCESS TO IMPROVE READ DISTURB FOR NAND FLASH MEMORY DEVICES
21
Patent #:
6284602
Issue Dt:
09/04/2001
Application #:
09399526
Filing Dt:
09/20/1999
Title:
PROCESS TO REDUCE POST CYCLING PROGRAM VT DISPERSION FOR NAND FLASH MEMORY DEVICES
22
Patent #:
6191636
Issue Dt:
02/20/2001
Application #:
09400685
Filing Dt:
09/22/1999
Title:
INPUT BUFFER/LEVEL SHIFTER
23
Patent #:
6530040
Issue Dt:
03/04/2003
Application #:
09401614
Filing Dt:
09/22/1999
Title:
PARALLEL TEST IN ASYNCHRONOUS MEMORY WITH SINGLE-ENDED OUTPUT PATH
24
Patent #:
6172914
Issue Dt:
01/09/2001
Application #:
09404078
Filing Dt:
09/23/1999
Title:
CONCURRENT ERASE VERIFY SCHEME FOR FLASH MEMORY APPLICATIONS
25
Patent #:
6049479
Issue Dt:
04/11/2000
Application #:
09404080
Filing Dt:
09/23/1999
Title:
OPERATIONAL APPROACH FOR THE SUPPRESSION OF BI-DIRECTIONAL TUNNEL OXIDE STRESS OF A FLASH CELL
26
Patent #:
6369416
Issue Dt:
04/09/2002
Application #:
09404394
Filing Dt:
09/23/1999
Title:
SEMICONDUCTOR DEVICE WITH CONTACTS HAVING A SLOPED PROFILE
27
Patent #:
6342415
Issue Dt:
01/29/2002
Application #:
09404395
Filing Dt:
09/23/1999
Publication #:
US20020025618
Pub Dt:
02/28/2002
Title:
METHOD AND SYSTEM FOR PROVIDING REDUCED-SIZED CONTACTS IN A SEMICONDUCTOR DEVICE
28
Patent #:
6734108
Issue Dt:
05/11/2004
Application #:
09405945
Filing Dt:
09/27/1999
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING CONTACTS IN A SEMICONDUCTOR STRUCTURE
29
Patent #:
6088289
Issue Dt:
07/11/2000
Application #:
09405950
Filing Dt:
09/27/1999
Title:
CIRCUIT AND METHOD FOR CONTROLLING A WORDLINE AND/OR STABILIZING A MEMORY CELL
30
Patent #:
6201747
Issue Dt:
03/13/2001
Application #:
09409542
Filing Dt:
09/30/1999
Title:
METHOD AND APPARATUS FOR MEASURING SUBTHRESHOLD CURRENT IN A MEMORY ARRAY
31
Patent #:
7062425
Issue Dt:
06/13/2006
Application #:
09410160
Filing Dt:
09/30/1999
Title:
METHOD AND APPARATUS FOR AUTOMATED ENUMERATION, SIMULATION, IDENTIFICATION AND/OR IRRADIATION OF DEVICE ATTRIBUTES
32
Patent #:
6266275
Issue Dt:
07/24/2001
Application #:
09410512
Filing Dt:
09/30/1999
Title:
DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
33
Patent #:
6452441
Issue Dt:
09/17/2002
Application #:
09411169
Filing Dt:
10/01/1999
Title:
LOW THRESHOLD VOLTAGE DEVICE WITH CHARGE PUMP FOR REDUCING STANDBY CURRENT IN AN INTEGRATED CIRCUIT HAVING REDUCED SUPPLY VOLTAGE
34
Patent #:
6177316
Issue Dt:
01/23/2001
Application #:
09412278
Filing Dt:
10/05/1999
Title:
POST BARRIER METAL CONTACT IMPLANTATION TO MINIMIZE OUT DIFFUSION FOR NAND DEVICE
35
Patent #:
6235584
Issue Dt:
05/22/2001
Application #:
09412544
Filing Dt:
10/05/1999
Title:
METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DEVICE
36
Patent #:
6122198
Issue Dt:
09/19/2000
Application #:
09413182
Filing Dt:
10/05/1999
Title:
BIT BY BIT APDE VERIFY FOR FLASH MEMORY APPLICATIONS
37
Patent #:
6506683
Issue Dt:
01/14/2003
Application #:
09413621
Filing Dt:
10/06/1999
Title:
IN-SITU PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INTEGRAL REMOVAL OF ANTIREFLECTION AND ETCH STOP LAYERS
38
Patent #:
6291296
Issue Dt:
09/18/2001
Application #:
09416382
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS BEFORE CONTACT CMP
39
Patent #:
6136649
Issue Dt:
10/24/2000
Application #:
09416389
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS AFTER CONTACT CMP
40
Patent #:
6275415
Issue Dt:
08/14/2001
Application #:
09416563
Filing Dt:
10/12/1999
Title:
MULTIPLE BYTE CHANNEL HOT ELECTRON PROGRAMMING USING RAMPED GATE AND SOURCE BIAS VOLTAGE
41
Patent #:
6197635
Issue Dt:
03/06/2001
Application #:
09417130
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED MASKING AND WITHOUT ARC LOSS IN PERIPHERAL CIRCUITRY REGION
42
Patent #:
6235587
Issue Dt:
05/22/2001
Application #:
09417131
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED ARC LOSS IN PERIPHERAL CIRCUITRY REGION
43
Patent #:
6200857
Issue Dt:
03/13/2001
Application #:
09417132
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITHOUT ARC LOSS IN PERIPHERAL CIRCUIT REGION
44
Patent #:
6118694
Issue Dt:
09/12/2000
Application #:
09417731
Filing Dt:
10/14/1999
Title:
DISTRIBUTING CFI DEVICES IN EXISTING DECODERS
45
Patent #:
6144606
Issue Dt:
11/07/2000
Application #:
09417732
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR BI-DIRECTIONAL VOLTAGE REGULATION DETECTION
46
Patent #:
6147906
Issue Dt:
11/14/2000
Application #:
09419695
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
47
Patent #:
6185130
Issue Dt:
02/06/2001
Application #:
09420209
Filing Dt:
10/18/1999
Title:
PROGRAMMABLE CURRENT SOURCE
48
Patent #:
6255165
Issue Dt:
07/03/2001
Application #:
09420220
Filing Dt:
10/18/1999
Title:
NITRIDE PLUG TO REDUCE GATE EDGE LIFTING
49
Patent #:
6662262
Issue Dt:
12/09/2003
Application #:
09420535
Filing Dt:
10/19/1999
Title:
OTP SECTOR DOUBLE PROTECTION FOR A SIMULTANEOUS OPERATION FLASH MEMORY
50
Patent #:
6125055
Issue Dt:
09/26/2000
Application #:
09421105
Filing Dt:
10/19/1999
Title:
SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
51
Patent #:
6201753
Issue Dt:
03/13/2001
Application #:
09421142
Filing Dt:
10/19/1999
Title:
LATCHING CAM DATA IN A FLASH MEMORY DEVICE
52
Patent #:
6344281
Issue Dt:
02/05/2002
Application #:
09421333
Filing Dt:
10/18/1999
Title:
ALUMINUM METALLIZATION METHOD AND PRODUCT
53
Patent #:
6285585
Issue Dt:
09/04/2001
Application #:
09421471
Filing Dt:
10/19/1999
Title:
OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
54
Patent #:
6331950
Issue Dt:
12/18/2001
Application #:
09421757
Filing Dt:
10/19/1999
Title:
WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
55
Patent #:
6178129
Issue Dt:
01/23/2001
Application #:
09421762
Filing Dt:
10/19/1999
Title:
SEPARATE OUTPUT POWER SUPPLY TO REDUCE OUTPUT NOISE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
56
Patent #:
6163478
Issue Dt:
12/19/2000
Application #:
09421774
Filing Dt:
10/19/1999
Title:
COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
57
Patent #:
6327181
Issue Dt:
12/04/2001
Application #:
09421775
Filing Dt:
10/19/1999
Title:
REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
58
Patent #:
6111787
Issue Dt:
08/29/2000
Application #:
09421776
Filing Dt:
10/19/1999
Title:
ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
59
Patent #:
6185128
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
60
Patent #:
6359808
Issue Dt:
03/19/2002
Application #:
09421985
Filing Dt:
10/19/1999
Title:
LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
61
Patent #:
6259633
Issue Dt:
07/10/2001
Application #:
09422198
Filing Dt:
10/19/1999
Title:
SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
62
Patent #:
6118698
Issue Dt:
09/12/2000
Application #:
09422199
Filing Dt:
10/19/1999
Title:
OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
63
Patent #:
6172907
Issue Dt:
01/09/2001
Application #:
09426100
Filing Dt:
10/22/1999
Title:
SILICON-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR (SONOS) TYPE MEMORY CELL AND METHOD FOR RETAINING DATA IN THE SAME
64
Patent #:
6248635
Issue Dt:
06/19/2001
Application #:
09426205
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
65
Patent #:
6218227
Issue Dt:
04/17/2001
Application #:
09426239
Filing Dt:
10/25/1999
Title:
METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
66
Patent #:
6207502
Issue Dt:
03/27/2001
Application #:
09426255
Filing Dt:
10/25/1999
Title:
METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
67
Patent #:
6326268
Issue Dt:
12/04/2001
Application #:
09426427
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
68
Patent #:
6248628
Issue Dt:
06/19/2001
Application #:
09426430
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
69
Patent #:
6265268
Issue Dt:
07/24/2001
Application #:
09426672
Filing Dt:
10/25/1999
Title:
HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
70
Patent #:
6297143
Issue Dt:
10/02/2001
Application #:
09426743
Filing Dt:
10/25/1999
Title:
PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
71
Patent #:
6516378
Issue Dt:
02/04/2003
Application #:
09426757
Filing Dt:
10/26/1999
Title:
MICROPROCESSOR FOR CONTROLLING BUSSES
72
Patent #:
6117730
Issue Dt:
09/12/2000
Application #:
09427402
Filing Dt:
10/25/1999
Title:
INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
73
Patent #:
6242305
Issue Dt:
06/05/2001
Application #:
09427404
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
74
Patent #:
6287637
Issue Dt:
09/11/2001
Application #:
09427644
Filing Dt:
10/27/1999
Title:
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
75
Patent #:
6369660
Issue Dt:
04/09/2002
Application #:
09428624
Filing Dt:
10/27/1999
Title:
CIRCUIT AND METHOD FOR PREVENTING RUNAWAY IN A PHASE LOCK LOOP
76
Patent #:
6399446
Issue Dt:
06/04/2002
Application #:
09429722
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A METALLIC HARD MASK
77
Patent #:
6147907
Issue Dt:
11/14/2000
Application #:
09430336
Filing Dt:
10/29/1999
Title:
BIASING SCHEME TO REDUCE STRESS ON NON-SELECTED CELLS DURING READ
78
Patent #:
6867097
Issue Dt:
03/15/2005
Application #:
09430366
Filing Dt:
10/28/1999
Title:
METHOD OF MAKING A MEMORY CELL WITH POLISHED INSULATOR LAYER
79
Patent #:
6329273
Issue Dt:
12/11/2001
Application #:
09430410
Filing Dt:
10/29/1999
Title:
SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
80
Patent #:
6436766
Issue Dt:
08/20/2002
Application #:
09430493
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A POLYSILICON HARD MASK
81
Patent #:
6180454
Issue Dt:
01/30/2001
Application #:
09430765
Filing Dt:
10/29/1999
Title:
METHOD FOR FORMING FLASH MEMORY DEVICES
82
Patent #:
6441418
Issue Dt:
08/27/2002
Application #:
09430848
Filing Dt:
11/01/1999
Title:
SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
83
Patent #:
6319775
Issue Dt:
11/20/2001
Application #:
09433037
Filing Dt:
10/25/1999
Title:
NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
84
Patent #:
6406960
Issue Dt:
06/18/2002
Application #:
09433041
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER
85
Patent #:
6458677
Issue Dt:
10/01/2002
Application #:
09433186
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE
86
Patent #:
6166991
Issue Dt:
12/26/2000
Application #:
09433822
Filing Dt:
11/03/1999
Title:
CIRCUIT, ARCHITECTURE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYNCHRONOUS INTEGRATED CIRCUIT
87
Patent #:
6927756
Issue Dt:
08/09/2005
Application #:
09434908
Filing Dt:
11/05/1999
Title:
APPARATUS AND METHOD FOR CONTROLLING AN ELECTRONIC PRESENTATION
88
Patent #:
6553057
Issue Dt:
04/22/2003
Application #:
09436155
Filing Dt:
11/09/1999
Title:
CIRCUIT AND METHOD FOR LINEAR CONTROL OF A SPREAD SPECTRUM TRANSITION
89
Patent #:
6232632
Issue Dt:
05/15/2001
Application #:
09436503
Filing Dt:
11/09/1999
Title:
DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
90
Patent #:
6309949
Issue Dt:
10/30/2001
Application #:
09440934
Filing Dt:
11/16/1999
Title:
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
91
Patent #:
6608612
Issue Dt:
08/19/2003
Application #:
09441134
Filing Dt:
11/17/1999
Publication #:
US20030071777
Pub Dt:
04/17/2003
Title:
SELECTOR AND MULTILAYER INTERCONNECTION WITH REDUCED OCCUPIED AREA ON SUBSTRATE
92
Patent #:
6489805
Issue Dt:
12/03/2002
Application #:
09441649
Filing Dt:
11/17/1999
Publication #:
US20020171452
Pub Dt:
11/21/2002
Title:
CIRCUITS, ARCHITECTURES, AND METHODS FOR GENERATING A PERIODIC SIGNAL IN A MEMORY
93
Patent #:
6215689
Issue Dt:
04/10/2001
Application #:
09442851
Filing Dt:
11/18/1999
Title:
ARCHITECTURE, CIRCUITRY AND METHOD FOR CONFIGURING VOLATILE AND/OR NON-VOLATILE MEMORY FOR PROGRAMMABLE LOGIC APPLICATIONS
94
Patent #:
6246263
Issue Dt:
06/12/2001
Application #:
09451958
Filing Dt:
11/30/1999
Title:
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
95
Patent #:
6467073
Issue Dt:
10/15/2002
Application #:
09451959
Filing Dt:
11/30/1999
Title:
METHOD AND APPARATUS FOR THE AUTOMATED GENERATION OF SINGLE AND MULTISTAGE PROGRAMMABLE INTERCONNECT MATRICES WITH AUTOMATIC ROUTING TOOLS
96
Patent #:
6144580
Issue Dt:
11/07/2000
Application #:
09456801
Filing Dt:
12/08/1999
Title:
NON-VOLATILE INVERTER LATCH
97
Patent #:
6329840
Issue Dt:
12/11/2001
Application #:
09458552
Filing Dt:
12/09/1999
Title:
Tristate output buffer with matched signals to pmos and nmos output transistors
98
Patent #:
6236596
Issue Dt:
05/22/2001
Application #:
09461376
Filing Dt:
12/15/1999
Title:
BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
99
Patent #:
6249464
Issue Dt:
06/19/2001
Application #:
09461632
Filing Dt:
12/15/1999
Title:
BLOCK REDUNDANCY IN ULTRA LOW POWER MEMORY CIRCUITS
100
Patent #:
6668302
Issue Dt:
12/23/2003
Application #:
09465067
Filing Dt:
12/16/1999
Title:
METHOD AND ARCHITECTURE FOR RE-PROGRAMMING CONVENTIONALLY NON-REPROGRAMMABLE TECHNOLOGY
Assignor
1
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Exec Dt:
08/11/2016
Assignees
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
2
SPANSION LLC
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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