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Patent #:
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|
Issue Dt:
|
12/30/2003
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Application #:
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09592201
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Filing Dt:
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06/13/2000
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Title:
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FAULT TOLERANT USB METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09592206
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Filing Dt:
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06/13/2000
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Title:
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FAULT TOLERANT USB METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09592700
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Filing Dt:
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06/13/2000
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Title:
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DISTRIBUTED TEST ARCHITECTURE FOR MULTIPORT RAMS OR OTHER CIRCUITRY
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09593303
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Filing Dt:
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06/13/2000
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Title:
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Method to reduce capactive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09593967
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Filing Dt:
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06/15/2000
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Title:
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METHOD OF MAKING METALLIZATION AND CONTACT STRUCTURES IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09593968
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Filing Dt:
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06/15/2000
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Title:
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METHOD OF MAKING METALLIZATION AND CONTACT STRUCTURES IN AN INTEGRATED CIRCUIT COMPRISING AN ETCH STOP LAYER
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09594207
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Filing Dt:
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06/14/2000
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Title:
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FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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09594218
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Filing Dt:
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06/14/2000
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Title:
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LOW-LATENCY INTERRUPT HANDLING DURING MEMORY ACCESS DELAY PERIODS IN MICROPROCESSORS
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09594219
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Filing Dt:
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06/14/2000
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Title:
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LOW-LATENCY DMA HANDLING IN PIPELINED PROESSORS
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09595166
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Filing Dt:
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06/15/2000
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Title:
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Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09595519
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Filing Dt:
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06/16/2000
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Title:
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Voltage boost level clamping circuit for a flash memory
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09596522
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Filing Dt:
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06/19/2000
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Title:
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COMPENSATION OF CRYSTAL START UP FOR ACCURATE TIME MEASUREMENT
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09597099
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Filing Dt:
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06/20/2000
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Title:
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HIGH SPEED LOW SKEW LVTTL OUTPUT BUFFER WITH INVERT CAPABILITY
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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09598561
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Filing Dt:
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06/21/2000
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Title:
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DUAL MODE USB-PS/2 DEVICE
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09599586
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Filing Dt:
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06/22/2000
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Title:
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JTAG INSTRUCTION REGISTER AND DECODER FOR PLDS
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09602095
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Filing Dt:
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06/22/2000
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Title:
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Voltage protection of write protect cams
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09602328
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Filing Dt:
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06/23/2000
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Title:
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Apparatus and method of direct current sensing from source side in a virtual ground array
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09604190
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Filing Dt:
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06/27/2000
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Title:
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HOT SOCKET SOFT PULL FOR ESD DEVICES
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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09605311
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Filing Dt:
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06/28/2000
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Title:
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REFERENCE -SWITCH HYSTERESIS FOR COMPARATOR APPLICATIONS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09607675
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Filing Dt:
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06/30/2000
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Title:
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DUAL-PURPOSE ANTI-REFLECTIVE COATING AND SPACER FOR FLASH MEMORY AND OTHER DUAL GATE TECHNOLOGIES AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09607697
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Filing Dt:
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06/30/2000
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Title:
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LOADABLE DIVIDE-BY-N WITH FIXED DUTY CYCLE
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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09608158
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Filing Dt:
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06/30/2000
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Title:
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A SCHEME FOR IMPROVING THE SIMULATION ACCURACY OF INTEGRATED CIRCUIT PATTERNS BY SIMULATION OF THE MASK.
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09608279
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Filing Dt:
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06/30/2000
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Title:
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TEST MODE CLOCK MULTIPLICATION
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09609192
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Filing Dt:
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06/30/2000
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Title:
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MAJORITY VOTE CIRCUIT FOR TEST MODE CLOCK MULTIPLICATION
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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09609387
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Filing Dt:
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07/03/2000
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Title:
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METHOD OF UNIFORMLY ETCHING REFRACTORY METALS, REFRACTORY METAL ALLOYS AND REFRACTORY METAL SILICIDES
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09609468
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Filing Dt:
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07/03/2000
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Title:
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Species implantation for minimizing interface defect density in flash memory devices
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09613874
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Filing Dt:
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07/10/2000
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Title:
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SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE HAVING A NAND CELL STRUCTURE
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Patent #:
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Issue Dt:
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12/25/2001
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Application #:
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09613949
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Filing Dt:
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07/11/2000
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Title:
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Circuit and method for controlling a wordline and/or stabilizing a memory cell
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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09617454
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Filing Dt:
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07/17/2000
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Title:
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METHOD FOR CLEANING PLASMA ETCH CHAMBER STRUCTURES
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09617601
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Filing Dt:
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06/12/2000
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Title:
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CPLD HIGH SPEED PATH
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09617820
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Filing Dt:
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07/17/2000
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Title:
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Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09620339
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Filing Dt:
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07/20/2000
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Title:
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Fully recessed semiconductor method for low power applications
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09620490
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Filing Dt:
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07/20/2000
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Title:
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SELF CALIBRATING, ZERO POWER PRECISION INPUT THRESHOLD CIRCUIT
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09621717
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Filing Dt:
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07/24/2000
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Title:
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STRUCTURE AND METHOD FOR MONITORING A SEMICONDUCTOR PROCESS, AND METHOD OF MAKING SUCH A STRUCTURE
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09625167
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Filing Dt:
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07/25/2000
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Title:
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REAL-TIME I/O PROCESSOR USED TO IMPLEMENT BUS INTERFACE PROTOCOLS
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09626267
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Filing Dt:
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07/25/2000
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Title:
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Semiconductor non-volatile latch device including non-volatile elements
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09626368
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Filing Dt:
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07/25/2000
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Title:
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Power management system and current augmentation and battery charger method and apparatus for a computer peripheral
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09626986
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Filing Dt:
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07/27/2000
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Title:
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Method and circuitry for writing data
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09627565
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Filing Dt:
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07/28/2000
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Title:
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Dual bit isolation scheme for flash memory devices having polysilicon floating gates
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09627567
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Filing Dt:
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07/28/2000
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Title:
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Use of an etch to reduce the thickness and round the edges of a resist mask during the creation of a memory cell
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09627664
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Filing Dt:
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07/28/2000
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Title:
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Nitrogen implant after bit-line formation for ono flash memory devices
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09629780
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Filing Dt:
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07/31/2000
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR METHOD WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09629916
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Filing Dt:
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07/31/2000
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Title:
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METHOD AND APPARATUS FOR MULITLE BOOT-UP FUNCTIONALITIES FOR A PROCGRAMMABLE LOGIC DEVICE (PLD)
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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09631427
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Filing Dt:
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08/03/2000
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Title:
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ANALOG SIGNAL VERIFICATION USING DIGITAL SIGNATURES
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09631894
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Filing Dt:
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08/04/2000
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Title:
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NOVEL CAPPING LAYER
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09632536
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Filing Dt:
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08/04/2000
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Title:
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A TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH CORNER DOPING AND SIDEWALL DOPING
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09633514
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Filing Dt:
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08/07/2000
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Title:
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Dual port sram
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09633689
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Filing Dt:
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08/07/2000
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Title:
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SEMICONDUCTOR MEMORY SELF-TEST CONTROLLABLE AT BOARD LEVEL USING STANDARD INTERFACE
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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09635507
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Filing Dt:
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08/09/2000
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Title:
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PROCESS FOR REDUCING LEAKAGE IN AN INTEGRATED CIRCUIT WITH SHALLOW TRENCH ISOLATED ACTIVE AREAS
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09638055
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Filing Dt:
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08/11/2000
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Title:
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Burst read mode word line boosting
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09639454
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Filing Dt:
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08/15/2000
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Title:
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Parallel test for asynchronous memory
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09640082
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Filing Dt:
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08/17/2000
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Title:
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OXYGEN IMPLANTATION FOR REDUCTION OF JUNCTION CAPACITANCE IN MOS TRANSISTORS
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09641091
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Filing Dt:
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08/17/2000
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Title:
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METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE STRUCTURE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09644358
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Filing Dt:
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08/23/2000
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Title:
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Precise reference wordline loading compensation for a high density flash memory device
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09645623
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Filing Dt:
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08/24/2000
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Title:
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Fast-erase memory devices and method for reducing erasing time in a memory device
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09648077
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FORMING ONO FLASH MEMORY DEVICES USING RAPID THERMAL OXIDATION
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09648221
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Filing Dt:
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08/25/2000
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Title:
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Circuit, structure and method of testing a semiconductor, such as an integrated circuit
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09648361
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FORMING ONO FLASH MEMORY DEVICES USING LOW ENERGY NITROGEN IMPLANTATION
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09649027
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Filing Dt:
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08/28/2000
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Title:
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METHOD OF MAKING TUNGSTEN GATE MOS TRANSISTOR AND MEMORY CELL BY ENCAPSULATING
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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09649551
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Filing Dt:
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08/28/2000
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Title:
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POWER SUPPLY FOR UNIVERSAL SERIAL BUS INTERFACE WITH PROGRAMMABLE BUS PULLUP RESISTOR
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09650133
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Filing Dt:
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08/29/2000
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Title:
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ANALOG ENVELOPE DETECTOR
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09650437
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Filing Dt:
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08/29/2000
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Title:
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DIFFERENTIAL, REDUCED SWING BUFFER DESIGN
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09652136
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Filing Dt:
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08/31/2000
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Title:
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NON-VOLATILE MEMORY DEVICE WITH ENCAPSULATED TUNGSTEN GATE AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09652742
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Filing Dt:
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08/31/2000
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Title:
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Method and apparatus for eliminating false data in a page mode memory device
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09652806
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Filing Dt:
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08/31/2000
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Title:
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METHOD AND SYSTEM FOR EFFICIENTLY TESTING CIRCUITRY
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09654831
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Filing Dt:
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09/01/2000
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Title:
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ARRANGEMENT FOR PROGRAMMING SELECTED DEVICE REGISTERS DURING INITIALIZATION FROM AN EXTERNAL MEMORY
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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09658597
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Filing Dt:
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09/11/2000
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Title:
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APPARATUS AND METHOD TO TEST HIGH SPEED DEVICES WITH A LOW SPEED TESTER
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09661356
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Filing Dt:
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09/14/2000
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Title:
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Output buffer for external voltage
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09663765
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Filing Dt:
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09/18/2000
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Title:
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VARIABLE SECTOR SIZE FOR A HIGH DENSITY FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09663909
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Filing Dt:
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09/18/2000
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Title:
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Address transition detector architecture for a high density flash memory device
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09664636
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Filing Dt:
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09/19/2000
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Title:
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Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09667347
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Filing Dt:
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09/22/2000
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Title:
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Serial sequencing of automatic program disturb erase verify during a fast erase mode
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Patent #:
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Issue Dt:
|
11/27/2001
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Application #:
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09667891
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Filing Dt:
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09/22/2000
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Title:
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Application of external voltage during array VT testing
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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09668801
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Filing Dt:
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09/22/2000
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Title:
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CIRCUIT AND METHOD FOR PROVIDING A PRECISE CLOCK FOR DATA COMMUNICATIONS
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09672122
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Filing Dt:
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09/27/2000
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Title:
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GAIN SWITCHING SCHEME FOR AMPLIFIERS WITH DIGITAL AUTOMATIC GAIN CONTROL
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09672396
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Filing Dt:
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09/28/2000
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Title:
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Method, circuit and/or architecture for reducing gate oxide stress in low-voltage regulated devices
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Patent #:
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Issue Dt:
|
06/29/2004
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Application #:
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09672836
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Filing Dt:
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09/29/2000
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Title:
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METHOD OF FORMING CONTACT OPENINGS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09675372
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Filing Dt:
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09/29/2000
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Title:
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POWER-SAVING MODES FOR MEMORIES
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09675895
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Filing Dt:
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09/29/2000
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Title:
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BITLINE/DATALINE SHORT SCHEME TO IMPROVE FALL-THROUGH TIMING IN A MULTI-PORT MEMORY
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Patent #:
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Issue Dt:
|
09/11/2001
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Application #:
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09675940
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Filing Dt:
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09/29/2000
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Title:
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Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider
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Patent #:
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Issue Dt:
|
11/09/2004
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Application #:
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09676169
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Filing Dt:
|
09/29/2000
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Title:
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LOGIC FOR PROVIDING ARBITRATION FOR SYNCHRONOUS DUAL-PORT MEMORY
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09676170
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Filing Dt:
|
09/29/2000
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Title:
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METHOD AND LOGIC FOR INITIALIZING THE FORWARD-POINTER MEMORY DURING NORMAL OPERATION OF THE DEVICE AS A BACKGROUND PROCESS
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Patent #:
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Issue Dt:
|
06/10/2003
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Application #:
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09676171
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Filing Dt:
|
09/29/2000
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Title:
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METHOD AND LOGIC FOR STORING AND EXTRACTING IN-BAND MULTICAST PORT INFORMATION STORED ALONG WITH THE DATA IN A SINGLE MEMORY WITHOUT MEMORY READ CYCLE OVERHEAD
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Patent #:
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Issue Dt:
|
11/19/2002
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Application #:
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09676539
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Filing Dt:
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09/29/2000
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Title:
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LOW VOLTAGE DIFFERENTIAL AMPLIFIER WITH HIGH VOLTAGE PROTECTION
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Patent #:
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Issue Dt:
|
10/07/2003
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Application #:
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09676705
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Filing Dt:
|
09/29/2000
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Title:
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LOGIC FOR INITIALIZING THE DEPTH OF THE QUEUE POINTER MEMORY
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Patent #:
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Issue Dt:
|
03/21/2006
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Application #:
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09676706
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Filing Dt:
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09/29/2000
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Title:
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LOGIC FOR GENERATING MULTICAST/UNICAST ADDRESS (ES)
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09676902
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Filing Dt:
|
10/02/2000
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Title:
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Architecture for a dual-bank page mode memory with redundancy
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Patent #:
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Issue Dt:
|
06/08/2004
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Application #:
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09677062
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Filing Dt:
|
09/29/2000
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Title:
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PLD CONFIGURATION PORT ARCHITECTURE AND LOGIC
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Patent #:
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Issue Dt:
|
05/13/2003
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Application #:
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09677255
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Filing Dt:
|
10/02/2000
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Title:
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METHOD AND APPARATUS FOR USING PROGRAMMABLE LOGIC DEVICE (PLD) LOGIC FOR DECOMPRESSION OF CONFIGURATION DATA
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Patent #:
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Issue Dt:
|
12/31/2002
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Application #:
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09684694
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Filing Dt:
|
10/04/2000
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Title:
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USING A LOW DRAIN BIAS DURING ERASE VERIFY TO ENSURE COMPLETE REMOVAL OF RESIDUAL CHARGE IN THE NITRIDE IN SONOS NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
|
03/25/2003
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Application #:
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09688504
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Filing Dt:
|
10/16/2000
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Title:
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PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
|
06/29/2004
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Application #:
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09688817
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Filing Dt:
|
10/17/2000
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|
Title:
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LOW TEMPERATURE METALLIZATION PROCESS
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Patent #:
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Issue Dt:
|
06/24/2003
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Application #:
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09688936
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Filing Dt:
|
10/16/2000
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Title:
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SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
|
04/16/2002
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Application #:
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09689036
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Filing Dt:
|
10/12/2000
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Title:
|
Two side decoding of a memory array
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Patent #:
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Issue Dt:
|
05/20/2003
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Application #:
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09689144
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Filing Dt:
|
10/11/2000
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|
Title:
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METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS AND DEVICE THEREBY FORMED
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|
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Patent #:
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|
Issue Dt:
|
06/15/2004
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Application #:
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09689442
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Filing Dt:
|
10/12/2000
|
|
Title:
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SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE HAVING AN IMPROVED WRITE SPEED
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
09689492
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Filing Dt:
|
10/12/2000
|
|
Title:
|
CLOCK GENERATOR WITH PROGRAMMABLE TWO-TONE MODULATION FOR EMI REDUCTION
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|
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|
Patent #:
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|
Issue Dt:
|
07/26/2005
|
Application #:
|
09689532
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Filing Dt:
|
10/12/2000
|
|
Title:
|
CIRCUIT FOR GENERATING SILICON ID FOR PLDS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09690294
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Filing Dt:
|
10/17/2000
|
|
Title:
|
Configurable memory block
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09693649
|
Filing Dt:
|
10/21/2000
|
|
Title:
|
FEEDBACK METHOD TO OPTIMIZE ELECTRIC FIELD DURING CHANNEL ERASE OF FLASH MEMORY DEVICES
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|
