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11/06/2001
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10/23/2000
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06/29/2004
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09696714
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10/25/2000
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12/18/2001
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09697813
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10/26/2000
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Title:
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Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
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02/04/2003
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09698485
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10/30/2000
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01/14/2003
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09698614
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10/27/2000
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04/04/2006
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10/30/2000
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ARCHITECTURE FOR EFFICIENT IMPLEMENTATION OF SERIAL DATA COMMUNICATION FUNCTIONS ON A PROGRAMMABLE LOGIC DEVICE (PLD)
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02/19/2002
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09706984
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11/06/2000
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Non-volatile inverter latch
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09/17/2002
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09707879
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11/08/2000
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GAIN VARIABLE AMPLIFIER
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08/21/2001
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09708982
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11/01/2000
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Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant
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02/17/2004
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09713390
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11/15/2000
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FLASH MEMORY CELL WITH MINIMIZED FLOATING GATE TO DRAIN/SOURCE OVERLAP FOR MINIMIZING CHARGE LEAKAGE
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09/23/2003
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09714441
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11/16/2000
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METHOD AND/OR ARCHITECTURE FOR IMPLEMENTING QUEUE EXPANSION IN MULTIQUEUE DEVICES
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09/06/2011
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09715437
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11/16/2000
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TRANSPORTABLE VOLUME, LOCAL ENVIRONMENT REPOSITORY
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09/03/2002
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09716526
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11/20/2000
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CIRCUIT TECHNIQUE FOR IMPROVED CURRENT MATCHING IN CHARGE PUMP PLLS
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10/23/2001
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09716659
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11/20/2000
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Double layer hard mask process to improve oxide quality for non-volatile flash memory products
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10/29/2002
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09718986
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11/22/2000
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METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR MEMORY DEVICE
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03/25/2003
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09721031
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11/22/2000
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STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
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02/04/2003
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09721316
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11/22/2000
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PROGRAMMABLE OSCILLATOR SCHEME
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06/11/2002
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09723494
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11/28/2000
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SWITCHED WELL TECHNIQUE FOR BIASING CROSS-COUPLED SWITCHES OR DRIVERS
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07/02/2002
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09725843
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11/30/2000
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08/23/2001
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Title:
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METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
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04/08/2003
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09727656
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11/30/2000
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ERASE VERIFY MODE TO EVALUATE NEGATIVE VT'S
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06/10/2003
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09728347
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12/01/2000
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POWER-SUPPLY-CONFIGURABLE OUTPUTS
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03/14/2006
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09728554
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12/01/2000
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DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES
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04/16/2002
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09730315
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12/05/2000
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VOLTAGE REGULATOR
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09/30/2003
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09732685
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12/08/2000
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FIFO READ INTERFACE PROTOCOL
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10/26/2004
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09732686
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12/08/2000
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FIFO READ INTERFACE PROTOCOL
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03/30/2004
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09732687
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12/08/2000
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OUT-OF-BAND LOOK-AHEAD ARBITRATION METHOD AND/OR ARCHITECTURE
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01/27/2004
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09733252
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12/07/2000
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RELIABILITY MONITOR FOR A MEMORY ARRAY
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12/10/2002
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09736648
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12/13/2000
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PROGRAMMABLE PIN FLAG
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11/26/2002
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09740106
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12/18/2000
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PROGRAMMABLE SWITCH
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06/10/2003
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09745658
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12/21/2000
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Title:
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CONFIGURABLE PCI CLAMP OR HIGH VOLTAGE TOLERANT I/O CIRCUIT
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Patent #:
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04/02/2002
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09745660
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12/21/2000
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Linearized digital phase-locked loop
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03/18/2003
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09746802
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03/12/2001
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LINEARIZED DIGITAL PHASE-LOCKED LOOP METHOD
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09/27/2005
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09747188
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12/22/2000
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LINEARIZED DIGITAL PHASE-LOCKED LOOP METHOD
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01/31/2006
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09747257
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12/22/2000
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Title:
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LINEARIZED DIGITAL PHASE-LOCKED LOOP
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03/23/2004
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09747262
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12/22/2000
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LINEARIZED DIGITAL PHASE-LOCKED LOOP
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07/09/2002
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09747281
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12/21/2000
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LINEARIZED DIGITAL PHASE-LOCKED LOOP METHOD
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03/26/2002
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09747790
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12/22/2000
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05/10/2001
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Title:
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Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
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10/15/2002
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09750608
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12/27/2000
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METHOD AND/OR APPARATUS FOR LOWERING POWER CONSUMPTION IN A PERIPHERAL DEVICE
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05/20/2003
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09751234
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12/27/2000
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PLD CONFIGURATION ARCHITECTURE
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02/06/2007
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09753011
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01/02/2001
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METHOD OF MAKING UNIFORM OXIDE LAYER
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05/13/2003
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09753137
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12/29/2000
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INTEGRATED SCHEME FOR PREDICTING YIELD OF SEMICONDUCTOR (MOS) DEVICES FROM DESIGNED LAYOUT
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NONE
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09756123
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01/09/2001
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11/22/2001
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Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process
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08/28/2001
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09759128
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01/11/2001
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05/24/2001
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Title:
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Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer
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03/18/2003
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09759925
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01/12/2001
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07/19/2001
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METHOD OF FORMING METAL LAYER(S) AND/OR ANTIREFLECTIVE COATING LAYER(S) ON AN INTEGRATED CIRCUIT
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NONE
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09764585
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01/17/2001
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08/23/2001
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Ferroelectric thin films and solutions: compositions and processing
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11/30/2004
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09766001
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01/19/2001
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10/25/2001
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INTERFACE APPARATUS
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10/01/2002
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09767341
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01/23/2001
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THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY
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08/10/2004
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09768348
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01/25/2001
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03/07/2002
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CACHE SYSTEM WITH LIMITED NUMBER OF TAG MEMORY ACCESSES
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08/24/2004
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09768873
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01/23/2001
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FORMING A SUBSTANTIALLY PLANAR UPPER SURFACE AT THE OUTER EDGE OF A SEMICONDUCTOR TOPOGRAPHY
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12/06/2005
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09768900
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01/24/2001
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N-WAY SIMULTANEOUS FRAMER FOR BIT-INTERLEAVED TIME DIVISION MULTIPLEXED (TDM) SERIAL BIT STREAMS
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01/18/2005
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09774323
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01/31/2001
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METHOD FOR IMPROVING DIELECTRIC POLISHING
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06/25/2002
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09774327
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01/31/2001
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06/28/2001
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FLASH MEMORY DEVICE WITH MONITOR STRUCTURE FOR MONITORING SECOND GATE OVER-ETCH
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Issue Dt:
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08/14/2001
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09774509
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Filing Dt:
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01/31/2001
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Title:
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Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
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Issue Dt:
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11/09/2004
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09775372
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02/01/2001
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Title:
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CONFIGURABLE FAST CLOCK DETECTION LOGIC WITH PROGRAMMABLE RESOLUTION
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Issue Dt:
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04/27/2004
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09777457
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02/06/2001
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Pub Dt:
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11/29/2001
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METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES
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06/06/2006
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09778233
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02/06/2001
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METHOD AND APPARATUS FOR AUTOMATIC DETECTION OF A SERIAL PERIPHERAL INTERFACE (SPI) DEVICE MEMORY SIZE
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09/09/2008
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09778837
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02/08/2001
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Pub Dt:
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09/20/2001
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ABNORMALITY DETECTION DEVICE FOR DETECTING AN ABNORMALITY IN A COMMUNICATION BUS
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07/09/2002
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09779225
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING USING GRADUATED STEPS FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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12/17/2002
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09779764
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02/08/2001
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CONCURRENT PROGRAM RECONNAISSANCE WITH PIGGYBACK PULSES FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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10/15/2002
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09779792
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Filing Dt:
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING USING TIMING CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Issue Dt:
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07/23/2002
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09779864
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02/08/2001
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Title:
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PROGRAM RECONNAISSANCE TO ELIMINATE VARIATIONS IN VT DISTRIBUTIONS OF MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Issue Dt:
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12/30/2003
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09779884
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING WITH STAIRCASE VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Issue Dt:
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05/14/2002
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09782482
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02/13/2001
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Title:
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CONFIGURABLE CLOCK GENERATOR
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09783496
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Filing Dt:
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02/13/2001
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES
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Issue Dt:
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07/15/2003
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09783716
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02/14/2001
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Title:
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METHOD OF UNIFORM POLISH IN SHALLOW TRENCH ISOLATION PROCESS
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Issue Dt:
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09/03/2002
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Application #:
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09784892
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Filing Dt:
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02/15/2001
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Title:
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METHOD FOR PRODUCING A SHALLOW TRENCH ISOLATION FILLED WITH THERMAL OXIDE
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Issue Dt:
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12/03/2002
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Application #:
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09788045
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Filing Dt:
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02/16/2001
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Title:
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METHOD OF FORMING A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-UM FLASH MEMORY TECHNOLOGY AND SEMICONDUCTOR DEVICE THEREBY FORMED
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Issue Dt:
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10/15/2002
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Application #:
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09788838
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Filing Dt:
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02/20/2001
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Title:
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MULTIPLEXERS FOR EFFICIENT PLD LOGIC BLOCKS
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09789052
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Filing Dt:
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02/20/2001
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Title:
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MULTIPLEXERS FOR EFFICIENT PLD LOGIC BLOCKS
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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09791355
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Filing Dt:
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02/23/2001
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Title:
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EMC ENHANCEMENT FOR DIFFERENTIAL DEVICES
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09791874
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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PROCESSOR CAPABLE OF ENABLING/DISABLING MEMORY ACCESS
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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09793359
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Filing Dt:
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02/26/2001
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Title:
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HIGH VOLTAGE SWITCH WITH NO LATCH-UP HAZARDS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09794479
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Filing Dt:
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02/26/2001
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Title:
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CONFIGURE REGISTERS AND LOADS TO TAILOR A MULTI-LEVEL CELL FLASH DESIGN
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09794480
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Filing Dt:
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02/26/2001
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Title:
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ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09794482
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Filing Dt:
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02/26/2001
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Title:
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STAIRCASE PROGRAM VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09796549
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Filing Dt:
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03/02/2001
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Publication #:
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Pub Dt:
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03/14/2002
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Title:
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ACTIVE LOAD CIRCUIT, AND OPERATIONAL AMPLIFIER AND COMPARATOR HAVING THE SAME
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09803400
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Filing Dt:
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09804523
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Filing Dt:
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03/12/2001
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Title:
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CONFIGURABLE DEDICATED LOGIC IN PLDS
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09808488
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Filing Dt:
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03/13/2001
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Title:
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OUTPUT BUFFER METHOD AND APPARATUS WITH ON RESISTANCE AND SKEW CONTROL
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09809208
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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12/20/2001
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Title:
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FRACTIONAL-N-PILL FREQUENCY SYNTHESIZER AND PHASE ERROR CANCELING METHOD THEREFOR
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09809221
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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PLL FREQUENCY SYNTHESIZER CIRCUIT
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09809242
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Filing Dt:
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03/15/2001
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Title:
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PARALLEL CONFIGURATION METHOD AND/OR ARCHITECTURE FOR PLDS OR FPGAS
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09811288
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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08/23/2001
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Title:
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Method for reduced gate aspect ratio to improve gap-fill after spacer etch
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09812109
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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CONFIGURABLE AND MEMORY ARCHITECTURE INDEPENDENT MEMORY BUILT-IN SELF TEST
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09812475
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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08/09/2001
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Title:
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UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE WITH SEQUENCER
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09816749
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Filing Dt:
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03/26/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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TRIMMING CIRCUIT OF SEMICONDUCTOR APPARATUS
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09817628
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Filing Dt:
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03/26/2001
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Title:
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FORMATION OF NON-VOLATILE MEMORY DEVICE COMPRISED OF AN ARRAY OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURES
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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09819592
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Filing Dt:
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03/27/2001
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Title:
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METHOD OF EMAIL ATTACHMENT CONFIRMATION
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09821006
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A UNIVERSAL SERIAL BUS DEVICE
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09821680
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Filing Dt:
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03/29/2001
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Title:
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METHOD AND APPARATUS FOR ACCURATELY READING A POTENTIOMETER
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09823414
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Filing Dt:
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03/31/2001
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Title:
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INTELLIGENT, EXTENSIBLE SIE PERIPHERAL DEVICE
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09823530
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Filing Dt:
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03/30/2001
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Title:
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METHOD FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09824841
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Filing Dt:
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04/02/2001
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Title:
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Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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09825027
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Filing Dt:
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04/02/2001
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Title:
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CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09825899
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Filing Dt:
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04/03/2001
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Title:
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CASCADABLE BUS BASED CROSSBAR SWITCH IN A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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09826998
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Filing Dt:
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04/03/2001
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Title:
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EXECUTABLE CODE DERIVED FROM USER-SELECTABLE LINKS EMBEDDED WITHIN THE COMMENTS PORTION OF A PROGRAM
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09828772
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Filing Dt:
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04/09/2001
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Title:
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BI-DIRECTIONAL ARCHITECTURE FOR A HIGH-VOLTAGE CROSS-COUPLED CHARGE PUMP
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09829510
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Filing Dt:
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04/09/2001
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Title:
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SRAM CELL DESIGN
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09833307
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Filing Dt:
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04/11/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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DUAL BIT ISOLATION SCHEME FOR FLASH MEMORY DEVICES HAVING POLYSILICON FLOATING GATES
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09834219
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Filing Dt:
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04/12/2001
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Title:
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I/O CELL ARCHITECTURE FOR CPLDS
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