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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:040038/0898   Pages: 16
Recorded: 09/14/2016
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 62
1
Patent #:
Issue Dt:
12/11/2007
Application #:
11195910
Filing Dt:
08/02/2005
Publication #:
Pub Dt:
02/08/2007
Title:
PROGRAMMABLE STRENGTH OUTPUT BUFFER FOR RDIMM ADDRESS REGISTER
2
Patent #:
NONE
Issue Dt:
Application #:
12132488
Filing Dt:
06/03/2008
Publication #:
Pub Dt:
12/03/2009
Title:
Method and Apparatus for Testing Write-Only Registers
3
Patent #:
Issue Dt:
11/25/2014
Application #:
12267355
Filing Dt:
11/07/2008
Publication #:
Pub Dt:
05/07/2009
Title:
Redriven/Retimed Registered Dual Inline Memory Module
4
Patent #:
Issue Dt:
07/31/2012
Application #:
12505344
Filing Dt:
07/17/2009
Publication #:
Pub Dt:
01/28/2010
Title:
HIGH SPEED MEMORY MODULE
5
Patent #:
Issue Dt:
09/25/2012
Application #:
12563308
Filing Dt:
09/21/2009
Title:
LOAD REDUCTION SYSTEM AND METHOD FOR DIMM-BASED MEMORY SYSTEMS
6
Patent #:
Issue Dt:
11/20/2012
Application #:
12611834
Filing Dt:
11/03/2009
Publication #:
Pub Dt:
05/05/2011
Title:
HIGH THROUGHPUT FLASH MEMORY SYSTEM
7
Patent #:
Issue Dt:
04/08/2014
Application #:
13359877
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
10/11/2012
Title:
MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES
8
Patent #:
Issue Dt:
04/08/2014
Application #:
13445143
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
10/18/2012
Title:
SYSTEMS AND METHODS FOR ERROR DETECTION AND CORRECTION IN A MEMORY MODULE WHICH INCLUDES A MEMORY BUFFER
9
Patent #:
Issue Dt:
04/29/2014
Application #:
13460307
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
11/15/2012
Title:
DRAM REFRESH METHOD AND SYSTEM
10
Patent #:
Issue Dt:
11/24/2015
Application #:
13530647
Filing Dt:
06/22/2012
Publication #:
Pub Dt:
12/27/2012
Title:
EXTENDED-HEIGHT DIMM
11
Patent #:
Issue Dt:
04/01/2014
Application #:
13558332
Filing Dt:
07/25/2012
Publication #:
Pub Dt:
01/31/2013
Title:
POWER MANAGEMENT IN SEMICONDUCTOR MEMORY SYSTEM
12
Patent #:
Issue Dt:
10/13/2015
Application #:
13587887
Filing Dt:
08/16/2012
Publication #:
Pub Dt:
06/20/2013
Title:
SELF TERMINATED DYNAMIC RANDOM ACCESS MEMORY
13
Patent #:
Issue Dt:
11/04/2014
Application #:
13619692
Filing Dt:
09/14/2012
Publication #:
Pub Dt:
03/21/2013
Title:
Methods and Apparatus for Transferring Data Between Memory Modules
14
Patent #:
NONE
Issue Dt:
Application #:
13620288
Filing Dt:
09/14/2012
Publication #:
Pub Dt:
04/10/2014
Title:
REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT
15
Patent #:
Issue Dt:
06/09/2015
Application #:
13653373
Filing Dt:
10/16/2012
Publication #:
Pub Dt:
05/23/2013
Title:
HIGH THROUGHPUT FLASH MEMORY SYSTEM
16
Patent #:
Issue Dt:
02/03/2015
Application #:
13768986
Filing Dt:
02/15/2013
Title:
HYBRID MEMORY BLADE
17
Patent #:
Issue Dt:
11/11/2014
Application #:
13778531
Filing Dt:
02/27/2013
Title:
COMPRESSION OF CONTENT ENTRIES IN STORAGE FOR REPLACING FAULTY MEMORY CELLS
18
Patent #:
Issue Dt:
03/03/2015
Application #:
13782348
Filing Dt:
03/01/2013
Publication #:
Pub Dt:
07/11/2013
Title:
REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT
19
Patent #:
Issue Dt:
01/05/2016
Application #:
13783155
Filing Dt:
03/01/2013
Title:
DISTRIBUTED HARDWARE TREE SEARCH METHODS AND APPARATUS FOR MEMORY DATA REPLACEMENT
20
Patent #:
Issue Dt:
01/19/2016
Application #:
13786325
Filing Dt:
03/05/2013
Title:
MEMORY TEST SEQUENCER
21
Patent #:
Issue Dt:
06/30/2015
Application #:
13787282
Filing Dt:
03/06/2013
Title:
MEMORY PARAMETRIC IMPROVEMENTS
22
Patent #:
Issue Dt:
01/05/2016
Application #:
13787350
Filing Dt:
03/06/2013
Title:
MEMORY PARAMETRIC IMPROVEMENTS
23
Patent #:
Issue Dt:
10/27/2015
Application #:
13791124
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
10/03/2013
Title:
MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION
24
Patent #:
Issue Dt:
11/24/2015
Application #:
13791161
Filing Dt:
03/08/2013
Title:
CONTENT MATCHING USING A MULTI-HASH FUNCTION FOR REPLACEMENT OF A FAULTY MEMORY CELL
25
Patent #:
Issue Dt:
08/04/2015
Application #:
13791792
Filing Dt:
03/08/2013
Title:
SINGLE CHIP MIXED MEMORY FOR DYNAMIC REPLACEMENT OF DRAM BAD CELL
26
Patent #:
Issue Dt:
12/02/2014
Application #:
13791807
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
07/18/2013
Title:
REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT
27
Patent #:
Issue Dt:
10/14/2014
Application #:
13791814
Filing Dt:
03/08/2013
Title:
METHOD OF USING NON-VOLATILE MEMORIES FOR ON-DIMM MEMORY ADDRESS LIST STORAGE
28
Patent #:
Issue Dt:
03/31/2015
Application #:
13797583
Filing Dt:
03/12/2013
Title:
VERTICAL ERROR CORRECTION CODE FOR DRAM MEMORY
29
Patent #:
Issue Dt:
02/24/2015
Application #:
13797623
Filing Dt:
03/12/2013
Title:
PROTOCOL CHECKING LOGIC CIRCUIT FOR MEMORY SYSTEM RELIABILITY
30
Patent #:
Issue Dt:
07/18/2017
Application #:
13797700
Filing Dt:
03/12/2013
Title:
SYSTEM AND METHOD FOR MEMORY ACCESS IN SERVER COMMUNICATIONS
31
Patent #:
Issue Dt:
10/07/2014
Application #:
13797814
Filing Dt:
03/12/2013
Title:
SYSTEM AND METHOD FOR MEMORY ACCESS IN SERVER COMMUNICATIONS
32
Patent #:
Issue Dt:
03/24/2015
Application #:
13909489
Filing Dt:
06/04/2013
Title:
EYE SCAN FOR ASYMMETRIC SHAPED COMMUNICATION SIGNAL
33
Patent #:
Issue Dt:
05/24/2016
Application #:
14175857
Filing Dt:
02/07/2014
Publication #:
Pub Dt:
09/18/2014
Title:
HIDDEN REFRESH OF WEAK MEMORY STORAGE CELLS IN SEMICONDUCTOR MEMORY
34
Patent #:
Issue Dt:
11/04/2014
Application #:
14178241
Filing Dt:
02/11/2014
Publication #:
Pub Dt:
06/12/2014
Title:
POWER MANAGEMENT IN SEMICONDUCTOR MEMORY SYSTEM
35
Patent #:
Issue Dt:
02/14/2017
Application #:
14181422
Filing Dt:
02/14/2014
Title:
ALTERNATE ACCESS TO DRAM DATA USING CYCLE STEALING
36
Patent #:
Issue Dt:
05/24/2016
Application #:
14194416
Filing Dt:
02/28/2014
Title:
MEMORY CENTRIC COMPUTING
37
Patent #:
Issue Dt:
02/02/2016
Application #:
14194574
Filing Dt:
02/28/2014
Title:
ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)
38
Patent #:
Issue Dt:
03/24/2015
Application #:
14228673
Filing Dt:
03/28/2014
Publication #:
Pub Dt:
07/31/2014
Title:
MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES
39
Patent #:
Issue Dt:
04/21/2015
Application #:
14228847
Filing Dt:
03/28/2014
Publication #:
Pub Dt:
07/31/2014
Title:
SYSTEMS AND METHODS FOR ERROR DETECTION AND CORRECTION IN A MEMORY MODULE WHICH INCLUDES A MEMORY BUFFER
40
Patent #:
Issue Dt:
09/22/2015
Application #:
14242292
Filing Dt:
04/01/2014
Publication #:
Pub Dt:
07/31/2014
Title:
DRAM REFRESH METHOD AND SYSTEM
41
Patent #:
Issue Dt:
09/01/2015
Application #:
14245991
Filing Dt:
04/04/2014
Title:
BACKWARD COMPATIBLE DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF TESTING THEREFOR
42
Patent #:
Issue Dt:
05/24/2016
Application #:
14316707
Filing Dt:
06/26/2014
Title:
MEMORY CONTROLLER SYSTEM WITH NON-VOLATILE BACKUP STORAGE
43
Patent #:
Issue Dt:
10/01/2019
Application #:
14444225
Filing Dt:
07/28/2014
Title:
MEMORY CONTROLLER SYSTEMS WITH NONVOLATILE MEMORY FOR STORING OPERATING PARAMETERS
44
Patent #:
Issue Dt:
01/19/2016
Application #:
14473872
Filing Dt:
08/29/2014
Publication #:
Pub Dt:
01/15/2015
Title:
METHOD OF USING NON-VOLATILE MEMORIES FOR ON-DIMM MEMORY ADDRESS LIST STORAGE
45
Patent #:
Issue Dt:
04/07/2015
Application #:
14527644
Filing Dt:
10/29/2014
Publication #:
Pub Dt:
02/19/2015
Title:
REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT
46
Patent #:
Issue Dt:
01/22/2019
Application #:
14536312
Filing Dt:
11/07/2014
Title:
NEAR-MEMORY COMPUTE MODULE
47
Patent #:
Issue Dt:
04/19/2016
Application #:
14593257
Filing Dt:
01/09/2015
Publication #:
Pub Dt:
04/30/2015
Title:
PROTOCOL CHECKING LOGIC CIRCUIT FOR MEMORY SYSTEM RELIABILITY
48
Patent #:
Issue Dt:
04/26/2016
Application #:
14665968
Filing Dt:
03/23/2015
Publication #:
Pub Dt:
09/17/2015
Title:
MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES
49
Patent #:
Issue Dt:
12/12/2017
Application #:
14706886
Filing Dt:
05/07/2015
Title:
METHOD AND SYSTEM USING MEMORY CHANNEL LOAD SHARING
50
Patent #:
Issue Dt:
02/14/2017
Application #:
14798340
Filing Dt:
07/13/2015
Title:
DYNAMIC UPDATE TECHNIQUE FOR PHASE INTERPOLATOR DEVICE AND METHOD THEREFOR
51
Patent #:
Issue Dt:
02/07/2017
Application #:
14861079
Filing Dt:
09/22/2015
Title:
METHOD AND CIRCUIT FOR DELAY ADJUSTMENT MONOTONICITY IN A DELAY LINE
52
Patent #:
Issue Dt:
07/24/2018
Application #:
14883155
Filing Dt:
10/14/2015
Title:
HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE
53
Patent #:
Issue Dt:
03/26/2019
Application #:
14884496
Filing Dt:
10/15/2015
Title:
HYBRID MEMORY MODULE WITH IMPROVED INTER-MEMORY DATA TRANSMISSION PATH
54
Patent #:
Issue Dt:
02/05/2019
Application #:
14885031
Filing Dt:
10/16/2015
Title:
BUFFERING DEVICE WITH STATUS COMMUNICATION METHOD FOR MEMORY CONTROLLER
55
Patent #:
Issue Dt:
05/15/2018
Application #:
14923345
Filing Dt:
10/26/2015
Publication #:
Pub Dt:
07/28/2016
Title:
MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION
56
Patent #:
Issue Dt:
08/29/2017
Application #:
14951377
Filing Dt:
11/24/2015
Publication #:
Pub Dt:
05/12/2016
Title:
EXTENDED-HEIGHT DIMM
57
Patent #:
Issue Dt:
10/10/2017
Application #:
14963098
Filing Dt:
12/08/2015
Title:
PERSISTENT MEMORY DESCRIPTOR
58
Patent #:
NONE
Issue Dt:
Application #:
14975273
Filing Dt:
12/18/2015
Publication #:
Pub Dt:
04/21/2016
Title:
ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)
59
Patent #:
Issue Dt:
01/03/2017
Application #:
14989323
Filing Dt:
01/06/2016
Title:
PHASE INTERPOLATOR DEVICE USING DYNAMIC STOP AND PHASE CODE UPDATE AND METHOD THEREFOR
60
Patent #:
Issue Dt:
02/21/2017
Application #:
15137467
Filing Dt:
04/25/2016
Publication #:
Pub Dt:
08/18/2016
Title:
MEMORY CONTROLLER SYSTEM WITH NON-VOLATILE BACKUP STORAGE
61
Patent #:
Issue Dt:
03/06/2018
Application #:
15137802
Filing Dt:
04/25/2016
Publication #:
Pub Dt:
08/18/2016
Title:
MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES
62
Patent #:
Issue Dt:
04/17/2018
Application #:
15156691
Filing Dt:
05/17/2016
Publication #:
Pub Dt:
04/20/2017
Title:
HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE
Assignor
1
Exec Dt:
08/04/2016
Assignee
1
1050 ENTERPRISE WAY
SUITE 700
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
WILSON SONSINI GOODRICH & ROSATI
650 PAGE MILL ROAD
PALO ALTO, CA 94304-1050

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