Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 040413/0485 | |
| Pages: | 4 |
| | Recorded: | 11/23/2016 | | |
| Attorney Dkt #: | 04359D 05222D 04897D |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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11782587
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Filing Dt:
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07/24/2007
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FORMING AN INSULATING LAYER WITH A HARD SHEET BURIED THEREIN
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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11880162
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Filing Dt:
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07/20/2007
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Publication #:
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Pub Dt:
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11/15/2007
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Title:
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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCORPORATING A SEMICONDUCTOR CONSTRUCTING BODY AND AN INTERCONNECTING LAYER WHICH IS CONNECTED TO A GROUND LAYER VIA A VERTICAL CONDUCTING PORTION
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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12047228
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Filing Dt:
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03/12/2008
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Publication #:
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Pub Dt:
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07/10/2008
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Title:
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SEMICONDUCTOR PACKAGE INCLUDING CONNECTED UPPER AND LOWER INTERCONNECTIONS, AND MANUFACTURING METHOD THEREOF
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Assignees
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| 6-2, HON-MACHI 1-CHOME |
| SHIBUYA-KU |
| TOKYO, JAPAN 151-8543 |
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| 5-1, NISHISHINJUKU 6-CHOME |
| SHINJUKU-KU |
| TOKYO, JAPAN 1631388 |
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Correspondence name and address
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HOLTZ, HOLTZ & VOLEK PC
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630 NINTH AVENUE
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SUITE 1010
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NEW YORK, NY 10036
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