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Reel/Frame:040454/0913   Pages: 7
Recorded: 11/29/2016
Attorney Dkt #:24061.2475US03
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
05/26/2020
Application #:
15357203
Filing Dt:
11/21/2016
Publication #:
Pub Dt:
03/09/2017
Title:
Spacer Etching Process for Integrated Circuit Design
Assignors
1
Exec Dt:
10/18/2013
2
Exec Dt:
10/18/2013
3
Exec Dt:
10/18/2013
4
Exec Dt:
10/21/2013
5
Exec Dt:
10/21/2013
6
Exec Dt:
10/24/2013
7
Exec Dt:
10/22/2013
8
Exec Dt:
10/22/2013
9
Exec Dt:
10/24/2013
10
Exec Dt:
10/23/2013
11
Exec Dt:
10/22/2013
12
Exec Dt:
10/22/2013
Assignee
1
NO. 8, LI-HSIN RD. 6
SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU, TAIWAN 300-77
Correspondence name and address
HAYNES AND BOONE, LLP IP SECTION
2323 VICTORY AVENUE
SUITE 700
DALLAS, TX 75219

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