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Patent Assignment Details
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Reel/Frame:040516/0793   Pages: 2
Recorded: 12/05/2016
Attorney Dkt #:252011-9010
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 4
1
Patent #:
Issue Dt:
10/30/2012
Application #:
12955657
Filing Dt:
11/29/2010
Publication #:
Pub Dt:
03/29/2012
Title:
RESISTIVE RANDOM ACCESS MEMORY AND VERIFYING METHOD THEREOF
2
Patent #:
Issue Dt:
04/29/2014
Application #:
13338264
Filing Dt:
12/28/2011
Publication #:
Pub Dt:
07/04/2013
Title:
RESISTIVE RANDOM ACCESS MEMORY CELL AND RESISTIVE RANDOM ACCESS MEMORY MODULE
3
Patent #:
Issue Dt:
09/02/2014
Application #:
13645493
Filing Dt:
10/04/2012
Publication #:
Pub Dt:
02/06/2014
Title:
LOGIC GATE
4
Patent #:
Issue Dt:
10/28/2014
Application #:
13872168
Filing Dt:
04/29/2013
Publication #:
Pub Dt:
07/31/2014
Title:
CONFIGURABLE LOGIC BLOCK AND OPERATION METHOD THEREOF
Assignor
1
Exec Dt:
11/09/2016
Assignee
1
NO. 8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
MCCLURE, QUALEY & RODACK, LLP
3100 INTERSTATE NORTH CIRCLE
SUITE 150
ATLANTA, GA 30339

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