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Reel/Frame:040908/0979   Pages: 11
Recorded: 12/14/2016
Attorney Dkt #:Q4-CSC-MRL
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 64
1
Patent #:
Issue Dt:
02/22/2000
Application #:
08970520
Filing Dt:
11/14/1997
Title:
MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
2
Patent #:
Issue Dt:
05/08/2001
Application #:
08993149
Filing Dt:
12/18/1997
Title:
METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
3
Patent #:
Issue Dt:
04/03/2001
Application #:
09353781
Filing Dt:
07/15/1999
Title:
SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
4
Patent #:
Issue Dt:
02/06/2001
Application #:
09465724
Filing Dt:
12/17/1999
Title:
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
5
Patent #:
Issue Dt:
07/16/2002
Application #:
09502163
Filing Dt:
02/11/2000
Title:
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
6
Patent #:
Issue Dt:
01/27/2004
Application #:
09504087
Filing Dt:
02/15/2000
Title:
INTEGRATED CIRCUIT HAVING INCREASED GATE COUPLING CAPACITANCE
7
Patent #:
Issue Dt:
02/26/2002
Application #:
09533057
Filing Dt:
03/22/2000
Title:
High voltage transistor with modified field implant mask
8
Patent #:
Issue Dt:
08/13/2002
Application #:
09535255
Filing Dt:
03/23/2000
Title:
METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
9
Patent #:
Issue Dt:
02/12/2002
Application #:
09538168
Filing Dt:
03/30/2000
Title:
Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
10
Patent #:
Issue Dt:
09/10/2002
Application #:
09539307
Filing Dt:
03/30/2000
Title:
METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR DEVICE
11
Patent #:
Issue Dt:
03/18/2003
Application #:
09548616
Filing Dt:
04/13/2000
Title:
METHOD OF HIGH DENSITY PLASMA METAL ETCHING
12
Patent #:
Issue Dt:
04/02/2002
Application #:
09563024
Filing Dt:
05/02/2000
Title:
Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch
13
Patent #:
Issue Dt:
09/25/2001
Application #:
09586254
Filing Dt:
05/31/2000
Title:
Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
14
Patent #:
Issue Dt:
04/30/2002
Application #:
09588119
Filing Dt:
05/31/2000
Title:
METHOD FOR CREATING PARTIALLY UV TRANSPARENT ANTI-REFLECTIVE COATING FOR SEMICONDUCTORS
15
Patent #:
Issue Dt:
04/23/2002
Application #:
09627584
Filing Dt:
07/28/2000
Title:
Optimization of thermal cycle for the formation of pocket implants
16
Patent #:
Issue Dt:
07/09/2002
Application #:
09651684
Filing Dt:
08/30/2000
Title:
Semiconductor structure
17
Patent #:
Issue Dt:
06/26/2001
Application #:
09663121
Filing Dt:
09/15/2000
Title:
Reference cell configuration for a 1T/1C ferroelectric memory
18
Patent #:
Issue Dt:
03/04/2003
Application #:
09665916
Filing Dt:
09/20/2000
Title:
NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER
19
Patent #:
Issue Dt:
01/14/2003
Application #:
09667686
Filing Dt:
09/22/2000
Title:
MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH
20
Patent #:
Issue Dt:
01/28/2003
Application #:
09681314
Filing Dt:
03/16/2001
Publication #:
Pub Dt:
09/19/2002
Title:
NAND STACK EEPROM WITH RANDOM PROGRAMMING CAPABILITY
21
Patent #:
Issue Dt:
08/07/2001
Application #:
09685968
Filing Dt:
10/10/2000
Title:
Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
22
Patent #:
Issue Dt:
11/19/2002
Application #:
09685972
Filing Dt:
10/10/2000
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS USING DECOUPLED LOCAL INTERCONNECT PROCESS
23
Patent #:
Issue Dt:
03/25/2003
Application #:
09691643
Filing Dt:
10/18/2000
Title:
METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
24
Patent #:
Issue Dt:
12/31/2002
Application #:
09699531
Filing Dt:
10/30/2000
Title:
METHOD FOR SELECTIVE REMOVAL OF ONO LAYER
25
Patent #:
Issue Dt:
10/22/2002
Application #:
09703151
Filing Dt:
10/30/2000
Title:
COMPACT NONVOLATILE CIRCUIT HAVING MARGIN TESTING CAPABILITY
26
Patent #:
Issue Dt:
05/06/2003
Application #:
09764223
Filing Dt:
01/16/2001
Publication #:
Pub Dt:
10/25/2001
Title:
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
27
Patent #:
Issue Dt:
10/23/2001
Application #:
09799469
Filing Dt:
03/05/2001
Title:
Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
28
Patent #:
Issue Dt:
09/30/2003
Application #:
09805287
Filing Dt:
03/13/2001
Title:
METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE
29
Patent #:
Issue Dt:
04/29/2003
Application #:
09871172
Filing Dt:
05/31/2001
Title:
NON-VOLATILE STATIC MEMORY CELL
30
Patent #:
Issue Dt:
01/21/2003
Application #:
09875073
Filing Dt:
06/05/2001
Title:
METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
31
Patent #:
Issue Dt:
06/03/2003
Application #:
09884204
Filing Dt:
06/19/2001
Title:
METHOD OF FORMING ZERO MARKS
32
Patent #:
Issue Dt:
05/04/2004
Application #:
10017832
Filing Dt:
12/12/2001
Title:
METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET
33
Patent #:
Issue Dt:
02/04/2003
Application #:
10044510
Filing Dt:
01/11/2002
Title:
METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK
34
Patent #:
Issue Dt:
10/26/2004
Application #:
10045354
Filing Dt:
11/07/2001
Title:
INNOVATIVE METHOD OF HARD MASK REMOVAL
35
Patent #:
Issue Dt:
04/15/2003
Application #:
10067765
Filing Dt:
02/08/2002
Publication #:
Pub Dt:
06/13/2002
Title:
PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION
36
Patent #:
Issue Dt:
11/05/2002
Application #:
10109526
Filing Dt:
03/27/2002
Title:
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
37
Patent #:
Issue Dt:
12/27/2005
Application #:
10112572
Filing Dt:
03/29/2002
Title:
CONTACT STRUCTURE AND METHOD OF MAKING THE SAME
38
Patent #:
Issue Dt:
10/19/2004
Application #:
10120116
Filing Dt:
04/09/2002
Title:
ISOLATION TRENCH FILL PROCESS
39
Patent #:
Issue Dt:
02/10/2004
Application #:
10126841
Filing Dt:
04/19/2002
Title:
REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
40
Patent #:
Issue Dt:
08/19/2003
Application #:
10165837
Filing Dt:
06/06/2002
Title:
HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
41
Patent #:
Issue Dt:
09/28/2004
Application #:
10305889
Filing Dt:
11/26/2002
Publication #:
Pub Dt:
05/27/2004
Title:
MOCVD FORMATION OF CU2S
42
Patent #:
Issue Dt:
07/20/2004
Application #:
10327094
Filing Dt:
12/24/2002
Publication #:
Pub Dt:
07/10/2003
Title:
PULSE WIDTH DETECTION CIRCUIT FILTERING THE INPUT SIGNAL AND GENERATING A BINARY SIGNAL
43
Patent #:
Issue Dt:
10/11/2005
Application #:
10358756
Filing Dt:
02/05/2003
Title:
REDUCED SILICON GOUGING AND COMMON SOURCE LINE RESISTANCE IN SEMICONDUCTOR DEVICES
44
Patent #:
Issue Dt:
02/15/2005
Application #:
10389276
Filing Dt:
03/13/2003
Publication #:
Pub Dt:
11/13/2003
Title:
COLUMN DECODER CONFIGURATION FOR A 1T/1C MEMORY
45
Patent #:
Issue Dt:
09/07/2004
Application #:
10418174
Filing Dt:
04/18/2003
Publication #:
Pub Dt:
10/23/2003
Title:
AMPLIFICATION CIRCUIT AND OPTICAL COMMUNICATION APPARATUS PROVIDED WITH THE AMPLIFICATION CIRCUIT
46
Patent #:
Issue Dt:
09/04/2007
Application #:
10799413
Filing Dt:
03/12/2004
Title:
AVOIDING FIELD OXIDE GOUGING IN SHALLOW TRENCH ISOLATION (STI) REGIONS
47
Patent #:
NONE
Issue Dt:
Application #:
10850395
Filing Dt:
05/21/2004
Publication #:
Pub Dt:
11/04/2004
Title:
DC component cancellation circuit
48
Patent #:
Issue Dt:
04/22/2008
Application #:
10934923
Filing Dt:
09/02/2004
Title:
SEMICONDUCTOR CONTACT AND NITRIDE SPACER FORMATION SYSTEM AND METHOD
49
Patent #:
NONE
Issue Dt:
Application #:
10993202
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
06/09/2005
Title:
Reference cell configuration for a 1T/1C ferroelectric memory
50
Patent #:
Issue Dt:
02/17/2009
Application #:
11086310
Filing Dt:
03/23/2005
Publication #:
Pub Dt:
09/28/2006
Title:
HIGH K STACK FOR NON-VOLATILE MEMORY
51
Patent #:
Issue Dt:
05/13/2008
Application #:
11122123
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
07/13/2006
Title:
SIGNAL DETECTION METHOD, FREQUENCY DETECTION METHOD, POWER CONSUMPTION CONTROL METHOD, SIGNAL DETECTING DEVICE, FREQUENCY DETECTING DEVICE, POWER CONSUMPTION CONTROL DEVICE AND ELECTRONIC APPARATUS
52
Patent #:
Issue Dt:
06/29/2010
Application #:
11138823
Filing Dt:
05/26/2005
Title:
IMPEDANCE BUFFER AND METHOD
53
Patent #:
Issue Dt:
07/12/2011
Application #:
11168448
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
10/05/2006
Title:
MICROCONTROLLER
54
Patent #:
Issue Dt:
09/20/2011
Application #:
11169747
Filing Dt:
06/30/2005
Publication #:
Pub Dt:
09/28/2006
Title:
COMMUNICATION DATA CONTROLLER
55
Patent #:
Issue Dt:
01/01/2008
Application #:
11494620
Filing Dt:
07/28/2006
Title:
PULSE WIDTH MODULATION CIRCUIT
56
Patent #:
Issue Dt:
01/20/2009
Application #:
11540831
Filing Dt:
09/28/2006
Title:
VARIABLE IMPEDANCE SENSE ARCHITECTURE AND METHOD
57
Patent #:
Issue Dt:
06/10/2008
Application #:
11644196
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
02/21/2008
Title:
NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH REGULATED ERASE SATURATION AND PROGRAM WINDOW
58
Patent #:
NONE
Issue Dt:
Application #:
11781551
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
11/15/2007
Title:
DEVICE HAVING A PROTECTIVE CAP FORMED OVER AN ANTI-REFLECTIVE COATING LAYER AND OVER AN INSULATING MATERIAL
59
Patent #:
Issue Dt:
08/17/2010
Application #:
12006224
Filing Dt:
12/31/2007
Publication #:
Pub Dt:
07/02/2009
Title:
DUMMY CELL FOR MEMORY CIRCUITS
60
Patent #:
Issue Dt:
11/22/2011
Application #:
12006226
Filing Dt:
12/31/2007
Publication #:
Pub Dt:
07/02/2009
Title:
ARCHITECTURE OF A NVDRAM ARRAY AND ITS SENSE REGIME
61
Patent #:
Issue Dt:
11/15/2011
Application #:
12006227
Filing Dt:
12/31/2007
Publication #:
Pub Dt:
07/02/2009
Title:
3T HIGH DENSITY NVDRAM CELL
62
Patent #:
Issue Dt:
12/13/2011
Application #:
12043506
Filing Dt:
03/06/2008
Publication #:
Pub Dt:
09/11/2008
Title:
POWER SUPPLY VOLTAGE REGULATOR CIRCUIT AND MICROCOMPUTER
63
Patent #:
Issue Dt:
12/28/2010
Application #:
12059560
Filing Dt:
03/31/2008
Title:
CIRCUIT AND METHOD TO INCREASE READ MARGIN IN NON-VOLATILE MEMORIES USING A DIFFERENTIAL SENSING CIRCUIT
64
Patent #:
Issue Dt:
09/18/2012
Application #:
12154584
Filing Dt:
05/22/2008
Publication #:
Pub Dt:
11/27/2008
Title:
FLOATING GATE MEMORY DEVICE WITH INCREASED COUPLING COEFFICIENT
Assignor
1
Exec Dt:
12/09/2016
Assignee
1
3945 FREEDOM CIRCLE
SUITE 900
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
LONGITUDE LICENSING LTD
1ST FLOOR, EUROPA HOUSE,
HARCOURT CENTRE, HARCOURT STREET
DUBLIN 2, D02 WR20 IRELAND

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