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64
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Issue Dt:
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02/22/2000
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Application #:
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08970520
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Filing Dt:
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11/14/1997
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Title:
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MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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08993149
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Filing Dt:
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12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09353781
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Filing Dt:
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07/15/1999
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Title:
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SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09465724
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Filing Dt:
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12/17/1999
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Title:
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PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09502163
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Filing Dt:
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02/11/2000
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Title:
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SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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09504087
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Filing Dt:
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02/15/2000
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Title:
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INTEGRATED CIRCUIT HAVING INCREASED GATE COUPLING CAPACITANCE
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09533057
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Filing Dt:
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03/22/2000
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Title:
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High voltage transistor with modified field implant mask
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Patent #:
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Issue Dt:
|
08/13/2002
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Application #:
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09535255
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Filing Dt:
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03/23/2000
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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Patent #:
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Issue Dt:
|
02/12/2002
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Application #:
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09538168
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Filing Dt:
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03/30/2000
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Title:
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Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
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Patent #:
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Issue Dt:
|
09/10/2002
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Application #:
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09539307
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Filing Dt:
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03/30/2000
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Title:
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METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09548616
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Filing Dt:
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04/13/2000
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Title:
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METHOD OF HIGH DENSITY PLASMA METAL ETCHING
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Patent #:
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Issue Dt:
|
04/02/2002
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Application #:
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09563024
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Filing Dt:
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05/02/2000
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Title:
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Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch
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Patent #:
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Issue Dt:
|
09/25/2001
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Application #:
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09586254
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Filing Dt:
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05/31/2000
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Title:
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Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09588119
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Filing Dt:
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05/31/2000
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Title:
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METHOD FOR CREATING PARTIALLY UV TRANSPARENT ANTI-REFLECTIVE COATING FOR SEMICONDUCTORS
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Patent #:
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Issue Dt:
|
04/23/2002
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Application #:
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09627584
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Filing Dt:
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07/28/2000
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Title:
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Optimization of thermal cycle for the formation of pocket implants
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Patent #:
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Issue Dt:
|
07/09/2002
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Application #:
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09651684
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Filing Dt:
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08/30/2000
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Title:
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Semiconductor structure
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09663121
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Filing Dt:
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09/15/2000
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Title:
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Reference cell configuration for a 1T/1C ferroelectric memory
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09665916
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Filing Dt:
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09/20/2000
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Title:
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NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09667686
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Filing Dt:
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09/22/2000
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Title:
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MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09681314
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
Title:
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NAND STACK EEPROM WITH RANDOM PROGRAMMING CAPABILITY
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09685968
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Filing Dt:
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10/10/2000
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Title:
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Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09685972
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Filing Dt:
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10/10/2000
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Title:
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METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS USING DECOUPLED LOCAL INTERCONNECT PROCESS
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09691643
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Filing Dt:
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10/18/2000
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Title:
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METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09699531
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Filing Dt:
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10/30/2000
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Title:
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METHOD FOR SELECTIVE REMOVAL OF ONO LAYER
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09703151
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Filing Dt:
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10/30/2000
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Title:
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COMPACT NONVOLATILE CIRCUIT HAVING MARGIN TESTING CAPABILITY
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Patent #:
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05/06/2003
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Application #:
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09764223
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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10/25/2001
| | | | |
Title:
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SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09799469
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Filing Dt:
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03/05/2001
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Title:
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Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09805287
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Filing Dt:
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03/13/2001
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Title:
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METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09871172
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Filing Dt:
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05/31/2001
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Title:
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NON-VOLATILE STATIC MEMORY CELL
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Patent #:
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01/21/2003
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09875073
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06/05/2001
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Title:
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METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
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Patent #:
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06/03/2003
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09884204
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06/19/2001
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Title:
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METHOD OF FORMING ZERO MARKS
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05/04/2004
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10017832
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12/12/2001
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Title:
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METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET
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02/04/2003
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10044510
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01/11/2002
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Title:
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METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK
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10/26/2004
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10045354
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11/07/2001
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Title:
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INNOVATIVE METHOD OF HARD MASK REMOVAL
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04/15/2003
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10067765
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02/08/2002
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Pub Dt:
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06/13/2002
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Title:
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PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION
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11/05/2002
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10109526
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03/27/2002
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Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
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12/27/2005
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10112572
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03/29/2002
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Title:
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CONTACT STRUCTURE AND METHOD OF MAKING THE SAME
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10/19/2004
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10120116
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04/09/2002
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Title:
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ISOLATION TRENCH FILL PROCESS
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02/10/2004
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10126841
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04/19/2002
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Title:
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REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
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08/19/2003
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10165837
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06/06/2002
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Title:
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HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
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09/28/2004
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10305889
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11/26/2002
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05/27/2004
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Title:
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MOCVD FORMATION OF CU2S
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07/20/2004
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10327094
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12/24/2002
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07/10/2003
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Title:
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PULSE WIDTH DETECTION CIRCUIT FILTERING THE INPUT SIGNAL AND GENERATING A BINARY SIGNAL
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10/11/2005
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10358756
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02/05/2003
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REDUCED SILICON GOUGING AND COMMON SOURCE LINE RESISTANCE IN SEMICONDUCTOR DEVICES
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02/15/2005
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10389276
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03/13/2003
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11/13/2003
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COLUMN DECODER CONFIGURATION FOR A 1T/1C MEMORY
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09/07/2004
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10418174
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04/18/2003
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10/23/2003
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AMPLIFICATION CIRCUIT AND OPTICAL COMMUNICATION APPARATUS PROVIDED WITH THE AMPLIFICATION CIRCUIT
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09/04/2007
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10799413
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03/12/2004
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AVOIDING FIELD OXIDE GOUGING IN SHALLOW TRENCH ISOLATION (STI) REGIONS
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NONE
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10850395
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05/21/2004
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11/04/2004
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DC component cancellation circuit
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04/22/2008
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10934923
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09/02/2004
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SEMICONDUCTOR CONTACT AND NITRIDE SPACER FORMATION SYSTEM AND METHOD
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NONE
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10993202
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11/18/2004
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06/09/2005
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Reference cell configuration for a 1T/1C ferroelectric memory
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02/17/2009
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11086310
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03/23/2005
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09/28/2006
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HIGH K STACK FOR NON-VOLATILE MEMORY
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05/13/2008
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11122123
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05/05/2005
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07/13/2006
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Title:
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SIGNAL DETECTION METHOD, FREQUENCY DETECTION METHOD, POWER CONSUMPTION CONTROL METHOD, SIGNAL DETECTING DEVICE, FREQUENCY DETECTING DEVICE, POWER CONSUMPTION CONTROL DEVICE AND ELECTRONIC APPARATUS
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06/29/2010
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05/26/2005
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07/12/2011
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06/29/2005
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10/05/2006
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MICROCONTROLLER
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09/20/2011
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06/30/2005
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09/28/2006
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COMMUNICATION DATA CONTROLLER
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01/01/2008
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07/28/2006
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01/20/2009
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09/28/2006
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06/10/2008
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12/22/2006
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02/21/2008
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NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH REGULATED ERASE SATURATION AND PROGRAM WINDOW
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NONE
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07/23/2007
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11/15/2007
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DEVICE HAVING A PROTECTIVE CAP FORMED OVER AN ANTI-REFLECTIVE COATING LAYER AND OVER AN INSULATING MATERIAL
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08/17/2010
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07/02/2009
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11/22/2011
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12/31/2007
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07/02/2009
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ARCHITECTURE OF A NVDRAM ARRAY AND ITS SENSE REGIME
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11/15/2011
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12/31/2007
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07/02/2009
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12/13/2011
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03/06/2008
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09/11/2008
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POWER SUPPLY VOLTAGE REGULATOR CIRCUIT AND MICROCOMPUTER
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12/28/2010
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CIRCUIT AND METHOD TO INCREASE READ MARGIN IN NON-VOLATILE MEMORIES USING A DIFFERENTIAL SENSING CIRCUIT
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09/18/2012
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11/27/2008
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FLOATING GATE MEMORY DEVICE WITH INCREASED COUPLING COEFFICIENT
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