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|
|
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Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
08915370
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
SYSTEM AND METHOD FOR UPDATING THE DATA STORED IN A CACHE MEMORY ATTACHED TO AN INPUT/OUTPUT SYSTEM
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|
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|
Patent #:
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|
Issue Dt:
|
05/02/2000
|
Application #:
|
08915984
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
REDUNDANCY SCHEME PROVIDING IMPROVEMENTS IN REDUNDANT CIRCUIT ACCESS TIME AND INTEGRATED CIRCUIT LAYOUT AREA
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|
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|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08917149
|
Filing Dt:
|
08/25/1997
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|
Title:
|
REDUCTION OF CHARGE LOSS IN NONVOLATILE MEMORY CELLS BY PHOSPHORUS IMPLANTATION INTO PECVD NITRIDE/OXYNITRIDE FILMS
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|
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Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08920200
|
Filing Dt:
|
08/25/1997
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|
Title:
|
CIRCUIT AND METHOD FOR MEASURING THE DIFFERENCE FREQUENCY BETWEEN TWO CLOCKS
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|
|
|
Patent #:
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|
Issue Dt:
|
03/14/2000
|
Application #:
|
08920539
|
Filing Dt:
|
08/27/1997
|
|
Title:
|
MECHANISM FOR DETECTING PARTICULATE FORMATION AND/OR FAILURES IN THE REMOVAL OF GAS FROM A LIQUID
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08926611
|
Filing Dt:
|
09/10/1997
|
|
Title:
|
NON-VOLATILE RANDOM ACCESS MEMORY AND METHODS FOR MAKING AND CONFIGURING SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
08929308
|
Filing Dt:
|
09/03/1997
|
|
Title:
|
METHOD AND STRUCTURE FOR A SINGLE-SIDED NON-SELF-ALIGNED TRANSISTOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08931989
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
SCAN PATH CIRCUITRY FOR PROGRAMMING A VARIABLE CLOCK PULSE WIDTH
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08932315
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
SCAN PATH CIRCUITRY INCLUDING A PROGRAMMABLE DELAY CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08932637
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
TEST MODE FEATURES FOR SYNCHRONOUS PIPELINED MEMORIES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/14/1999
|
Application #:
|
08932638
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
SCAN PATH CIRCUITRY INCLUDING AN OUTPUT REGISTER HAVING A FLOW THROUGH MODE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/14/1999
|
Application #:
|
08933139
|
Filing Dt:
|
09/18/1997
|
|
Title:
|
VOLTAGE LEVEL INTERFACE CIRCUIT WITH SET UP AND HOLD CONTROL
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|
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|
Patent #:
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|
Issue Dt:
|
03/19/2002
|
Application #:
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08933562
|
Filing Dt:
|
09/19/1997
|
|
Title:
|
METHOD AND APPARATUS TO PREVENT LATCH-UP IN CMOS DEVICES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/18/1999
|
Application #:
|
08934805
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHODS, CIRCUITS AND DEVICES FOR IMPROVING CROSSOVER PERFORMANCE AND/OR MONOTONICITY, AND APPLICATIONS OF THE SAME IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/15/1999
|
Application #:
|
08934933
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHODS, CIRCUITS AND DEVICES FOR IMPROVING CROSSOVER PERFORMANCE AND/OR MONOTONICITY, AND APPLICATIONS OF THE SAME IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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|
|
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|
Patent #:
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|
Issue Dt:
|
07/27/1999
|
Application #:
|
08935350
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHODS, CIRCUITS AND DEVICES FOR REDUCING AND/OR IMPROVING CROSSOVER PERFORMANCE AND/OR MONOTONICITY, AND APPLICATIONS OF THE SAME IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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|
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|
Patent #:
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|
Issue Dt:
|
12/26/2000
|
Application #:
|
08935705
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Filing Dt:
|
09/23/1997
|
|
Title:
|
PLASMA ETCHING METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08937597
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
VOLTAGE THRESHOLD DETECTION CIRCUIT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/16/1999
|
Application #:
|
08938292
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Filing Dt:
|
09/26/1997
|
|
Title:
|
SELECTIVE BIT LINE RECOVERY IN A MEMORY ARRAY
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|
|
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|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
08939196
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/07/2000
|
Application #:
|
08939838
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
ISOLATION SCHEME BASED ON RECESSED LOCOS USING A SLOPED SI ETCH AND DRY FIELD OXIDATION
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|
Patent #:
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|
Issue Dt:
|
10/12/1999
|
Application #:
|
08940437
|
Filing Dt:
|
09/30/1997
|
|
Title:
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SYMMETRIC LOGIC BLOCK INPUT/OUTPUT SCHEME
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/08/2003
|
Application #:
|
08940682
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Filing Dt:
|
09/30/1997
|
|
Title:
|
HYBRID ROUTING ARCHITECTURE FOR HIGH DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/13/2001
|
Application #:
|
08946030
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Filing Dt:
|
10/07/1997
|
|
Title:
|
CIRCULAR PRODUCT TERM ALLOATIONS SCHEME FOR A PROGRAMMABLE DEVICE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/30/1999
|
Application #:
|
08947123
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
MEMORY CELL FOR STORING AT LEAST THREE LOGIC STATES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/11/2000
|
Application #:
|
08949861
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Filing Dt:
|
10/14/1997
|
|
Title:
|
VOLTAGE REFERENCE SOURCE FOR AN OVERVOLTAGE-TOLERANT BUS INTERFACE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08949863
|
Filing Dt:
|
10/14/1997
|
|
Title:
|
OVERVOLTAGE-TOLERANT INPUT OUTPUT BUFFERS HAVING A SWITCH CONFIGURED T TO ISOLATE A PUL-UP TRANSISTOR FROM A VOLTAGE SUPPLY
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|
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Patent #:
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|
Issue Dt:
|
03/30/1999
|
Application #:
|
08955794
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Filing Dt:
|
10/22/1997
|
|
Title:
|
MEMORY CELL FABRICATION EMPLOYING AN INTERPOLY GATE DIELECTRIC ARRANGED UPON A POLISHED FLOATING GATE
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|
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|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08958464
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Filing Dt:
|
10/27/1997
|
|
Title:
|
SYMMETRICAL NOR GATES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/14/2000
|
Application #:
|
08962860
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Filing Dt:
|
11/03/1997
|
|
Title:
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STABLE ADJUSTABLE PROGRAMMING VOLTAGE SCHEME
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/19/1999
|
Application #:
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08963843
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Filing Dt:
|
11/04/1997
|
|
Title:
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CIRCUIT AND METHOD FOR RESETTING A MICROCONTROLLER
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|
|
|
Patent #:
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|
Issue Dt:
|
09/05/2000
|
Application #:
|
08967658
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Filing Dt:
|
11/10/1997
|
|
Title:
|
SKEW-REDUCTION CIRCUIT
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|
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|
Patent #:
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|
Issue Dt:
|
10/31/2000
|
Application #:
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08970107
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Filing Dt:
|
11/13/1997
|
|
Title:
|
LOW TEMPERATURE METALLIZATION PROCESS
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/30/1999
|
Application #:
|
08970448
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Filing Dt:
|
11/14/1997
|
|
Title:
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PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY
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|
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|
Patent #:
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|
Issue Dt:
|
09/21/1999
|
Application #:
|
08970452
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/09/1999
|
Application #:
|
08970453
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/06/1999
|
Application #:
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08970454
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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|
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|
Patent #:
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|
Issue Dt:
|
11/16/1999
|
Application #:
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08970518
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Filing Dt:
|
11/14/1997
|
|
Title:
|
REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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|
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|
Patent #:
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|
Issue Dt:
|
10/19/1999
|
Application #:
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08970519
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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|
Patent #:
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|
Issue Dt:
|
11/02/1999
|
Application #:
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08970522
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Filing Dt:
|
11/14/1997
|
|
Title:
|
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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|
Issue Dt:
|
12/05/2000
|
Application #:
|
08971627
|
Filing Dt:
|
11/17/1997
|
|
Title:
|
DYNAMIC PULL-UP SUPPRESSOR FOR COLUMN REDUNDANCY WRITE SCHEMES WITH REDUNDANT DATA LINES
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Patent #:
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|
Issue Dt:
|
03/21/2000
|
Application #:
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08974736
|
Filing Dt:
|
11/19/1997
|
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Title:
|
UNIVERSAL SERIAL BUS TO PARALLEL BUS SIGNAL CONVERTER AND METHOD OF CONVERSION
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|
Patent #:
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|
Issue Dt:
|
11/23/2004
|
Application #:
|
08974971
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Filing Dt:
|
11/20/1997
|
|
Title:
|
NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
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|
Patent #:
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|
Issue Dt:
|
02/01/2000
|
Application #:
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08978107
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Filing Dt:
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11/25/1997
|
|
Title:
|
METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
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Patent #:
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|
Issue Dt:
|
02/15/2000
|
Application #:
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08978398
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Filing Dt:
|
11/25/1997
|
|
Title:
|
METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
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Patent #:
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|
Issue Dt:
|
01/25/2000
|
Application #:
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08982186
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Filing Dt:
|
12/17/1997
|
|
Title:
|
METHOD FOR FORMING A LOW BARRIER HEIGHT OXIDE LAYER ON A SILICON SUBSTRATE
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|
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|
Patent #:
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|
Issue Dt:
|
08/29/2000
|
Application #:
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08985890
|
Filing Dt:
|
12/05/1997
|
|
Title:
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PARALLEL TEST FOR ASYNCHRONOUS MEMORY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/09/1999
|
Application #:
|
08986160
|
Filing Dt:
|
12/05/1997
|
|
Title:
|
SIDEWALL SPACER FOR PROTECTING TUNNEL OXIDE DURING ISOLATION TRENCH FORMATION IN SELF-ALIGNED FLASH MEMORY CORE
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|
Patent #:
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|
Issue Dt:
|
11/02/1999
|
Application #:
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08986371
|
Filing Dt:
|
12/08/1997
|
|
Title:
|
METHOD OF REDUCING IMPURITY CONTAMINATION IN SEMICONDUCTOR PROCESS CHAMBERS
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|
Patent #:
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|
Issue Dt:
|
04/25/2000
|
Application #:
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08986440
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Filing Dt:
|
12/08/1997
|
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Title:
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CURRENTSENSING AMPLIFIER WITH FEEDBACK
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|
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|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
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08986860
|
Filing Dt:
|
12/08/1997
|
|
Title:
|
METHOD OF ELIMINATING POLY STRINGER IN A MEMORY DEVICE
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|
Patent #:
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|
Issue Dt:
|
04/04/2000
|
Application #:
|
08986951
|
Filing Dt:
|
12/08/1997
|
|
Title:
|
ELIMINATION OF POLY STRINGERS WITH STRAIGHT POLY PROFILE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08986953
|
Filing Dt:
|
12/08/1997
|
|
Title:
|
REDUCTION OF ONO FENCE DURING SELF-ALIGNED ETCH TO ELIMINATE POLY STRINGERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08988942
|
Filing Dt:
|
12/11/1997
|
|
Title:
|
APPARATUS AND METHOD FOR CORRECTING DATA IN A NON- VOLATILE RANDOM ACCESS MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08989707
|
Filing Dt:
|
12/12/1997
|
|
Title:
|
LOW POWER BUFFER CIRCUIT AND METHOD FOR GENERATING A COMMON-MODE OUTPUT ABSENT PROCESS-INDUCED MISMATCH ERROR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08989820
|
Filing Dt:
|
12/12/1997
|
|
Title:
|
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
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|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08990126
|
Filing Dt:
|
12/12/1997
|
|
Title:
|
COMBINATIONAL LOGIC FEEDBACK CIRCUIT TO ENSURE CORRECT POWER-ON-RESET OF A FOUR-BIT SYNCHRONOUS SHIFT REGISTER
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|
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|
Patent #:
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|
Issue Dt:
|
11/30/1999
|
Application #:
|
08991052
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/05/1999
|
Application #:
|
08991231
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
WRITE ENABLING CIRCUITRY FOR A SEMICONDUCT0R MEMORY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/24/2005
|
Application #:
|
08991232
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
MICROCONTROLLER WITH PROGRAMMABLE LOGIC ON A SINGLE CHIP
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/06/2000
|
Application #:
|
08991299
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
INTERLEVEL DIELECTRIC THICKNESS MONITOR FOR COMPLEX SEMICONDUCTOR CHIPS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/12/1999
|
Application #:
|
08991466
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
PROGRAMMING OF MEMORY CELLS USING CONNECTED FLOATING GATE ANALOG REFERENCE CELL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/03/2000
|
Application #:
|
08991687
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
NON-SELF-ALIGNED SIDE CHANNEL IMPLANTS FOR FLASH MEMORY CELLS
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/02/2002
|
Application #:
|
08991845
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
APPARATUS AND METHOD FOR SHORTING RESTRANSMIT RECOVERY TIMES UTILIZING CACHE MEMORY IN HIGH SPEED FIFO
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/25/1999
|
Application #:
|
08992077
|
Filing Dt:
|
12/17/1997
|
|
Title:
|
METHOD TO IMPROVE TESTING SPEED OF MEMORY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/21/1999
|
Application #:
|
08992199
|
Filing Dt:
|
12/17/1997
|
|
Title:
|
CIRCUIT AND METHOD FOR INSTRUCTION CONTROLLABLE SLEW RATE OF BIT LINE DRIVER
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|
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|
Patent #:
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|
Issue Dt:
|
02/22/2000
|
Application #:
|
08992536
|
Filing Dt:
|
12/17/1997
|
|
Title:
|
METHOD FOR FULLY PLANARIZED CONDUCTIVE LINE FOR A STACK GATE
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/14/2002
|
Application #:
|
08992616
|
Filing Dt:
|
12/17/1997
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING LOCALIZED GATE EDGE ROUNDING WITH MINIMAL ENCROACHMENT AND GATE EDGE LIFTING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/15/2000
|
Application #:
|
08992618
|
Filing Dt:
|
12/17/1997
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING A DRAIN SIDE POCKET IMPLANT
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Patent #:
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Issue Dt:
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09/07/1999
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Application #:
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08992622
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Filing Dt:
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR SELECTED SOURCE DURING READ AND PROGRAMMING OF FLASH MEMORY
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08992950
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08992951
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A TAPERED FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08992960
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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08992961
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Filing Dt:
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12/18/1997
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Title:
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NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08993036
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Filing Dt:
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12/18/1997
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Title:
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METHOD AND APPARATUS FOR OBTAINING TWO-OR THREE-DEMENSIONAL INFORMATION FROM SCANNING ELECTRON MICROSCOPY
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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08993062
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Filing Dt:
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12/18/1997
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Title:
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DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08993343
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Filing Dt:
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12/18/1997
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Title:
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MANUFACTURING PROCESS TO ELIMINATE POLYSTRINGERS IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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08993344
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Filing Dt:
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12/18/1997
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Title:
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MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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08993368
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Filing Dt:
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12/18/1997
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Title:
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NOVEL NAND TYPE CORE CELL STRUCTURE FOR A HIGH DENSITY FLASH MEMORY DEVICE HAVING A UNIQUE SELECT GATE TRANSISTOR CONFIGURATION
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08993409
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Filing Dt:
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12/18/1997
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Title:
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METHODS FOR FORMING A CONTROL GATE APPARATUS IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08993443
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Filing Dt:
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12/18/1997
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Title:
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NITROGEN ION IMPLANTED AMORPHOUS SILICON TO PRODUCE OXIDATION RESISTANT AND FINER GRAIN POLYSILICON BASED FLOATING GATES
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08993444
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Filing Dt:
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12/18/1997
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Title:
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IN SITU P DOPED AMORPHOUS SILICON BY NH3 TO FORM OXIDATION RESISTANT AND FINER GRAIN FLOATING GATES.
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08993599
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Filing Dt:
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12/18/1997
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Title:
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METHOD AND SYSTEM FOR SOURCE ONLY REOXIDATION AFTER JUNCTION IMPLANT FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08993600
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Filing Dt:
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12/18/1997
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Title:
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METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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08993634
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Filing Dt:
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12/18/1997
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Title:
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SPLIT VOLTAGE FOR NAND FLASH
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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08993716
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Filing Dt:
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12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08993787
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Filing Dt:
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12/19/1997
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Title:
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METHOD AND SYSTEM FOR GATE STACK REOXIDATION CONTROL
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08993890
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Filing Dt:
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12/18/1997
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Title:
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NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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08994140
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Filing Dt:
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12/19/1997
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Title:
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METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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08995381
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Filing Dt:
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12/22/1997
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Title:
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STAGGERED BITLINE PRECHARGE SCHEME
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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08995494
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Filing Dt:
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12/22/1997
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Title:
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CURRENT SENSING GATED CURRENT SOURCE FOR DELAY REDUCTION IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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08998090
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Filing Dt:
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12/24/1997
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Title:
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OPTIMIZED PROGRAMMING/ERASE PARAMETERS FOR PROGRAMMABLE DEVICES
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Patent #:
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Issue Dt:
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09/28/1999
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Application #:
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08998258
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Filing Dt:
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12/29/1997
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Title:
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COUNTER-BIAS SCHEME TO REDUCE CHARGE GAIN IN AN ELECTRICALLY ERASABLE CELL
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09000739
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Filing Dt:
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12/30/1997
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Title:
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A LOW DIELECTRIC CONSTANT MATERIAL AND METHOD OF APPLICATION TO ISOLATE CONDUCTIVE LINES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09002783
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Filing Dt:
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01/05/1998
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Title:
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METHOD FOR PREVENTING P1 PUNCHTHROUGH
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09006495
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Filing Dt:
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01/13/1998
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Title:
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TRUNGSTEN PLUG FORMATION
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09006757
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Filing Dt:
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01/14/1998
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Title:
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FLASH EPROM CELL WITH REDUCED SHORT CHANNEL EFFECT AND METHOD FOR PROVIDING SAME
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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09006958
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Filing Dt:
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01/14/1998
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Title:
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METHOD OF FORMING A LOW RESISTIVITY TI-CONTAINING INTERCONNECT AND SEMICONDUCTOR DEVICE COMPRISING THE SAME
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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09007393
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Filing Dt:
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01/15/1998
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Title:
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IMPROVED CHARGE PUMP ARCHITECTURE
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09008162
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Filing Dt:
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01/16/1998
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Title:
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FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
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