Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 041567/0060 | |
| Pages: | 3 |
| | Recorded: | 03/14/2017 | | |
| Attorney Dkt #: | 140649-1227 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15458109
|
Filing Dt:
|
03/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2018
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING MOS TRANSISTORS AND METHOD OF MANUFACTURING THE SAME
|
|
|
Assignee
|
|
|
|
|
| 850, RUE JEAN MONNET |
| CROLLES, FRANCE F-38926 |
|
|
Correspondence name and address
|
| |
GWS-ST-EP GARDERE WYNNE SEWELL LLP
|
| |
INTELLECTUAL PROPERTY SECTION
|
| |
2021 MCKINNEY AVE., SUITE 1600
|
| |
DALLAS, TX 75201-2237
|
Search Results as of:
05/16/2024 08:44 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
