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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09039299
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Filing Dt:
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03/14/1998
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Title:
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PROGRAMMABLE CONTROLLING DEVICE WITH NON-VOLATILE FERROELECTRIC STATE-MACHINES FOR RESTARTING PROCESSOR WHEN POWER IS RESTORED WITH EXECUTION STATES RETAINED IN SAID NON-VOLATILE STATE-MACHINES ON POWER DOWN
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09078872
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Filing Dt:
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05/14/1998
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Title:
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FIELD PROGRAMMABLE GATE ARRAY (FPGA) EMULATOR FOR DEBUGGING SOFTWARE
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09078952
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Filing Dt:
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05/14/1998
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Title:
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MICROCONTROLLER INCORPORATING AN ENHANCED PERIPHERAL CONTROLLER FOR AUTOMATIC UPDATING THE CONFIGURATION DATA OF MULTIPLE PERIPHERALS BY USING A FERROELECTRIC MEMORY ARRAY
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09110115
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Filing Dt:
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07/02/1998
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Title:
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METHOD OF SELF-ALIGNING A FLOATING GATE TO A CONTROL GATE AND TO AN ISOLATION IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY CELL, AND A CELL MADE THEREBY
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09118736
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Filing Dt:
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07/17/1998
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Title:
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SMART CARD COMPRISING INTEGRATED CIRCUITRY INCLUDING EPROM
AND ERROR CHECK AND CORRECTION SYSTEM
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09231928
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Filing Dt:
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01/14/1999
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Title:
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ARRAY ARCHITECTURE AND OPERATING METHOD FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTERGATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09255360
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Filing Dt:
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02/23/1999
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Title:
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NONVOLATILE MEMORY WITH SELF-ALIGNED FLOATING GATE AND FABRICATION PROCESS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09275670
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Filing Dt:
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03/24/1999
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Title:
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FLASH MEMORY CELL WITH SELF-ALIGNED GATES AND FABRICATION PROCESS
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09281570
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Filing Dt:
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03/30/1999
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Title:
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CHARGE PUMP CIRCUIT
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09322126
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Filing Dt:
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05/27/1999
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Title:
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FLASH MEMORY CELL WITH THIN FLOATING GATE WITH ROUNDED SIDE WALL
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09337569
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Filing Dt:
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06/22/1999
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Title:
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VOLTAGE SENSING CIRCUIT AND METHOD FOR PREVENTING A LOW-VOLTAGE FROM BEING INADVERTENTLY SENSED AS A HIGH-VOLTAGE DURING POWER-UP OR POWER-DOWN
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09338451
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Filing Dt:
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06/22/1999
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Title:
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FLASH MEMORY WITH ALTERABLE ERASE SECTOR SIZE
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09370557
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Filing Dt:
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08/09/1999
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Title:
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MEMORY CELL WITH SELF-ALIGNED FLOATING GATE AND SEPARATE SELECT GATE, AND FABRICATION PROCESS
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09390060
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Filing Dt:
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09/03/1999
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Title:
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WORD LINE AND SOURCE LINE DRIVER CIRCUITRIES
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09401173
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Filing Dt:
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09/22/1999
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Title:
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SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS AND A MEMORY ARRAY MADE THEREBY
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09401622
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Filing Dt:
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09/22/1999
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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SELF-ALIGNED NON-VOLATILE RANDOM ACCESS MEMORY CELL AND PROCESS TO MAKE THE SAME
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09412854
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Filing Dt:
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10/05/1999
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Title:
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MEMORY CELL WITH SELF-ALIGNED FLOATING GATE AND SEPARATE SELECT GATE, AND FABRICATION PROCESS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09420318
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Filing Dt:
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10/19/1999
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Title:
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MEMORY MANAGEMENT METHOD AND APPARATUS FOR PARTITIONING HOMOGENEOUS MEMORY AND RESTRICTING ACCESS OF INSTALLED APPLICATIONS TO PREDETERMINED MEMORY RANGES
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09427885
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Filing Dt:
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10/26/1999
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Title:
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FLASH MEMORY CELL WITH SELF-ALIGNED GATES AND FABRICATION PROCESS
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09428291
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Filing Dt:
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10/27/1999
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Title:
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CLAMP CIRCUIT USING PMOS-TRANSISTORS WITH A WEAK TEMPERATURE DEPENDENCY
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09507219
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Filing Dt:
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02/18/2000
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Title:
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AN IMPROVED OSCILLATOR AND CURRENT SOURCE
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09507220
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Filing Dt:
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02/18/2000
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Title:
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Output stage for a charge pump and a charge pump made thereby
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09507234
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Filing Dt:
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02/18/2000
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Title:
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METHOD AND APPARATUS FOR TESTING A NON-VOLATILE MEMORY ARRAY HAVING A LOW NUMBER OF OUTPUT PINS
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09507570
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Filing Dt:
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02/18/2000
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Title:
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Non-volatile flip-flop circuit
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09523828
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Filing Dt:
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03/13/2000
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Title:
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Precision programming of nonvolatile memory cells
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09527373
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Filing Dt:
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03/16/2000
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Title:
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Differential non-volatile content addressable memory cell and array
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09531131
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Filing Dt:
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03/17/2000
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Title:
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METHOD AND APPARATUS FOR DETECTING A TAMPER CONDITION AND ISOLATING A CIRCUIT THEREFROM
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09536387
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Filing Dt:
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03/28/2000
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Title:
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Isolation circuit and method for controlling discharge of high-voltage in a flash EEPROM
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09561710
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Filing Dt:
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05/01/2000
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Title:
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Reduction of data dependent power supply noise when sensing the state of a memory cell
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09562490
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Filing Dt:
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05/01/2000
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Title:
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Integrated memory circuit having a flash memory array and at least one sram memory array with internal address and data bus for transfer of signals therebetween
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09564324
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Filing Dt:
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05/03/2000
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Title:
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Electronically-eraseable programmable read-only memory having reduced-page-size program and erase
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09574387
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Filing Dt:
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05/19/2000
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Title:
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Voltage regulating circuit with a clamp up circuit and a clamp down circuit operating in tandem
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09576394
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Filing Dt:
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05/22/2000
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Title:
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FLASH MEMORY CELL WITH CONTACTLESS BIT LINE, AND PROCESS OF FABRICATION
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09627917
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Filing Dt:
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07/28/2000
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Title:
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TESTING OF MULTILEVEL SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09661681
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Filing Dt:
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09/14/2000
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Title:
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BIAS GENERATING CIRCUIT FOR USE WITH AN OSCILLATING CIRCUIT IN AN INTEGRATED CIRCUIT CHARGE PUMP
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09718650
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Filing Dt:
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11/21/2000
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Title:
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TIMING INDEPENDENT CURRENT COMPARISON AND SELF-LATCHING DATA CIRCUIT
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09726690
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Filing Dt:
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11/29/2000
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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POWER ON CIRCUIT FOR GENERATING RESET SIGNAL
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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09742861
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Filing Dt:
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12/20/2000
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Publication #:
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Pub Dt:
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07/05/2001
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Title:
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INTEGRATED CIRCUIT PROVIDED WITH MEAND FOR CALIBRATING AN ELECTRIC MODULE AND METHOD FOR CALIBRATING AN ELECTRIC MODULE OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09768984
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Filing Dt:
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01/23/2001
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Publication #:
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Pub Dt:
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09/06/2001
| | | | |
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Title:
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MEMORY CELL WITH SELF-ALIGNED FLOATING GATE AND SEPARATE SELECT GATE, AND FABRICATION PROCESS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09802184
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Filing Dt:
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03/08/2001
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Publication #:
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Pub Dt:
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11/08/2001
| | | | |
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Title:
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REDUCTION OF DATA DEPENDENT POWER SUPPLY NOISE WHEN SENSING THE STATE OF A MEMORY CELL
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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09809897
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
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Title:
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ON-CHIP METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR CIRCUITS
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09823032
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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02/14/2002
| | | | |
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Title:
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METHOD OF SELF-ALIGNING A FLOATING GATE TO A CONTROL GATE AND TO AN ISOLATION IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY CELL, AND A CELL MADE THEREBY
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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09839107
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Filing Dt:
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04/20/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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WIRELESS IC INTERCONNECTION METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09860706
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Filing Dt:
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05/18/2001
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Title:
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CONTROL CIRCUIT FOR A NON-VOLATILE MEMORY ARRAY FOR CONTROLLING THE RAMP RATE OF HIGH VOLTAGE APPLIED TO THE MEMORY CELLS AND TO LIMIT THE CURRENT DRAWN THEREFROM
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09862078
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Filing Dt:
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05/21/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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FLASH MEMORY CELL WITH CONTACTLESS BIT LINE, AND PROCESS OF FABRICATION
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09898582
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Filing Dt:
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07/02/2001
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Publication #:
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Pub Dt:
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03/28/2002
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Title:
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ARRAY ARCHITECTURE AND OPERATING METHODS FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09903919
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Filing Dt:
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07/12/2001
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Title:
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METHOD AND APPARATUS FOR SENSING A MEMORY SIGNAL FROM A SELECTED MEMORY CELL OF A MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09904160
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Filing Dt:
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07/11/2001
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Title:
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BITLINE PRECHARGE MATCHING
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09909817
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Filing Dt:
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07/20/2001
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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PRECISION PROGRAMMING OF NONVOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09916423
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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A SELF-ALIGNED FLOATING GATE POLY FOR A FLASH E2PROM CELL
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09916555
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH LOW RESISTANCE SOURCE REGIONS AND HIGH SOURCE COUPLING
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09916618
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH VERTICAL CONTROL GATE SIDEWALLS AND INSULATION SPACERS
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09916619
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH CONTROL GATE SPACER PORTIONS
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09917023
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH CONTROL GATES PROTRUDING PORTIONS, AND A MEMORY ARRAY MADE THEREBY
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09929370
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Filing Dt:
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08/13/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Title:
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ARRAY ARCHITECTURE AND OPERATING METHODS FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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09929542
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Filing Dt:
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08/13/2001
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Publication #:
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Pub Dt:
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04/11/2002
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Title:
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ARRAY ARCHITECTURE AND OPERATING METHODS FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09930811
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Filing Dt:
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08/15/2001
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Title:
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METHOD AND APPARATUS FOR STRAPPING A PLURALITY OF POLYSILICON LINES IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09931956
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Filing Dt:
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08/16/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH FLOATING GATES HAVING MULTIPLE SHARP EDGES
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09954387
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Filing Dt:
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09/10/2001
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Publication #:
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Pub Dt:
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03/13/2003
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Title:
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INTEGRATED CIRCUIT FOR CONCURRENT FLASH MEMORY WITH UNEVEN ARRAY ARCHITECTURE
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09960544
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Filing Dt:
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09/21/2001
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Title:
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REPROGRAMMABLE FUSE AND METHOD OF OPERATING
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09960589
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Filing Dt:
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09/21/2001
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Publication #:
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Pub Dt:
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03/27/2003
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Title:
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FOLDED CASCODE HIGH VOLTAGE OPERATIONAL AMPLIFIER WITH CLASS AB SOURCE FOLLOWER OUTPUT STAGE
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09972179
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Filing Dt:
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10/05/2001
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Publication #:
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Pub Dt:
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01/31/2002
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Title:
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SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS, AND A MEMORY ARRAY MADE THEREBY
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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09982413
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Filing Dt:
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10/17/2001
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED BIT-LINE AND VERTICAL WORD LINE TRANSISTOR
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09999709
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Filing Dt:
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10/30/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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ON-CHIP INDUCTOR USING ACTIVE MAGNETIC ENERGY RECOVERY
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10002036
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Filing Dt:
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11/01/2001
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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NON-VOLATILE FLASH FUSE ELEMENT
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10017608
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Filing Dt:
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12/14/2001
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS SRAM FUNCTIONALITY WITH A DRAM ARRAY
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01/21/2003
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10022314
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Filing Dt:
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12/18/2001
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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ELECTRICALLY-ERASEABLE PROGRAMMABLE READ-ONLY MEMORY HAVING REDUCED-PAGE-SIZE PROGRAM AND ERASE
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Patent #:
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Issue Dt:
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10/28/2003
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10027665
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12/20/2001
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06/26/2003
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Title:
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METHOD AND SYSTEM FOR DYNAMICALLY CLOCKING DIGITAL SYSTEMS BASED ON POWER USAGE
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Patent #:
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05/20/2003
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Application #:
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10040724
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Filing Dt:
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10/31/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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SENICONDUCTOR ARRAY OF FLOATING GATE MEMORY CELLS AND STRAP REGIONS
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10044273
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Filing Dt:
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01/10/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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HIGH VOLTAGE GENERATION AND REGULATION SYSTEM FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10044821
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Filing Dt:
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01/10/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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BIAS DISTRIBUTION NETWORK FOR DIGITAL MULTILEVEL NONVOLATILE FLASH MEMORY
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10052278
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Filing Dt:
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01/17/2002
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Title:
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HIGH SPEED BIAS VOLTAGE GENERATING CIRCUIT
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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10105741
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Filing Dt:
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03/20/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED BIT-LINE AND RAISED SOURCE LINE
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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10135916
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Filing Dt:
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04/29/2002
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Title:
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METHOD OF ERASING NONVOLATILE TUNNELING INJECTOR MEMORY CELL
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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10136797
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Filing Dt:
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04/30/2002
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Title:
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METHOD OF FORMING A SEMICONDUCTOR ARRAY OF FLOATING GATE MEMORY CELLS HAVING STRAP REGIONS AND A PERIPHERAL LOGIC DEVICE REGION
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10146569
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Filing Dt:
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05/14/2002
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR ARRAY OF NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10147959
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Filing Dt:
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05/15/2002
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Title:
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METHOD AND APPARATUS FOR PROGRAMMING NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10183834
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Filing Dt:
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06/25/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH HORIZONTALLY ORIENTED EDGES, AND A MEMORY ARRAY THEREBY
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Patent #:
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03/01/2005
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Application #:
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10192291
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Filing Dt:
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07/09/2002
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Publication #:
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Pub Dt:
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07/24/2003
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Title:
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An array of floating gate memory cells having strap regions and a peripheral logic device region
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10197281
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Filing Dt:
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07/16/2002
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Title:
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HIGH D.C. VOLTAGE TO LOW D.C. VOLTAGE CIRCUIT CONVERTER
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10205289
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Filing Dt:
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07/24/2002
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Publication #:
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Pub Dt:
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03/20/2003
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Title:
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METHOD OF FORMING A SEMICONDUCTOR ARRAY OF FLOATING GATE MEMORY CELLS AND STRAP REGIONS, AND A MEMORY ARRAY AND STRAP REGIONS MADE THEREBY
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10209538
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Filing Dt:
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07/30/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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HIGH VOLTAGE PULSE METHOD AND APPARATUS FOR DIGITAL MULTILEVEL NON-VOLATILE MEMORY INTEGRATED SYSTEM
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10211886
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08/01/2002
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Publication #:
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Pub Dt:
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03/27/2003
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Title:
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WIDE DYNAMIC RANGE AND HIGH SPEED VOLTAGE MODE SENSING FOR A MULTILEVEL DIGITAL NON-VOLATILE MEMORY
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09/07/2004
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10213243
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08/05/2002
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02/05/2004
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Title:
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EMBEDDED RECALL APPARATUS AND METHOD IN NONVOLATILE MEMORY
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12/09/2008
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10238757
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09/10/2002
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03/11/2004
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Title:
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PROGRAMMABLE SERIAL INTERFACE FOR A SEMICONDUCTOR CIRCUIT
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04/26/2005
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10241266
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09/10/2002
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03/11/2004
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Title:
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DIFFERENTIAL SENSE AMPLIFIER FOR MULTILEVEL NON-VOLATILE MEMORY
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05/02/2006
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10241442
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09/10/2002
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03/11/2004
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Title:
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HIGH SPEED AND HIGH PRECISION SENSING FOR DIGITAL MULTILEVEL NON-VOLATILE MEMORY SYSTEM
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01/04/2005
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10246196
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09/17/2002
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03/18/2004
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Title:
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USER IDENTIFICATION FOR MULTI-PURPOSE FLASH MEMORY
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03/02/2004
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10246882
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09/18/2002
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Title:
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HYBRID TRENCH ISOLATION TECHNOLOGY FOR HIGH VOLTAGE ISOLATION USING THIN FIELD OXIDE IN A SEMICONDUCTOR PROCESS
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06/29/2004
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10247400
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09/18/2002
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03/18/2004
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METHOD FOR FORMING A SUBLITHOGRAPHIC OPENING IN A SEMICONDUCTOR PROCESS
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04/26/2005
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10251664
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09/19/2002
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03/25/2004
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SELF-ALIGNED SPLIT-GATE NAND FLASH MEMORY AND FABRICATION PROCESS
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06/08/2004
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10267014
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10/07/2002
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04/08/2004
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10/19/2004
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10286605
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11/01/2002
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05/06/2004
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METHOD AND APPARATUS FOR VIRTUALLY PARTITIONING AN INTEGRATED MULTILEVEL NONVOLATILE MEMORY CIRCUIT
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06/22/2004
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10288361
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11/04/2002
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05/06/2004
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METHOD AND APPARATUS FOR PROGRAMMING AND TESTING A NON-VOLATILE MEMORY CELL FOR STORING MULTIBIT STATES
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11/09/2004
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10305735
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11/27/2002
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05/27/2004
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Title:
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METHOD OF UTILIZING A PLURALITY OF VOLTAGE PULSES TO PROGRAM NON-VOLATILE MEMORY ELEMENTS AND RELATED EMBEDDED MEMORIES
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08/10/2004
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10306571
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11/27/2002
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05/27/2004
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Title:
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METHOD OF UTILIZING VOLTAGE GRADIENTS TO GUIDE DIELECTRIC BREAKDOWNS FOR NON-VOLATILE MEMORY ELEMENTS AND RELATED EMBEDDED MEMORIES
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08/10/2004
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10306572
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11/27/2002
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05/27/2004
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Title:
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NON-VOLATILE MEMORY ELEMENT INTEGRATABLE WITH STANDARD CMOS CIRCUITRY AND RELATED PROGRAMMING METHODS AND EMBEDDED MEMORIES
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04/12/2005
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10310441
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12/04/2002
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08/14/2003
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Title:
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SELF ALIGNED METHOD OF FORMING NON-VOLATILE MEMORY CELLS WITH FLAT WORD LINE
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12/13/2005
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10317375
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12/11/2002
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Pub Dt:
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08/28/2003
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Title:
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DIGITAL MULTILEVEL NON-VOLATILE MEMORY SYSTEM
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04/18/2006
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10317409
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12/11/2002
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Pub Dt:
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06/05/2003
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Title:
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DIGITAL MULTILEVEL MEMORY SYSTEM HAVING MULTISTAGE AUTOZERO SENSING
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