Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 042355/0948 | |
| Pages: | 18 |
| | Recorded: | 05/12/2017 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
13
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Patent #:
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Issue Dt:
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08/01/2017
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Application #:
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15473537
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Filing Dt:
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03/29/2017
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Title:
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INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-TIP SHORT CONFIGURED FILL CELLS
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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15473542
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Filing Dt:
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03/29/2017
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Title:
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INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-SIDE SHORT CONFIGURED FILL CELLS
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Patent #:
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Issue Dt:
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09/19/2017
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Application #:
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15473547
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Filing Dt:
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03/29/2017
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Title:
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Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Side-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
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Patent #:
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Issue Dt:
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11/21/2017
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Application #:
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15473644
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Filing Dt:
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03/30/2017
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Title:
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INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING TIP-TO-TIP SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS
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Patent #:
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Issue Dt:
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08/01/2017
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Application #:
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15473646
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Filing Dt:
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03/30/2017
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Title:
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Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Tip Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells
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Patent #:
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Issue Dt:
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11/14/2017
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Application #:
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15473647
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Filing Dt:
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03/30/2017
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Title:
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Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
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Patent #:
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Issue Dt:
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04/23/2019
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Application #:
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15473649
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Filing Dt:
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03/30/2017
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Title:
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Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells
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Patent #:
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Issue Dt:
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10/24/2017
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Application #:
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15473651
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Filing Dt:
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03/30/2017
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Title:
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INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CORNER SHORT CONFIGURED FILL CELLS
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Patent #:
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Issue Dt:
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08/29/2017
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Application #:
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15475194
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Filing Dt:
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03/31/2017
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Title:
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PROCESS FOR MAKING AND USING A SEMICONDUCTOR WAFER CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-SIDE SHORT CONFIGURE
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Patent #:
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Issue Dt:
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03/20/2018
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Application #:
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15475198
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Filing Dt:
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03/31/2017
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Title:
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PROCESS FOR MAKING AND USING A SEMICONDUCTOR WAFER CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS
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Patent #:
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Issue Dt:
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01/16/2018
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Application #:
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15475242
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Filing Dt:
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03/31/2017
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Title:
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Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Tip Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
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Patent #:
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Issue Dt:
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03/27/2018
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Application #:
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15475285
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Filing Dt:
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03/31/2017
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Title:
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Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
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Patent #:
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Issue Dt:
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09/26/2017
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Application #:
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15475327
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Filing Dt:
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03/31/2017
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Title:
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Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Chamfer Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells
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Assignee
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333 W. SAN CARLOS ST. |
STE 1000 |
SAN JOSE, CALIFORNIA 95110 |
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Correspondence name and address
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DAVID GARROD, PH.D., ESQ.
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711 IVY STREET
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PITTSBURGH, PA 15232
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