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Patent Assignment Details
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Reel/Frame:042355/0948   Pages: 18
Recorded: 05/12/2017
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 13
1
Patent #:
Issue Dt:
08/01/2017
Application #:
15473537
Filing Dt:
03/29/2017
Title:
INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-TIP SHORT CONFIGURED FILL CELLS
2
Patent #:
Issue Dt:
07/18/2017
Application #:
15473542
Filing Dt:
03/29/2017
Title:
INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-SIDE SHORT CONFIGURED FILL CELLS
3
Patent #:
Issue Dt:
09/19/2017
Application #:
15473547
Filing Dt:
03/29/2017
Title:
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Side-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
4
Patent #:
Issue Dt:
11/21/2017
Application #:
15473644
Filing Dt:
03/30/2017
Title:
INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING TIP-TO-TIP SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS
5
Patent #:
Issue Dt:
08/01/2017
Application #:
15473646
Filing Dt:
03/30/2017
Title:
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Tip Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells
6
Patent #:
Issue Dt:
11/14/2017
Application #:
15473647
Filing Dt:
03/30/2017
Title:
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
7
Patent #:
Issue Dt:
04/23/2019
Application #:
15473649
Filing Dt:
03/30/2017
Title:
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells
8
Patent #:
Issue Dt:
10/24/2017
Application #:
15473651
Filing Dt:
03/30/2017
Title:
INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CORNER SHORT CONFIGURED FILL CELLS
9
Patent #:
Issue Dt:
08/29/2017
Application #:
15475194
Filing Dt:
03/31/2017
Title:
PROCESS FOR MAKING AND USING A SEMICONDUCTOR WAFER CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-SIDE SHORT CONFIGURE
10
Patent #:
Issue Dt:
03/20/2018
Application #:
15475198
Filing Dt:
03/31/2017
Title:
PROCESS FOR MAKING AND USING A SEMICONDUCTOR WAFER CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS
11
Patent #:
Issue Dt:
01/16/2018
Application #:
15475242
Filing Dt:
03/31/2017
Title:
Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Tip Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
12
Patent #:
Issue Dt:
03/27/2018
Application #:
15475285
Filing Dt:
03/31/2017
Title:
Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells
13
Patent #:
Issue Dt:
09/26/2017
Application #:
15475327
Filing Dt:
03/31/2017
Title:
Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Chamfer Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells
Assignors
1
Exec Dt:
04/21/2016
2
Exec Dt:
04/15/2016
3
Exec Dt:
04/20/2016
4
Exec Dt:
05/06/2016
5
Exec Dt:
04/13/2016
6
Exec Dt:
04/12/2016
7
Exec Dt:
04/28/2016
8
Exec Dt:
04/26/2016
9
Exec Dt:
04/13/2016
10
Exec Dt:
04/13/2016
11
Exec Dt:
04/12/2016
12
Exec Dt:
04/18/2016
13
Exec Dt:
04/14/2016
14
Exec Dt:
04/15/2016
15
Exec Dt:
04/28/2016
16
Exec Dt:
04/25/2016
17
Exec Dt:
04/18/2016
18
Exec Dt:
04/21/2016
19
Exec Dt:
04/26/2016
20
Exec Dt:
04/13/2016
21
Exec Dt:
04/28/2016
22
Exec Dt:
04/13/2016
23
Exec Dt:
04/13/2016
24
Exec Dt:
04/12/2016
25
Exec Dt:
04/21/2016
26
Exec Dt:
04/13/2016
Assignee
1
333 W. SAN CARLOS ST.
STE 1000
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
DAVID GARROD, PH.D., ESQ.
711 IVY STREET
PITTSBURGH, PA 15232

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