Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 042356/0327 | |
| Pages: | 3 |
| | Recorded: | 05/12/2017 | | |
| Attorney Dkt #: | T&A-GENERAL/Z-1704(USMA)S |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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07/20/2010
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Application #:
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11837168
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Filing Dt:
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08/10/2007
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Publication #:
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Pub Dt:
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12/13/2007
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Title:
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FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12836432
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Filing Dt:
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07/14/2010
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12956524
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Filing Dt:
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11/30/2010
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Publication #:
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Pub Dt:
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03/24/2011
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Title:
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FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13607864
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Assignees
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN |
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| 3-2, FUJIHASHI 3-CHOME, OME-SHI |
| TOKYO, JAPAN |
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Correspondence name and address
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MATTINGLY & MALUR, PC
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1800 DIAGONAL ROAD
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SUITE 210
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ALEXANDRIA, VA 22314
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