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Reel/Frame:042610/0451   Pages: 12
Recorded: 05/29/2017
Attorney Dkt #:VLSIS001
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 56
1
Patent #:
6147510
Issue Dt:
11/14/2000
Application #:
09114119
Filing Dt:
07/13/1998
Title:
INTEGRATED CIRCUIT FOR HANDLING BUFFER CONTENTION AND METHOD THEREOF
2
Patent #:
6111796
Issue Dt:
08/29/2000
Application #:
09259454
Filing Dt:
03/01/1999
Title:
PROGRAMMABLE DELAY CONTROL IN A MEMORY
3
Patent #:
5978286
Issue Dt:
11/02/1999
Application #:
09259455
Filing Dt:
03/01/1999
Title:
TIMING CONTROL OF AMPLIFIERS IN A MEMORY
4
Patent #:
6297155
Issue Dt:
10/02/2001
Application #:
09305093
Filing Dt:
05/03/1999
Title:
METHOD FOR FORMING A COPPER LAYER OVER A SEMICONDUCTOR WAFER
5
Patent #:
6396158
Issue Dt:
05/28/2002
Application #:
09340697
Filing Dt:
06/29/1999
Title:
SEMICONDUCTOR DEVICE AND A PROCESS FOR DESIGNING A MASK
6
Patent #:
6274478
Issue Dt:
08/14/2001
Application #:
09352136
Filing Dt:
07/13/1999
Title:
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
7
Patent #:
6242956
Issue Dt:
06/05/2001
Application #:
09425880
Filing Dt:
10/22/1999
Title:
PHASE LOCKED LOOP
8
Patent #:
6108266
Issue Dt:
08/22/2000
Application #:
09428440
Filing Dt:
10/28/1999
Title:
MEMORY UTILIZING A PROGRAMMABLE DELAY TO CONTROL ADDRESS BUFFERS
9
Patent #:
6385101
Issue Dt:
05/07/2002
Application #:
09543532
Filing Dt:
04/06/2000
Title:
PROGRAMMABLE DELAY CONTROL FOR SENSE AMPLIFIERS IN A MEMORY
10
Patent #:
6380760
Issue Dt:
04/30/2002
Application #:
09636493
Filing Dt:
08/11/2000
Title:
Integrated circuit for handling buffer contention and method thereof
11
Patent #:
6420208
Issue Dt:
07/16/2002
Application #:
09662079
Filing Dt:
09/14/2000
Title:
METHOD OF FORMING AN ALTERNATIVE GROUND CONTACT FOR A SEMICONDUCTOR DIE
12
Patent #:
6444569
Issue Dt:
09/03/2002
Application #:
09835276
Filing Dt:
04/16/2001
Publication #:
US20010027083
Pub Dt:
10/04/2001
Title:
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
13
Patent #:
6593226
Issue Dt:
07/15/2003
Application #:
09906874
Filing Dt:
07/17/2001
Publication #:
US20020050655
Pub Dt:
05/02/2002
Title:
METHOD FOR ADDING FEATURES TO A DESIGN LAYOUT AND PROCESS FOR DESIGNING A MASK
14
Patent #:
6531384
Issue Dt:
03/11/2003
Application #:
09952527
Filing Dt:
09/14/2001
Publication #:
US20030054626
Pub Dt:
03/20/2003
Title:
METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF
15
Patent #:
6657502
Issue Dt:
12/02/2003
Application #:
09968171
Filing Dt:
10/01/2001
Publication #:
US20030062960
Pub Dt:
04/03/2003
Title:
MULTIPHASE VOLTAGE CONTROLLED OSCILLATOR
16
Patent #:
6990164
Issue Dt:
01/24/2006
Application #:
09968178
Filing Dt:
10/01/2001
Publication #:
US20030086519
Pub Dt:
05/08/2003
Title:
DUAL STEERED FREQUENCY SYNTHESIZER
17
Patent #:
7185251
Issue Dt:
02/27/2007
Application #:
10157094
Filing Dt:
05/29/2002
Publication #:
US20030226080
Pub Dt:
12/04/2003
Title:
METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
18
Patent #:
6573173
Issue Dt:
06/03/2003
Application #:
10175637
Filing Dt:
06/20/2002
Publication #:
US20020151167
Pub Dt:
10/17/2002
Title:
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
19
Patent #:
6878633
Issue Dt:
04/12/2005
Application #:
10329081
Filing Dt:
12/23/2002
Publication #:
US20040121606
Pub Dt:
06/24/2004
Title:
FLIP-CHIP STRUCTURE AND METHOD FOR HIGH QUALITY INDUCTORS AND TRANSFORMERS
20
Patent #:
6838721
Issue Dt:
01/04/2005
Application #:
10423589
Filing Dt:
04/25/2003
Publication #:
US20040211963
Pub Dt:
10/28/2004
Title:
Integrated circuit with a transistor over an interconnect layer
21
Patent #:
7385451
Issue Dt:
06/10/2008
Application #:
10537634
Filing Dt:
04/10/2006
Publication #:
US20060192620
Pub Dt:
08/31/2006
Title:
ARRANGEMENT, PHASE LOCKED LOOP AND METHOD FOR NOISE SHAPING IN A PHASE-LOCKED LOOP
22
Patent #:
7057462
Issue Dt:
06/06/2006
Application #:
10857040
Filing Dt:
05/28/2004
Publication #:
US20050264363
Pub Dt:
12/01/2005
Title:
TEMPERATURE COMPENSATED ON-CHIP BIAS CIRCUIT FOR LINEAR RF HBT POWER AMPLIFIERS
23
Patent #:
7042765
Issue Dt:
05/09/2006
Application #:
10912824
Filing Dt:
08/06/2004
Publication #:
US20060028898
Pub Dt:
02/09/2006
Title:
MEMORY BIT LINE SEGMENT ISOLATION
24
Patent #:
7247552
Issue Dt:
07/24/2007
Application #:
11033009
Filing Dt:
01/11/2005
Publication #:
US20060154470
Pub Dt:
07/13/2006
Title:
INTEGRATED CIRCUIT HAVING STRUCTURAL SUPPORT FOR A FLIP-CHIP INTERCONNECT PAD AND METHOD THEREFOR
25
Patent #:
7268588
Issue Dt:
09/11/2007
Application #:
11170398
Filing Dt:
06/29/2005
Publication #:
US20070008001
Pub Dt:
01/11/2007
Title:
CASCADABLE LEVEL SHIFTER CELL
26
Patent #:
7256657
Issue Dt:
08/14/2007
Application #:
11251467
Filing Dt:
10/14/2005
Publication #:
US20070085624
Pub Dt:
04/19/2007
Title:
VOLTAGE CONTROLLED OSCILLATOR HAVING DIGITALLY CONTROLLED PHASE ADJUSTMENT AND METHOD THEREFOR
27
Patent #:
7709303
Issue Dt:
05/04/2010
Application #:
11328668
Filing Dt:
01/10/2006
Publication #:
US20070161171
Pub Dt:
07/12/2007
Title:
PROCESS FOR FORMING AN ELECTRONIC DEVICE INCLUDING A FIN-TYPE STRUCTURE
28
Patent #:
7286423
Issue Dt:
10/23/2007
Application #:
11362694
Filing Dt:
02/27/2006
Publication #:
US20070201298
Pub Dt:
08/30/2007
Title:
BIT LINE PRECHARGE IN EMBEDDED MEMORY
29
Patent #:
7440354
Issue Dt:
10/21/2008
Application #:
11433998
Filing Dt:
05/15/2006
Publication #:
US20070263474
Pub Dt:
11/15/2007
Title:
MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
30
Patent #:
7675806
Issue Dt:
03/09/2010
Application #:
11435942
Filing Dt:
05/17/2006
Publication #:
US20070280026
Pub Dt:
12/06/2007
Title:
LOW VOLTAGE MEMORY DEVICE AND METHOD THEREOF
31
Patent #:
7443745
Issue Dt:
10/28/2008
Application #:
11612626
Filing Dt:
12/19/2006
Publication #:
US20080144409
Pub Dt:
06/19/2008
Title:
BYTE WRITEABLE MEMORY WITH BIT-COLUMN VOLTAGE SELECTION AND COLUMN REDUNDANCY
32
Patent #:
7581151
Issue Dt:
08/25/2009
Application #:
11624454
Filing Dt:
01/18/2007
Publication #:
US20070150782
Pub Dt:
06/28/2007
Title:
METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
33
Patent #:
7880516
Issue Dt:
02/01/2011
Application #:
11910062
Filing Dt:
09/28/2007
Publication #:
US20080265958
Pub Dt:
10/30/2008
Title:
METHOD FOR NOISE REDUCTION IN A PHASE LOCKED LOOP AND A DEVICE HAVING NOISE REDUCTION CAPABILITIES
34
Patent #:
8020014
Issue Dt:
09/13/2011
Application #:
11914079
Filing Dt:
11/09/2007
Publication #:
US20080209248
Pub Dt:
08/28/2008
Title:
METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES
35
Patent #:
7689897
Issue Dt:
03/30/2010
Application #:
11914700
Filing Dt:
11/16/2007
Publication #:
US20090129183
Pub Dt:
05/21/2009
Title:
METHOD AND DEVICE FOR HIGH SPEED TESTING OF AN INTEGRATED CIRCUIT
36
Patent #:
7836369
Issue Dt:
11/16/2010
Application #:
12092463
Filing Dt:
05/02/2008
Publication #:
US20080270858
Pub Dt:
10/30/2008
Title:
DEVICE AND METHOD FOR CONFIGURING INPUT/OUTPUT PADS
37
Patent #:
7706207
Issue Dt:
04/27/2010
Application #:
12209477
Filing Dt:
09/12/2008
Publication #:
US20090021990
Pub Dt:
01/22/2009
Title:
MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
38
Patent #:
8255748
Issue Dt:
08/28/2012
Application #:
12415338
Filing Dt:
03/31/2009
Publication #:
US20100244918
Pub Dt:
09/30/2010
Title:
SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR
39
Patent #:
7868449
Issue Dt:
01/11/2011
Application #:
12471409
Filing Dt:
05/25/2009
Publication #:
US20100295169
Pub Dt:
11/25/2010
Title:
SEMICONDUCTOR SUBSTRATE AND METHOD OF CONNECTING SEMICONDUCTOR DIE TO SUBSTRATE
40
Patent #:
8059482
Issue Dt:
11/15/2011
Application #:
12487791
Filing Dt:
06/19/2009
Publication #:
US20100322027
Pub Dt:
12/23/2010
Title:
MEMORY USING MULTIPLE SUPPLY VOLTAGES
41
Patent #:
8120412
Issue Dt:
02/21/2012
Application #:
12537436
Filing Dt:
08/07/2009
Publication #:
US20110032026
Pub Dt:
02/10/2011
Title:
VOLTAGE BOOSTING SYSTEM WITH SLEW RATE CONTROL AND METHOD THEREOF
42
Patent #:
7948302
Issue Dt:
05/24/2011
Application #:
12555227
Filing Dt:
09/08/2009
Publication #:
US20110057694
Pub Dt:
03/10/2011
Title:
REGULATOR HAVING INTERLEAVED LATCHES
43
Patent #:
8566836
Issue Dt:
10/22/2013
Application #:
12618311
Filing Dt:
11/13/2009
Publication #:
US20110119672
Pub Dt:
05/19/2011
Title:
Multi-Core System on Chip
44
Patent #:
8476962
Issue Dt:
07/02/2013
Application #:
12621005
Filing Dt:
11/18/2009
Publication #:
US20110115554
Pub Dt:
05/19/2011
Title:
SYSTEM HAVING MULTIPLE VOLTAGE TIERS AND METHOD THEREFOR
45
Patent #:
8169257
Issue Dt:
05/01/2012
Application #:
12621026
Filing Dt:
11/18/2009
Publication #:
US20110115550
Pub Dt:
05/19/2011
Title:
SYSTEM AND METHOD FOR COMMUNICATING BETWEEN MULTIPLE VOLTAGE TIERS
46
Patent #:
8018259
Issue Dt:
09/13/2011
Application #:
12695461
Filing Dt:
01/28/2010
Publication #:
US20110181326
Pub Dt:
07/28/2011
Title:
PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR
47
Patent #:
8081026
Issue Dt:
12/20/2011
Application #:
12787457
Filing Dt:
05/26/2010
Publication #:
US20110291740
Pub Dt:
12/01/2011
Title:
METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT
48
Patent #:
8466539
Issue Dt:
06/18/2013
Application #:
13334006
Filing Dt:
12/21/2011
Publication #:
US20120211846
Pub Dt:
08/23/2012
Title:
MRAM DEVICE AND METHOD OF ASSEMBLING SAME
49
Patent #:
8692387
Issue Dt:
04/08/2014
Application #:
13490451
Filing Dt:
06/06/2012
Publication #:
US20130020690
Pub Dt:
01/24/2013
Title:
STACKED DIE SEMICONDUCTOR PACKAGE
50
Patent #:
9046556
Issue Dt:
06/02/2015
Application #:
13523675
Filing Dt:
06/14/2012
Publication #:
US20130335065
Pub Dt:
12/19/2013
Title:
SENSING DEVICE AND RELATED OPERATING METHODS
51
Patent #:
8896341
Issue Dt:
11/25/2014
Application #:
13634726
Filing Dt:
09/13/2012
Publication #:
US20130038373
Pub Dt:
02/14/2013
Title:
INTEGRATED CIRCUIT DEVICE, CALIBRATION MODULE, AND METHOD THEREFOR
52
Patent #:
9081708
Issue Dt:
07/14/2015
Application #:
13679481
Filing Dt:
11/16/2012
Publication #:
US20140143630
Pub Dt:
05/22/2014
Title:
DYNAMIC READ SCHEME FOR HIGH RELIABILITY HIGH PERFORMANCE FLASH MEMORY
53
Patent #:
8886874
Issue Dt:
11/11/2014
Application #:
13925807
Filing Dt:
06/24/2013
Title:
SYSTEM AND METHOD FOR LOW-LATENCY ADDRESSING IN FLASH MEMORY
54
Patent #:
9142566
Issue Dt:
09/22/2015
Application #:
14021485
Filing Dt:
09/09/2013
Publication #:
US20150069524
Pub Dt:
03/12/2015
Title:
Method of Forming Different Voltage Devices with High-K Metal Gate
55
Patent #:
9252751
Issue Dt:
02/02/2016
Application #:
14269194
Filing Dt:
05/04/2014
Publication #:
US20150318842
Pub Dt:
11/05/2015
Title:
APPARATUS AND METHOD FOR PREVENTING MULTIPLE RESETS
56
Patent #:
9368499
Issue Dt:
06/14/2016
Application #:
14843364
Filing Dt:
09/02/2015
Publication #:
US20150380408
Pub Dt:
12/31/2015
Title:
Method of Forming Different Voltage Devices with High-K Metal Gate
Assignor
1
MORGAN STANLEY SENIOR FUNDING, INC.
Exec Dt:
05/02/2017
Assignee
1
NXP USA, INC. F/K/A FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST
AUSTIN, TEXAS 78735
Correspondence name and address
ERIC R. SCHEUERLEIN
626 JEFFERSON AVENUE, SUITE 7
REDWOOD CITY, CA 94063

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