Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 043529/0095 | |
| Pages: | 5 |
| | Recorded: | 09/08/2017 | | |
| Attorney Dkt #: | 419.038 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15556652
|
Filing Dt:
|
09/08/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2018
| | | | |
|
Title:
|
FPGA Clock Signal Self-detection Method
|
|
|
Assignee
|
|
|
|
|
| NO. 428, EAST JIANGCHUAN ROAD, MINHANG DISTRICT |
| SHANGHAI, CHINA 200241 |
|
|
Correspondence name and address
|
| |
KILE PARK REED & HOUTTEMAN LLC
|
| |
3057 NUTLEY STREET
|
| |
SUITE 819
|
| |
FAIRFAX, VA 22031
|
Search Results as of:
05/11/2024 09:34 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
