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Patent Assignment Details
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Reel/Frame:043777/0241   Pages: 18
Recorded: 10/04/2017
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 10
1
Patent #:
Issue Dt:
04/17/2018
Application #:
15719513
Filing Dt:
09/28/2017
Title:
Integrated Circuit Including NCEM-Enabled, Side-to-Side Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
2
Patent #:
Issue Dt:
01/30/2018
Application #:
15719577
Filing Dt:
09/29/2017
Title:
INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, TIP-TO-TIP GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
3
Patent #:
Issue Dt:
10/23/2018
Application #:
15719584
Filing Dt:
09/29/2017
Title:
Integrated Circuit Including NCEM-Enabled, Tip-to-Side Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
4
Patent #:
Issue Dt:
03/06/2018
Application #:
15719595
Filing Dt:
09/29/2017
Title:
INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, CORNER GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
5
Patent #:
Issue Dt:
03/06/2018
Application #:
15719604
Filing Dt:
09/29/2017
Title:
Integrated Circuit Including NCEM-Enabled, Diagonal Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
6
Patent #:
Issue Dt:
01/16/2018
Application #:
15719615
Filing Dt:
09/29/2017
Title:
INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, INTERLAYER OVERLAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
7
Patent #:
Issue Dt:
03/27/2018
Application #:
15721762
Filing Dt:
09/30/2017
Title:
PROCESS FOR MAKING AN INTEGRATED CIRCUIT THAT INCLUDES NCEM-ENABLED, TIP-TO-SIDE GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
8
Patent #:
Issue Dt:
03/06/2018
Application #:
15721789
Filing Dt:
09/30/2017
Title:
Integrated Circuit Including NCEM-Enabled, Via-Open/Resistance-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
9
Patent #:
Issue Dt:
03/20/2018
Application #:
15721792
Filing Dt:
09/30/2017
Title:
Integrated Circuit Including NCEM-Enabled, Snake-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
10
Patent #:
Issue Dt:
02/20/2018
Application #:
15721890
Filing Dt:
09/30/2017
Title:
Process for Making an Integrated Circuit that Includes NCEM-Enabled, Interlayer Overlap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
Assignors
1
Exec Dt:
04/21/2016
2
Exec Dt:
04/15/2016
3
Exec Dt:
04/20/2016
4
Exec Dt:
05/06/2016
5
Exec Dt:
04/13/2016
6
Exec Dt:
04/12/2016
7
Exec Dt:
04/28/2016
8
Exec Dt:
04/26/2016
9
Exec Dt:
04/13/2016
10
Exec Dt:
04/13/2016
11
Exec Dt:
04/12/2016
12
Exec Dt:
04/18/2016
13
Exec Dt:
04/14/2016
14
Exec Dt:
04/15/2016
15
Exec Dt:
04/28/2016
16
Exec Dt:
04/25/2016
17
Exec Dt:
04/18/2016
18
Exec Dt:
04/21/2016
19
Exec Dt:
04/26/2016
20
Exec Dt:
04/13/2016
21
Exec Dt:
04/28/2016
22
Exec Dt:
04/13/2016
23
Exec Dt:
04/13/2016
24
Exec Dt:
04/12/2016
25
Exec Dt:
04/21/2016
26
Exec Dt:
04/13/2016
Assignee
1
333 W. SAN CARLOS ST.
STE 1000
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
DAVID GARROD, PH.D., ESQ.
711 IVY STREET
PITTSBURGH, PA 15232

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