Patent Assignment Details
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Reel/Frame: | 043777/0241 | |
| Pages: | 18 |
| | Recorded: | 10/04/2017 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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04/17/2018
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Application #:
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15719513
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Filing Dt:
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09/28/2017
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Title:
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Integrated Circuit Including NCEM-Enabled, Side-to-Side Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15719577
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Filing Dt:
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09/29/2017
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Title:
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INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, TIP-TO-TIP GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
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Patent #:
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Issue Dt:
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10/23/2018
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Application #:
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15719584
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Filing Dt:
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09/29/2017
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Title:
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Integrated Circuit Including NCEM-Enabled, Tip-to-Side Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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15719595
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Filing Dt:
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09/29/2017
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Title:
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INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, CORNER GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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15719604
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Filing Dt:
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09/29/2017
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Title:
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Integrated Circuit Including NCEM-Enabled, Diagonal Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
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Patent #:
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Issue Dt:
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01/16/2018
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Application #:
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15719615
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Filing Dt:
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09/29/2017
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Title:
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INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, INTERLAYER OVERLAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
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Patent #:
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Issue Dt:
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03/27/2018
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Application #:
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15721762
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Filing Dt:
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09/30/2017
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Title:
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PROCESS FOR MAKING AN INTEGRATED CIRCUIT THAT INCLUDES NCEM-ENABLED, TIP-TO-SIDE GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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15721789
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Filing Dt:
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09/30/2017
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Title:
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Integrated Circuit Including NCEM-Enabled, Via-Open/Resistance-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
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Patent #:
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Issue Dt:
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03/20/2018
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Application #:
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15721792
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Filing Dt:
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09/30/2017
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Title:
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Integrated Circuit Including NCEM-Enabled, Snake-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
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Patent #:
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Issue Dt:
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02/20/2018
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Application #:
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15721890
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Filing Dt:
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09/30/2017
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Title:
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Process for Making an Integrated Circuit that Includes NCEM-Enabled, Interlayer Overlap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates
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Assignee
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333 W. SAN CARLOS ST. |
STE 1000 |
SAN JOSE, CALIFORNIA 95110 |
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Correspondence name and address
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DAVID GARROD, PH.D., ESQ.
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711 IVY STREET
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PITTSBURGH, PA 15232
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