Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 044384/0054 | |
| Pages: | 2 |
| | Recorded: | 12/13/2017 | | |
| Attorney Dkt #: | 04329.0999-00000 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10739275
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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09/23/2004
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Title:
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WAFER FLATNESS EVALUATION METHOD, WAFER FLATNESS EVALUATION APPARATUS CARRYING OUT THE EVALUATION METHOD, WAFER MANUFACTURING METHOD USING THE EVALUATION METHOD, WAFER QUALITY ASSURANCE METHOD USING THE EVALUATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD U
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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11710410
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Filing Dt:
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02/26/2007
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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WAFER FLATNESS EVALUATION METHOD, WAFER FLATNESS EVALUATION APPARATUS CARRYING OUT THE EVALUATION METHOD, WAFER MANUFACTURING METHOD USING THE EVALUATION METHOD, WAFER QUALITY ASSURANCE METHOD USING THE EVALUATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD U
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Patent #:
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Issue Dt:
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01/06/2009
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Application #:
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11710552
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Filing Dt:
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02/26/2007
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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WAFER FLATNESS EVALUATION METHOD, WAFER FLATNESS EVALUATION APPARATUS CARRYING OUT THE EVALUATION METHOD, WAFER MANUFACTURING METHOD USING THE EVALUATION METHOD, WAFER QUALITY ASSURANCE METHOD USING THE EVALUATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD U
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Assignee
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN 105-0023 |
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Correspondence name and address
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JOHN M MULCAHY
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901 NEW YORK AVE, NW
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WASHINGTON, DC 20001
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