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Reel/Frame:044717/0683   Pages: 6
Recorded: 12/06/2017
Attorney Dkt #:050516/441426
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 71
1
Patent #:
Issue Dt:
11/04/2014
Application #:
12695953
Filing Dt:
01/28/2010
Title:
OPERATING SYSTEM WITH HARDWARE-ENABLED TASK MANAGER FOR OFFLOADING CPU TASK SCHEDULING
2
Patent #:
Issue Dt:
09/17/2013
Application #:
12767894
Filing Dt:
04/27/2010
Title:
FREQUENCY OPTIMIZATION USING USEFUL SKEW TIMING
3
Patent #:
Issue Dt:
10/13/2015
Application #:
12772832
Filing Dt:
05/03/2010
Title:
Packet Processing with Dynamic Load Balancing
4
Patent #:
Issue Dt:
07/30/2013
Application #:
12818870
Filing Dt:
06/18/2010
Title:
SYSTEM AND METHOD FOR ATTACHED STORAGE STACKING
5
Patent #:
Issue Dt:
07/29/2014
Application #:
12839225
Filing Dt:
07/19/2010
Title:
NETWORK-ATTACHED STORAGE (NAS) BANDWIDTH MANAGER
6
Patent #:
Issue Dt:
06/24/2014
Application #:
12884264
Filing Dt:
09/17/2010
Title:
SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DIE SIZE REDUCTION
7
Patent #:
Issue Dt:
05/20/2014
Application #:
12917425
Filing Dt:
11/01/2010
Title:
System and Method for Packet Splitting
8
Patent #:
Issue Dt:
12/23/2014
Application #:
13045453
Filing Dt:
03/10/2011
Title:
METHOD AND SYSTEM FOR QUEUING A REQUEST BY A PROCESSOR TO ACCESS A SHARED RESOURCE AND GRANTING ACCESS IN ACCORDANCE WITH AN EMBEDDED LOCK ID
9
Patent #:
Issue Dt:
12/31/2013
Application #:
13077949
Filing Dt:
03/31/2011
Title:
SHADOW LATCH
10
Patent #:
Issue Dt:
02/26/2013
Application #:
13092084
Filing Dt:
04/21/2011
Title:
Digital CMOS Circuit with Noise Cancellation
11
Patent #:
Issue Dt:
02/03/2015
Application #:
13103833
Filing Dt:
05/09/2011
Title:
THRESHOLD CONTROLLED LIMITED OUT OF ORDER LOAD EXECUTION
12
Patent #:
Issue Dt:
03/12/2013
Application #:
13115858
Filing Dt:
05/25/2011
Title:
INTEGRATED CIRCUIT MODULE TIME DELAY BUDGETING
13
Patent #:
Issue Dt:
07/30/2013
Application #:
13160569
Filing Dt:
06/15/2011
Title:
PASS GATE SHADOW LATCH
14
Patent #:
Issue Dt:
04/23/2013
Application #:
13167783
Filing Dt:
06/24/2011
Title:
Stashing System and Method for the Prevention of Cache Thrashing
15
Patent #:
Issue Dt:
11/18/2014
Application #:
13212112
Filing Dt:
08/17/2011
Title:
System and Method for Partitioning Resources in a System-on-Chip (SoC)
16
Patent #:
Issue Dt:
04/16/2013
Application #:
13225044
Filing Dt:
09/02/2011
Title:
HAZARD-FREE MINIMAL-LATENCY FLIP-FLOP (HFML-FF)
17
Patent #:
Issue Dt:
08/12/2014
Application #:
13250481
Filing Dt:
09/30/2011
Title:
Load Store Unit With Load Miss Result Buffer
18
Patent #:
Issue Dt:
09/30/2014
Application #:
13250544
Filing Dt:
09/30/2011
Title:
OUTSTANDING LOAD MISS BUFFER WITH SHARED ENTRIES
19
Patent #:
Issue Dt:
07/29/2014
Application #:
13250596
Filing Dt:
09/30/2011
Title:
Load Miss Result Buffer With Shared Data Lines
20
Patent #:
Issue Dt:
06/24/2014
Application #:
13278701
Filing Dt:
10/21/2011
Title:
SYSTEM AND METHOD FOR UPDATING A DATA STRUCTURE
21
Patent #:
Issue Dt:
11/25/2014
Application #:
13278753
Filing Dt:
10/21/2011
Title:
SYSTEM AND METHOD FOR CONTROLLING UPDATES OF A DATA STRUCTURE
22
Patent #:
Issue Dt:
10/06/2015
Application #:
13278785
Filing Dt:
10/21/2011
Title:
SYSTEM AND METHOD FOR SEARCHING A DATA STRUCTURE
23
Patent #:
Issue Dt:
07/01/2014
Application #:
13396711
Filing Dt:
02/15/2012
Title:
PACKET FORWARDING SYSTEM AND METHOD USING PATRICIA TRIE CONFIGURED HARDWARE
24
Patent #:
Issue Dt:
05/10/2016
Application #:
13398679
Filing Dt:
02/16/2012
Title:
SYSTEM AND METHOD FOR PRE-FETCHING DATA BASED ON A FIFO QUEUE OF PACKET MESSAGES REACHING A FIRST CAPACITY THRESHOLD
25
Patent #:
Issue Dt:
12/10/2013
Application #:
13412679
Filing Dt:
03/06/2012
Title:
PSEUDO SINGLE-PHASE FLIP-FLOP (PSP-FF)
26
Patent #:
Issue Dt:
06/16/2015
Application #:
13422979
Filing Dt:
03/16/2012
Title:
METHOD AND APPARATUS FOR PERFORMING TABLE LOOKUP
27
Patent #:
Issue Dt:
03/08/2016
Application #:
13478100
Filing Dt:
05/22/2012
Title:
Multi-Level Store Merging in a Cache and Memory Hierarchy
28
Patent #:
Issue Dt:
03/24/2015
Application #:
13644924
Filing Dt:
10/04/2012
Publication #:
Pub Dt:
04/10/2014
Title:
MANAGING REQUESTS TO OPEN AND CLOSED BANKS IN A MEMORY SYSTEM
29
Patent #:
Issue Dt:
05/10/2016
Application #:
13644935
Filing Dt:
10/04/2012
Publication #:
Pub Dt:
04/10/2014
Title:
SCHEDULING MEMORY BANKS BASED ON MEMORY ACCESS PATTERNS
30
Patent #:
Issue Dt:
02/24/2015
Application #:
13726800
Filing Dt:
12/26/2012
Publication #:
Pub Dt:
06/26/2014
Title:
PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE
31
Patent #:
Issue Dt:
09/29/2015
Application #:
13752161
Filing Dt:
01/28/2013
Publication #:
Pub Dt:
07/31/2014
Title:
SYSTEMS AND METHODS FOR QUEUE REQUEST ORDERING WITHOUT STALLING REQUESTS IN ALIASING CONDITIONS BY USING A HASH INDEXED BASED TABLE
32
Patent #:
Issue Dt:
03/29/2016
Application #:
13772535
Filing Dt:
02/21/2013
Publication #:
Pub Dt:
08/21/2014
Title:
LARGE RECEIVE OFFLOAD FUNCTIONALITY FOR A SYSTEM ON CHIP
33
Patent #:
Issue Dt:
12/15/2015
Application #:
13799268
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
BROADCAST MESSAGING AND ACKNOWLEDGMENT MESSAGING FOR POWER MANAGEMENT IN A MULTIPROCESSOR SYSTEM
34
Patent #:
Issue Dt:
05/15/2018
Application #:
13838624
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
04/06/2017
Title:
VIRTUAL APPLIANCE ON A CHIP
35
Patent #:
Issue Dt:
10/27/2015
Application #:
13848377
Filing Dt:
03/21/2013
Publication #:
Pub Dt:
09/25/2014
Title:
DYNAMIC POWER CONTROL
36
Patent #:
Issue Dt:
05/12/2015
Application #:
13848828
Filing Dt:
03/22/2013
Publication #:
Pub Dt:
09/25/2014
Title:
CACHE MISS DETECTION FILTER
37
Patent #:
Issue Dt:
09/22/2015
Application #:
13863208
Filing Dt:
04/15/2013
Publication #:
Pub Dt:
10/16/2014
Title:
INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL
38
Patent #:
Issue Dt:
02/12/2019
Application #:
13953059
Filing Dt:
07/29/2013
Publication #:
Pub Dt:
01/29/2015
Title:
END-TO-END FLOW CONTROL IN SYSTEM ON CHIP INTERCONNECTS
39
Patent #:
Issue Dt:
06/14/2016
Application #:
13967607
Filing Dt:
08/15/2013
Publication #:
Pub Dt:
02/19/2015
Title:
ADDRESS INDEX RECOVERY USING HASH-BASED EXCLUSIVE OR
40
Patent #:
Issue Dt:
04/06/2021
Application #:
14045065
Filing Dt:
10/03/2013
Publication #:
Pub Dt:
04/09/2015
Title:
TCP SEGMENTATION OFFLOAD IN A SERVER ON A CHIP
41
Patent #:
Issue Dt:
01/30/2018
Application #:
14100228
Filing Dt:
12/09/2013
Publication #:
Pub Dt:
06/11/2015
Title:
ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR SYSTEM BASED ON PREDICTION OF AN INSTRUCTION PIPELINE HAZARD
42
Patent #:
Issue Dt:
02/19/2019
Application #:
14101948
Filing Dt:
12/10/2013
Publication #:
Pub Dt:
04/02/2015
Title:
MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE
43
Patent #:
Issue Dt:
03/07/2017
Application #:
14162903
Filing Dt:
01/24/2014
Publication #:
Pub Dt:
11/12/2015
Title:
FLOW PINNING IN A SERVER ON A CHIP
44
Patent #:
Issue Dt:
08/17/2021
Application #:
14203896
Filing Dt:
03/11/2014
Publication #:
Pub Dt:
11/12/2015
Title:
HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A BUFFER ASSOCIATED WITH BRANCH PREDICTION
45
Patent #:
Issue Dt:
02/14/2017
Application #:
14208408
Filing Dt:
03/13/2014
Publication #:
Pub Dt:
11/12/2015
Title:
HIGH FREQUENCY VOLTAGE SUPPLY MONITOR
46
Patent #:
NONE
Issue Dt:
Application #:
14243949
Filing Dt:
04/03/2014
Publication #:
Pub Dt:
11/05/2015
Title:
IMPLEMENTATION OF LOAD ACQUIRE/STORE RELEASE INSTRUCTIONS USING LOAD/STORE OPERATION WITH DMB OPERATION
47
Patent #:
Issue Dt:
06/04/2019
Application #:
14264716
Filing Dt:
04/29/2014
Publication #:
Pub Dt:
11/12/2015
Title:
SYSTEMS AND METHODS FACILITATING MULTI-WORD ATOMIC OPERATION SUPPORT FOR SYSTEM ON CHIP ENVIRONMENTS
48
Patent #:
Issue Dt:
07/24/2018
Application #:
14482780
Filing Dt:
09/10/2014
Publication #:
Pub Dt:
12/17/2015
Title:
PULSE-LATCH BASED BUS DESIGN FOR INCREASED BANDWIDTH
49
Patent #:
Issue Dt:
03/27/2018
Application #:
14497619
Filing Dt:
09/26/2014
Publication #:
Pub Dt:
03/31/2016
Title:
PRIORITY FRAMEWORK FOR A COMPUTING DEVICE
50
Patent #:
Issue Dt:
09/12/2017
Application #:
14519271
Filing Dt:
10/21/2014
Title:
FLEXIBLE AND ROBUST POWER GRID CONNECTIVITY
51
Patent #:
Issue Dt:
09/25/2018
Application #:
14566945
Filing Dt:
12/11/2014
Publication #:
Pub Dt:
06/16/2016
Title:
GENERATING AND/OR EMPLOYING A DESCRIPTOR ASSOCIATED WITH A MEMORY TRANSLATION TABLE
52
Patent #:
Issue Dt:
08/15/2017
Application #:
14666771
Filing Dt:
03/24/2015
Publication #:
Pub Dt:
09/29/2016
Title:
MAIN MEMORY PREFETCH OPERATION AND MULTIPLE PREFETCH OPERATION
53
Patent #:
Issue Dt:
05/15/2018
Application #:
14710837
Filing Dt:
05/13/2015
Publication #:
Pub Dt:
11/17/2016
Title:
PREFETCH TAG FOR EVICTION PROMOTION
54
Patent #:
Issue Dt:
09/06/2016
Application #:
14736882
Filing Dt:
06/11/2015
Title:
HIGH EFFICIENCY HALF-CROSS-COUPLED DECOUPLING CAPACITOR
55
Patent #:
Issue Dt:
08/01/2017
Application #:
14796167
Filing Dt:
07/10/2015
Publication #:
Pub Dt:
01/12/2017
Title:
SYSTEMS AND METHODS FACILITATING REDUCED LATENCY VIA STASHING IN SYSTEM ON CHIPS
56
Patent #:
Issue Dt:
06/12/2018
Application #:
14838778
Filing Dt:
08/28/2015
Publication #:
Pub Dt:
03/02/2017
Title:
PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY
57
Patent #:
Issue Dt:
05/08/2018
Application #:
15015338
Filing Dt:
02/04/2016
Title:
MULTIPLE-QUEUE INTEGER COALESCING MAPPING ALGORITHM WITH SHARED BASED TIME
58
Patent #:
Issue Dt:
12/04/2018
Application #:
15068737
Filing Dt:
03/14/2016
Publication #:
Pub Dt:
09/14/2017
Title:
SELF-REFERENCED ON-DIE VOLTAGE DROOP DETECTOR
59
Patent #:
Issue Dt:
10/24/2017
Application #:
15098573
Filing Dt:
04/14/2016
Title:
DATA MANAGMENT FOR CACHE MEMORY
60
Patent #:
Issue Dt:
01/23/2018
Application #:
15149244
Filing Dt:
05/09/2016
Title:
MIMCAP CREATION AND UTILIZATION METHODOLOGY
61
Patent #:
Issue Dt:
06/11/2019
Application #:
15149249
Filing Dt:
05/09/2016
Title:
EFFICIENT TECHNIQUES FOR PROCESS VARIATION REDUCTION FOR STATIC TIMING ANALYSIS
62
Patent #:
Issue Dt:
01/31/2017
Application #:
15157597
Filing Dt:
05/18/2016
Publication #:
Pub Dt:
09/08/2016
Title:
RETRIEVAL HASH INDEX
63
Patent #:
Issue Dt:
10/27/2020
Application #:
15250966
Filing Dt:
08/30/2016
Title:
MANAGING A DATA PACKET FOR AN OPERATING SYSTEM ASSOCIATED WITH A MULTI-NODE SYSTEM
64
Patent #:
Issue Dt:
07/09/2019
Application #:
15256787
Filing Dt:
09/06/2016
Title:
CLOCK CONTROL BASED ON VOLTAGE ASSOCIATED WITH A MICROPROCESSOR
65
Patent #:
Issue Dt:
10/08/2019
Application #:
15351477
Filing Dt:
11/15/2016
Title:
MEMORY PAGE REQUEST FOR OPTIMIZING MEMORY PAGE LATENCY ASSOCIATED WITH NETWORK NODES
66
Patent #:
Issue Dt:
07/02/2019
Application #:
15366251
Filing Dt:
12/01/2016
Publication #:
Pub Dt:
06/07/2018
Title:
OPTIMIZING MEMORY MAPPING(S) ASSOCIATED WITH NETWORK NODES
67
Patent #:
Issue Dt:
08/14/2018
Application #:
15372581
Filing Dt:
12/08/2016
Publication #:
Pub Dt:
06/14/2018
Title:
WRITE ASSIST FOR MEMORIES WITH RESISTIVE BIT LINES
68
Patent #:
Issue Dt:
02/12/2019
Application #:
15384437
Filing Dt:
12/20/2016
Publication #:
Pub Dt:
06/21/2018
Title:
METHOD TO DYNAMICALLY INJECT ERRORS IN A REPAIRABLE MEMORY ON SILICON AND A METHOD TO VALIDATE BUILT-IN-SELF-REPAIR LOGIC
69
Patent #:
Issue Dt:
06/11/2019
Application #:
15414739
Filing Dt:
01/25/2017
Publication #:
Pub Dt:
07/26/2018
Title:
TECHNIQUES FOR STATISTICAL FREQUENCY ENHANCEMENT OF STATICALLY TIMED DESIGNS
70
Patent #:
Issue Dt:
12/25/2018
Application #:
15444478
Filing Dt:
02/28/2017
Title:
VARIATION IMMUNE ON-DIE VOLTAGE DROOP DETECTOR
71
Patent #:
Issue Dt:
08/06/2019
Application #:
15712519
Filing Dt:
09/22/2017
Title:
DATA MANAGMENT FOR CACHE MEMORY
Assignor
1
Exec Dt:
11/29/2017
Assignee
1
4555 GREAT AMERICA PKWY #601
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
ALSTON & BIRD LLP
BANK OF AMERICA PLAZA
101 SOUTH TRYON STREET, SUITE 4000
CHARLOTTE, NC 28280-4000

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