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Total properties:
14
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09148265
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Filing Dt:
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09/04/1998
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Title:
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HIGH SPEED BUMP PLATING/FORMING
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09184861
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Filing Dt:
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11/03/1998
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Title:
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STEPPER ALIGNMENT MARK STRUCTURE FOR MAINTAINING ALIGNMENT INTEGRITY
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09430476
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Filing Dt:
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10/29/1999
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Title:
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METHOD AND APPARATUS FOR FAULT DETECTION OF A PROCESSING TOOL IN AN ADVANCED PROCESS CONTROL (APC) FRAMEWORK
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09487493
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Filing Dt:
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01/19/2000
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Title:
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Stepper alignment mark structure for maintaining alignment integrity
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09562659
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Filing Dt:
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05/02/2000
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Title:
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HARDMASK TRIM PROCESS
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09799408
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Filing Dt:
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03/05/2001
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Title:
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METHOD AND APPARATUS FOR THE INTEGRATION OF SENSOR DATA FROM A PROCESS TOOL IN AN ADVANCED PROCESS CONTROL (APC) FRAMEWORK
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09874175
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Filing Dt:
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06/04/2001
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Title:
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INTEGRATED CIRCUIT WITH DIELECTRIC DIFFUSION BARRIER LAYER FORMED BETWEEN INTERCONNECTS AND INTERLAYER DIELECTRIC LAYERS
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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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10058227
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Filing Dt:
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01/29/2002
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Title:
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METHOD FOR FORMING AN INTERCONNECT STRUCTURE USING A CVD ORGANIC BARC TO MITIGATE VIA POISONING
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10135702
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Filing Dt:
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04/30/2002
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Title:
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ELECTROCHEMICALLY GENERATED REACTANTS FOR CHEMICAL MECHANICAL PLANARIZATION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10226520
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Filing Dt:
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08/22/2002
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Title:
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METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT WITH DIELECTRIC DIFFUSION BARRIER LAYER FORMED BETWEEN INTERCONNECTS AND INTERLAYER DIELECTRIC LAYERS
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10608883
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Filing Dt:
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06/26/2003
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Title:
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INTEGRATED CIRCUIT WITH DIELECTRIC DIFFUSION BARRIER LAYER FORMED BETWEEN INTERCONNECTS AND INTERLAYER DIELECTRIC LAYERS
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12110798
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Filing Dt:
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04/28/2008
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Publication #:
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Pub Dt:
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08/21/2008
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Title:
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INTEGRATED PACKAGE CIRCUIT WITH STIFFENER
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12553336
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Filing Dt:
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09/03/2009
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Publication #:
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Pub Dt:
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03/03/2011
| | | | |
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Title:
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SEMICONDUCTOR CHIP WITH CONTOURED SOLDER STRUCTURE OPENING
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13363620
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Filing Dt:
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02/01/2012
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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INTEGRATED CIRCUIT PACKAGE STRIP WITH STIFFENER
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