Patent Assignment Details
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| Reel/Frame: | 044803/0449 | |
| Pages: | 5 |
| | Recorded: | 11/27/2017 | | |
| Attorney Dkt #: | MEIGI-MEI2PC171127 |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09345485
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Filing Dt:
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07/01/1999
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Title:
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METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE, STORAGE MEDIUM HAVING STORED THEREON PROGRAM FOR EXECUTING THE LAYOUT DESIGNING METHOD, AND SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/25/2007
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Application #:
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10820033
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Filing Dt:
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04/08/2004
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Publication #:
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Pub Dt:
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10/21/2004
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Title:
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VOLTAGE BOOSTER POWER SUPPLY CIRCUIT
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10864814
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Filing Dt:
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06/10/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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SEMICONDUCTOR APPARATUS CAPABLE OF PERFORMING REFRESH CONTROL
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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11004909
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Filing Dt:
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12/07/2004
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Publication #:
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Pub Dt:
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06/16/2005
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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11131385
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Filing Dt:
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05/18/2005
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Publication #:
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Pub Dt:
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09/22/2005
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND MULTI-CHIP MODULE COMPRISING THE SEMICONDUCTOR MEMORY DEVICE
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Assignee
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| 1006, OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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PANASONIC CORPORATION
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2-1-61, SHIROMI, CHUO-KU
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7F OBP PANASONIC TOWER
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OSAKA, 540-6207 JAPAN
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