|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1992
|
Application #:
|
07591646
|
Filing Dt:
|
10/02/1990
|
|
Title:
|
STRUCTURE FOR FILTERING CVD CHAMBER PROCESS GASES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1993
|
Application #:
|
07592014
|
Filing Dt:
|
10/02/1990
|
|
Title:
|
APPARATUS FOR CONDUCTING A REFRACTORY METAL DEPOSITION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
07707365
|
Filing Dt:
|
05/30/1991
|
|
Title:
|
METHOD FOR FORMING SELF ALIGNED POLYSILICON CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
07719699
|
Filing Dt:
|
06/25/1991
|
|
Title:
|
DIELECTRIC FILM DEPOSITION METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/1995
|
Application #:
|
07739773
|
Filing Dt:
|
07/29/1991
|
|
Title:
|
TUNGSTEN DEPOSITION PROCESS FOR LOW CONTACT RESISTIVITY TO SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1993
|
Application #:
|
07794780
|
Filing Dt:
|
11/18/1991
|
|
Title:
|
METHOD FOR PERFORMING IN-SITU ETCH OF A CVD CHAMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1993
|
Application #:
|
07809104
|
Filing Dt:
|
12/12/1991
|
|
Title:
|
APPARATUS FOR PERFORMING IN-SITU ETCH OF CVD CHAMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/1997
|
Application #:
|
07866942
|
Filing Dt:
|
04/03/1992
|
|
Title:
|
FET WITH GATE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
08079310
|
Filing Dt:
|
06/17/1993
|
|
Title:
|
PROCESSES USING PHOTOSENSITIVE MATERIALS INCLUDING A NITRO BENZYL ESTER PHOTOACID GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/1995
|
Application #:
|
08150261
|
Filing Dt:
|
11/17/1993
|
|
Title:
|
ACTIVE NEURAL NETWORK CONTROL OF WAFER ATTRIBUTES IN A PLASMA ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08156953
|
Filing Dt:
|
11/19/1993
|
|
Title:
|
CONDUCTIVE OXIDE FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08163967
|
Filing Dt:
|
12/08/1993
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A HIGH VOLTAGE TERMINATION IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
08199910
|
Filing Dt:
|
02/22/1994
|
|
Title:
|
SEMI-INSULATED INDIUM PHOSPHIDE BASED COMPOSITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/1997
|
Application #:
|
08233607
|
Filing Dt:
|
04/22/1994
|
|
Title:
|
TECHNIQUES FOR FORMING SUPERCONDUCTIVE LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
08259575
|
Filing Dt:
|
06/14/1994
|
|
Title:
|
METHOD OF FORMING SOURCE AND DRAIN REGIONS FOR CMOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/1996
|
Application #:
|
08277344
|
Filing Dt:
|
07/19/1994
|
|
Title:
|
INTEGRATED CIRCUIT WITH ON-CHIP GROUND PLANE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
08278688
|
Filing Dt:
|
07/21/1994
|
|
Title:
|
METHOD COMPRISING REMOVAL OF MATERIAL FROM A DIAMOND FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/1995
|
Application #:
|
08283296
|
Filing Dt:
|
07/29/1994
|
|
Title:
|
UNIFORM AND REPEATABLE PLASMA PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/1995
|
Application #:
|
08286606
|
Filing Dt:
|
08/05/1994
|
|
Title:
|
METHOD OF ETCHING SILICON NITRIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/1996
|
Application #:
|
08316745
|
Filing Dt:
|
10/03/1994
|
|
Title:
|
INSPECTION APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
08324842
|
Filing Dt:
|
10/18/1994
|
|
Title:
|
PROCESS FOR THE ELECTROLESS DEPOSITION OF METAL ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/1996
|
Application #:
|
08326444
|
Filing Dt:
|
10/20/1994
|
|
Title:
|
DEVICE FABRICATION USING DUV/EUV PATTERN DELINEATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08331458
|
Filing Dt:
|
10/31/1994
|
|
Title:
|
FIELD EMISSION DEVICES EMPLOYING ENHANCED DIAMOND FIELD EMITTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/1997
|
Application #:
|
08332179
|
Filing Dt:
|
10/31/1994
|
|
Title:
|
ELECTRON FIELD EMITTERS COMPRISING PARTICLES COATED WITH LOW VOLTAGE EMITTING MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/1997
|
Application #:
|
08344318
|
Filing Dt:
|
11/22/1994
|
|
Title:
|
METHOD FOR MANUFACTURING GATE OXIDE CAPACITORS INCLUDING WAFER BACKSIDE DIELECTRIC AND IMPLANTATION ELECTRON FLOOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/1996
|
Application #:
|
08344785
|
Filing Dt:
|
11/22/1994
|
|
Title:
|
SINGLE-POLYSILICON CMOS ACTIVE PIXEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/1996
|
Application #:
|
08346806
|
Filing Dt:
|
11/30/1994
|
|
Title:
|
MINIENVIRONMENT FOR HAZARDOUS PROCESS TOOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/1995
|
Application #:
|
08346810
|
Filing Dt:
|
11/30/1994
|
|
Title:
|
METHOD AND APPARATUS FOR PLANAR MAGNETRON SPUTTERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
08347527
|
Filing Dt:
|
11/30/1994
|
|
Title:
|
PROCESS FOR FORMING ISOLATION REGIONS IN AN INTEGRATED CIRCUIT AND STRUCTURE FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/1996
|
Application #:
|
08350439
|
Filing Dt:
|
12/06/1994
|
|
Title:
|
HIGH Q INTEGRATED INDUCTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/1997
|
Application #:
|
08351516
|
Filing Dt:
|
12/07/1994
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08351977
|
Filing Dt:
|
12/08/1994
|
|
Title:
|
POLY-BUFFERED LOCOS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/1996
|
Application #:
|
08353015
|
Filing Dt:
|
12/09/1994
|
|
Title:
|
METHOD FOR MAKING A METAL TO METAL CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/1996
|
Application #:
|
08353032
|
Filing Dt:
|
12/09/1994
|
|
Title:
|
ARTICLE COMPRISING A THIN FILM TRANSISTOR WITH LOW CONDUCTIVITY ORGANIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08355787
|
Filing Dt:
|
12/14/1994
|
|
Title:
|
METHODOLOGY FOR MONITORING SOLVENT QUALITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/1997
|
Application #:
|
08357728
|
Filing Dt:
|
12/13/1994
|
|
Title:
|
USE OF RETICLE STITCHING TO PROVIDE DESIGN FLEXIBILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/1998
|
Application #:
|
08361616
|
Filing Dt:
|
12/22/1994
|
|
Title:
|
METHOD OF MAKING FIELD EMISSION DEVICES EMPLOYING ULTRA-FINE DIAMOND PARTICLE EMITTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/1996
|
Application #:
|
08362616
|
Filing Dt:
|
12/22/1994
|
|
Title:
|
INTEGRATED CIRCUIT FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/1996
|
Application #:
|
08366515
|
Filing Dt:
|
12/30/1994
|
|
Title:
|
REVERSE SIDE ETCHING FOR PRODUCING LAYERS WITH STRAIN VARIATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/1996
|
Application #:
|
08366529
|
Filing Dt:
|
12/30/1994
|
|
Title:
|
MULTIPLE LAYER TUNGSTEN DEPOSITION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08366952
|
Filing Dt:
|
12/30/1994
|
|
Title:
|
SELF-ALIGNED OPAQUE REGIONS FOR ATTENUATING PHASE-SHIFTING MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/1996
|
Application #:
|
08370902
|
Filing Dt:
|
01/10/1995
|
|
Title:
|
METHOD FOR MAKING MULTICHIP CIRCUITS USING ACTIVE SEMICONDUCTOR SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/1997
|
Application #:
|
08373732
|
Filing Dt:
|
01/17/1995
|
|
Title:
|
LASER-ASSISTED PARTICLE ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/1997
|
Application #:
|
08374193
|
Filing Dt:
|
01/18/1995
|
|
Title:
|
PROCESS FOR SELECTIVE DEPOSITION OF POLYSILICON OVER SINGLE CRYSTAL SILICON SUBSTRATE AND RESULTING PRODUCT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08374195
|
Filing Dt:
|
01/18/1995
|
|
Title:
|
IMPROVED MOS STRUCTURE WITH HOT CARRIER REDUCTION ME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08378027
|
Filing Dt:
|
01/24/1995
|
|
Title:
|
BARRIER METAL TECHNOLOGY FOR TUNGSTEN PLUG INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08380774
|
Filing Dt:
|
01/31/1995
|
|
Title:
|
MULTILAYER PILLAR STRUCTURE FOR IMPROVED FIELD EMISSION DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/1996
|
Application #:
|
08381262
|
Filing Dt:
|
01/31/1995
|
|
Title:
|
FIELD EMISSION DISPLAY HAVING CORRUGATED SUPPORT PILLARS AND METHOD FOR MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/1997
|
Application #:
|
08381375
|
Filing Dt:
|
01/31/1995
|
|
Title:
|
FIELD EMISSION DEVICES EMPLOYING ACTIVATED DIAMOND PARTICLE EMITTERS AND METHODS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08390329
|
Filing Dt:
|
02/17/1995
|
|
Title:
|
FILTERING TECHNIQUE FOR CVD CHAMBER PROCESS GASES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08393494
|
Filing Dt:
|
03/02/1995
|
|
Title:
|
ARTICLE COMPRISING ALPHA-HEXATHIENYL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/1996
|
Application #:
|
08396560
|
Filing Dt:
|
03/01/1995
|
|
Title:
|
MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING HEXAGONAL SEMICONDUCTOR "OR" GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08410375
|
Filing Dt:
|
03/27/1995
|
|
Title:
|
BICMOS COMPACTED LOGIC ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08412678
|
Filing Dt:
|
03/29/1995
|
|
Title:
|
METHOD FOR SUPPLYING PHOSPHOROUS VAPOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08413527
|
Filing Dt:
|
03/30/1995
|
|
Title:
|
INTEGRATED CIRCUIT MULTI-LEVEL INTERCONNECTION TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/1999
|
Application #:
|
08430084
|
Filing Dt:
|
04/27/1995
|
|
Title:
|
TRANSISTOR FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1997
|
Application #:
|
08431355
|
Filing Dt:
|
04/28/1995
|
|
Title:
|
REDUCED STRESS TUNGSTEN DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08434673
|
Filing Dt:
|
05/04/1995
|
|
Title:
|
PROCESS FOR MAKING GROUP IV SEMICONDUCTOR SUBSTRATE TREATED WITH ONE OR MORE GROUP IV ELEMENTS TO FORM ONE OR MORE BARRIER REGIONS CAPABLE OF INHIBITING MIGRATION OF DOPANT MATERILS IN SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/1996
|
Application #:
|
08439040
|
Filing Dt:
|
04/10/1995
|
|
Title:
|
SELF-ALIGNED ALIGNMENT MARKS FOR PHASE-SHIFTING MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08446122
|
Filing Dt:
|
05/19/1995
|
|
Title:
|
ACTIVE NEURAL NETWORK DETERMINATION OF ENDPOINT IN A PLASMA ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/1997
|
Application #:
|
08454542
|
Filing Dt:
|
05/30/1995
|
|
Title:
|
METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE WITH A SUPERCONDUCTIVE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08468167
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
ACTIVE NEURAL NETWORK CONTROL OF WAFER ATTRIBUTES IN A PLASMA ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08472033
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
INTEGRATED CIRCUIT CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08475028
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
METHOD OF FORMING AN MOS-TYPE INTEGRATED CIRCUIT STRUCTURE WITH A DIODE FORMED IN THE SUBSTRATE UNDER A POLYSILICON GATE ELECTRODE TO CONSERVE SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08475586
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SILICON CONTROLLED RECTIFIER (SCR) WITH CAPACITIVE TRIGGER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/1998
|
Application #:
|
08478133
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
METHD OF MAKING PMOSFETS HAVING INDIUM OR GALLIUM DOPED BURIED CHAN- NELS AND N+POLYSILICON GATES AND CMOS DEVICES FABRICATED THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/1998
|
Application #:
|
08484675
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SEGMENTED EMITTER LOW NOISE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08486803
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SILICIDATION PROCESS WITH ETCH STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08488075
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SELF-ALIGNED TWIN WELL PROCESS HAVING A SIO2-POLYSILICON-SIO2 BARRIER MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08497470
|
Filing Dt:
|
06/30/1995
|
|
Title:
|
DOPING OF SILICON LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/1996
|
Application #:
|
08502566
|
Filing Dt:
|
07/13/1995
|
|
Title:
|
COMBINED JFET & MOS TRANSISTOR DEVICE, CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1997
|
Application #:
|
08509678
|
Filing Dt:
|
07/31/1995
|
|
Title:
|
METHOD OF DETERMINING THE THERMAL RESISTIVITY OF ELECTRICALLY INSULATING CRYSTALLINE MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08509930
|
Filing Dt:
|
08/01/1995
|
|
Title:
|
COMBINED PHOTOGATE AND PHOTODIODE ACTIVE PIXEL IMAGE SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08512678
|
Filing Dt:
|
08/08/1995
|
|
Title:
|
AUTOMATING PHOTOLITHOGRAPHY IN THE FABRICATION OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08516060
|
Filing Dt:
|
08/17/1995
|
|
Title:
|
HIGH RESOLUTION REMOTE POSITION DETECTION USING SEGMENTED GRATINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1997
|
Application #:
|
08520030
|
Filing Dt:
|
08/28/1995
|
|
Title:
|
LEAK DETECTION SYSTEM FOR A GAS MANIFOLD OF A CHEMICAL VAPOR DEPOSITION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1996
|
Application #:
|
08521795
|
Filing Dt:
|
08/31/1995
|
|
Title:
|
IMPLANTATION OF A SEMICONDUCTOR SUBSTRATE WITH CONTROLLED AMOUNT OF NOBLE GAS IONS TO REDUCE CHANNELING AND/OR DIFFUSION OF A BORON DOPANT SUBSEQUENTLY IMPLANTED INTO THE SUBSTRATE TO FORM P- LDD REGION OF A PMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08534008
|
Filing Dt:
|
09/26/1995
|
|
Title:
|
ANTIFUSE DEVICE FOR USE ON A FIELD PROGRAMMABLE INTERCONNECT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/1997
|
Application #:
|
08534356
|
Filing Dt:
|
09/27/1995
|
|
Title:
|
SELF-POWERED DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/1996
|
Application #:
|
08538317
|
Filing Dt:
|
10/03/1995
|
|
Title:
|
COMPENSATION OF THE TEMPERATURE COEFFICIENT OF THE DIELECTRIC CONSTANT OF BARIUM STRONTIUM TITANATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08552461
|
Filing Dt:
|
11/09/1995
|
|
Title:
|
PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE COMPRISING LOCAL AREA INTERCONNECTS FORMED OVER SEMICONDUCTOR SUBSTRATE BY SELECTIVE DEPOSITION ON SEED LAYER IN PATTERNED TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/1997
|
Application #:
|
08555594
|
Filing Dt:
|
11/09/1995
|
|
Title:
|
FIELD EMISSION DEVICES EMPLOYING IMPROVED EMITTERS ON METAL FOIL AND METHODS FOR MAKING SUCH DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08558997
|
Filing Dt:
|
11/16/1995
|
|
Title:
|
PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/1997
|
Application #:
|
08561107
|
Filing Dt:
|
11/21/1995
|
|
Title:
|
MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR CMOS "NAND" GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08561473
|
Filing Dt:
|
11/21/1995
|
|
Title:
|
METHOD OF FORMING A DMOS-CONTROLLED LATERAL BIOPOLAR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1998
|
Application #:
|
08562235
|
Filing Dt:
|
11/21/1995
|
|
Title:
|
BIPOLAR TRANSISTOR WITH MOS-CONTROLLED PROTECTION FOR REVERSE-BIASED EMITTER-BASED JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
08563688
|
Filing Dt:
|
11/28/1995
|
|
Title:
|
PROCESS FOR CONTROLLING DOPANT DIFFUSION IN A SEMICONDUCTOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/1997
|
Application #:
|
08566445
|
Filing Dt:
|
12/01/1995
|
|
Title:
|
ENERGY SENSITIVE RESIST MATERIAL AND PROCESS FOR DEVICE FABRICATION USING THE RESIST MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08568040
|
Filing Dt:
|
12/06/1995
|
|
Title:
|
PROCESS FOR FORMING INTEGRATED CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08570429
|
Filing Dt:
|
12/11/1995
|
|
Title:
|
INTEGRATED CIRCUIT FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/1997
|
Application #:
|
08572196
|
Filing Dt:
|
12/14/1995
|
|
Title:
|
COMPLEMENTARY TFT DEVICES WITH DIODE-EFFECT ELIMINATION MEANS INDEPENDENT OF TFT-CHANNEL GEOMETRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08572599
|
Filing Dt:
|
12/14/1995
|
|
Title:
|
CASSETTE LIGHT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/1997
|
Application #:
|
08573923
|
Filing Dt:
|
12/18/1995
|
|
Title:
|
METHOD OF FORMING VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
08577077
|
Filing Dt:
|
12/22/1995
|
|
Title:
|
INTEGRATED CIRCUIT PROCESSING UTILIZING MICROWAVE RADIATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/1997
|
Application #:
|
08580674
|
Filing Dt:
|
12/29/1995
|
|
Title:
|
METHOD FOR POLISHING A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08581665
|
Filing Dt:
|
12/29/1995
|
|
Title:
|
METHOD FOR MAKING BIPOLAR TRANSISTORS HAVING INDIUM DOPED BASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
08586587
|
Filing Dt:
|
01/11/1996
|
|
Title:
|
SIDEWALL STRUCTURE FOR METAL INTERCONNECT AND METHOD OF MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
08587061
|
Filing Dt:
|
01/16/1996
|
|
Title:
|
TRANSISTOR FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/1997
|
Application #:
|
08587426
|
Filing Dt:
|
01/16/1996
|
|
Title:
|
ARTICLE COMPRISING COMPLEMENTARY CIRCUIT WITH INORGANIC N-CHANNEL AND ORGANIC P-CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/1997
|
Application #:
|
08589229
|
Filing Dt:
|
01/22/1996
|
|
Title:
|
PROCESS FOR MAKING AN X-RAY MASK
|
|
