|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09280103
|
Filing Dt:
|
03/29/1999
|
Title:
|
DEVICE COMPRISING N-CHANNEL SEMICONDUCTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09280387
|
Filing Dt:
|
03/29/1999
|
Title:
|
CAPACITOR FOR AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09281642
|
Filing Dt:
|
03/31/1999
|
Title:
|
MANUFACTURING AND ENGINEERING DATA BASE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09283528
|
Filing Dt:
|
04/01/1999
|
Title:
|
LITHOGRAPHIC PROCESS FOR DEVICE FABRICATION USING DARK-FIELD ILLUMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09286430
|
Filing Dt:
|
04/06/1999
|
Title:
|
MOBIUS STRIP BELT FOR LINEAR CMP TOOLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09286869
|
Filing Dt:
|
04/06/1999
|
Title:
|
APPARATUS AND METHOD FOR CONTINUOUS DELIVERY AND CONDITIONING OF A POLISHING SLURRY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09291781
|
Filing Dt:
|
04/14/1999
|
Title:
|
EMBEDDED THIN FILM PASSIVE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09292079
|
Filing Dt:
|
04/14/1999
|
Title:
|
REDUCTION OF PLASMA DAMAGE AT CONTACT ETCH IN MOS INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09292860
|
Filing Dt:
|
04/16/1999
|
Title:
|
MICROMAGNETIC DEVICE HAVING AN ANISOTROPIC FERROMAGNETIC CORE AND METHOD OF MANUFACTURE THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09296001
|
Filing Dt:
|
04/21/1999
|
Publication #:
|
|
Pub Dt:
|
01/03/2002
| | | | |
Title:
|
DEVICE COMPRISING THERMALLY STABLE, LOW DIELECTRIC CONSTANT MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09298068
|
Filing Dt:
|
04/22/1999
|
Title:
|
METHOD OF FORMING A MULTI-LAYERED DUAL-POLYSILICON STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09305722
|
Filing Dt:
|
05/05/1999
|
Title:
|
HIGH-RESOLUTION METHOD FOR PATTERNING A SUBSTRATE WITH MICRO-PRINTING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
09310388
|
Filing Dt:
|
05/12/1999
|
Title:
|
DAMASCENE CAPACITORS FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09310701
|
Filing Dt:
|
05/07/1999
|
Title:
|
IMPROVED WEHNELT GUN FOR ELECTRON LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09311631
|
Filing Dt:
|
05/14/1999
|
Publication #:
|
|
Pub Dt:
|
01/03/2002
| | | | |
Title:
|
OXIDATION OF SILICON USING FLUORINE IMPLANT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09312386
|
Filing Dt:
|
05/14/1999
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
Title:
|
STEPPED ETALON
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09332216
|
Filing Dt:
|
06/14/1999
|
Title:
|
WAFER CARRIER MODIFICATION FOR REDUCED EXTRACTION FORCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09333626
|
Filing Dt:
|
06/15/1999
|
Title:
|
PROCESS AND APPARATUS FOR MAKING COMPOSITE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09334977
|
Filing Dt:
|
06/17/1999
|
Title:
|
LAYERED DIELECTRIC FILM STRUCTURE SUITABLE FOR GATE DIELECTRIC APPLICATION IN SUB-0.25 uM TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09335707
|
Filing Dt:
|
06/18/1999
|
Title:
|
PROCESS FOR FABRICATING VERTICAL TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09338143
|
Filing Dt:
|
06/22/1999
|
Title:
|
INTEGRATED CIRCUIT HAVING A MICROMAGNETIC DEVICE INCLUDING A FERROMAGNETIC CORE AND METHOD OF MANUFACTURE THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
09338520
|
Filing Dt:
|
06/23/1999
|
Title:
|
CATHODE WITH IMPROVED WORK FUNCTION AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
09339306
|
Filing Dt:
|
06/23/1999
|
Title:
|
METHOD OF MAKING INTEGRATED CIRCUITS WITH TUB-TIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09345039
|
Filing Dt:
|
06/30/1999
|
Title:
|
METHOD FOR MAKING AN INTEGRATED CIRCUIT INCLUDING ALIGNMENT MARKS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09345556
|
Filing Dt:
|
06/30/1999
|
Title:
|
METHOD FOR MAKING AN INTEGRATED CIRCUIT CAPACITOR INCLUDING TANTALUM PENTOXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09347313
|
Filing Dt:
|
07/02/1999
|
Title:
|
METHOD ANALYZING A SEMICONDUCTOR SURFACE USING LINE WIDTH METROLOGY WITH AUTO-CORRELATION OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09347487
|
Filing Dt:
|
07/02/1999
|
Title:
|
METHOD FOR MANUFACTURING A METAL-TO-METAL CAPACITOR UTILIZING ONLY ONE MASKING STEP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09354657
|
Filing Dt:
|
07/16/1999
|
Title:
|
VERY LOW MAGNETIC FIELD INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09356396
|
Filing Dt:
|
07/16/1999
|
Title:
|
ZONE PLATES FOR X-RAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09358606
|
Filing Dt:
|
07/21/1999
|
Title:
|
OFF-AXIS PUPIL APERTURE AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09362648
|
Filing Dt:
|
07/27/1999
|
Title:
|
PRE-CONDITIONING POLISHING PADS FOR CHEMICAL-MECHANICAL POLISHING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09363758
|
Filing Dt:
|
07/29/1999
|
Title:
|
METHOD FOR PRODUCING ORIENTED PIEZOELECTRIC FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09363781
|
Filing Dt:
|
07/29/1999
|
Title:
|
MONOLITHIC RESISTOR HAVING DYNAMICALLY CONTROLLABLE IMPEDANCE AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09364366
|
Filing Dt:
|
07/30/1999
|
Title:
|
METHOD OF MAKING INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09364367
|
Filing Dt:
|
07/30/1999
|
Title:
|
INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUG
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09365440
|
Filing Dt:
|
08/02/1999
|
Title:
|
METHOD OF SINGLE STEP DAMASCENE PROCESS FOR DEPOSITION AND GLOBAL PLANARIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09366388
|
Filing Dt:
|
08/03/1999
|
Title:
|
METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09369802
|
Filing Dt:
|
08/06/1999
|
Title:
|
FIELD EMITTING DEVICE COMPRISING FIELD-CONCENTRATING NANOCONDUCTOR ASSEMBLY AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09370501
|
Filing Dt:
|
08/09/1999
|
Title:
|
LOW THRESHOLD VOLTAGE MOS TRANSISTOR AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09370912
|
Filing Dt:
|
08/06/1999
|
Title:
|
METHOD OF MAKING A SEMICONDUCTOR WITH COPPER PASSIVATING FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09370963
|
Filing Dt:
|
08/10/1999
|
Title:
|
USE OF A GETTER LAYER TO IMPROVE METAL TO METAL CONTACT RESISTANCE AT LOW RADIO FREQUENCY POWER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09375150
|
Filing Dt:
|
08/16/1999
|
Title:
|
SILICON-GERMANIUM TRANSISTOR AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09376233
|
Filing Dt:
|
08/17/1999
|
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING A PLANAR INTERLEVEL DIELECTRIC LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09376696
|
Filing Dt:
|
08/18/1999
|
Title:
|
WAFER CARRIER HEAD FOR PREVENTION OF UNINTENTIONAL SEMICONDUCTOR WAFER ROTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09377386
|
Filing Dt:
|
08/19/1999
|
Title:
|
DIFFUSION PREVENTING BARRIER LAYER IN INTEGRATED CIRCUIT INTER-METAL LAYER DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09378856
|
Filing Dt:
|
08/23/1999
|
Title:
|
PROCESS FOR DEUTERIUM PASSIVATION AND HOT CARRIER IMMUNITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09382611
|
Filing Dt:
|
08/25/1999
|
Title:
|
GLOVE BOX FILTER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09388166
|
Filing Dt:
|
09/01/1999
|
Title:
|
PROCESS FOR FABRICATING ARTICLE HAVING SUBSTANTIAL THREE-DIMENSIONAL ORDER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09388203
|
Filing Dt:
|
09/01/1999
|
Title:
|
STACKED VIA KELVIN RESISTANCE TEST STRUCTURE FOR MEASURING CONTACT ANOMALIES IN MULTI-LEVEL METAL INTEGRATED CIRCUIT TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09388297
|
Filing Dt:
|
09/01/1999
|
Title:
|
SEMICONDUCTOR DEVICE HAVING REGIONS OF INSULATING MATERIAL FORMED IN A SEMICONDUCTOR SUBSTRATE AND PROCESS OF MAKING THE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09390181
|
Filing Dt:
|
09/07/1999
|
Title:
|
PLASMA CONFINEMENT SHIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09393032
|
Filing Dt:
|
09/09/1999
|
Title:
|
Method For Fabricating Molded Microstructures On Substrates
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09395062
|
Filing Dt:
|
09/13/1999
|
Title:
|
ALIGNMENT OF OPENINGS IN SEMICONDUCTOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09395507
|
Filing Dt:
|
09/14/1999
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING TEMPERATURE OF A SEMICONDUCTOR WAFER DURING FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09397458
|
Filing Dt:
|
09/16/1999
|
Title:
|
PROCESS FOR IMPROVING LINE WIDTH VARIATIONS BETWEEN TIGHTLY SPACED AND ISOLATED FEATURES IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09397459
|
Filing Dt:
|
09/16/1999
|
Title:
|
SEMICONDUCTOR DEVICE HAVING REDUCED LINE WIDTH VARIATIONS BETWEEN TIGHTLY SPACED AND ISOLATED FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09397716
|
Filing Dt:
|
09/16/1999
|
Title:
|
METHOD OF FABRICATING DEVICES USING AN ATTENUATED PHASE-SHIFTING MASK AND AN ATTENUATED PHASE-SHIFTING MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09398977
|
Filing Dt:
|
09/17/1999
|
Title:
|
MULTILEVEL WIRING STRUCTURE AND METHOD OF FABRICATING A MULTILEVEL WIRING STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09399621
|
Filing Dt:
|
09/20/1999
|
Title:
|
CORROSION-RESISTANT POLISHING PAD CONDITONER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09404702
|
Filing Dt:
|
09/23/1999
|
Title:
|
SEMICONDUCTOR WAFER FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09405805
|
Filing Dt:
|
09/24/1999
|
Title:
|
METHOD FOR ENHANCING ANTIREFLECTIVE COATINGS USED IN PHOTOLIGHOGRAPHY OF ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09407575
|
Filing Dt:
|
09/28/1999
|
Title:
|
METHOD FOR ENHANCED DIELECTRIC FILM UNIFORMITY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09408299
|
Filing Dt:
|
09/29/1999
|
Title:
|
Method of forming capacitor having the lower electrope for preventing undesired pefects at the surface of the metal plug
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09409115
|
Filing Dt:
|
09/30/1999
|
Title:
|
METHOD FOR MAKING INTEGRATED CIRCUITS INCLUDING FEATURES WITH A RELATIVELY SMALL CRITICAL DIMENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09410686
|
Filing Dt:
|
10/01/1999
|
Title:
|
PROCESS FOR FABRICATING COPPER INTERCONNECT FOR ULSI INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09415529
|
Filing Dt:
|
10/08/1999
|
Title:
|
METHOD FOR CHEMICAL/MECHANICAL PLANARIZATION OF A SEMICONDUCTOR WAFER HAVING DISSIMILAR METAL PATTERN DENSITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09416336
|
Filing Dt:
|
10/12/1999
|
Title:
|
METHOD OF MANUFACTURING LATERAL HIGH-Q INDUCTOR FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09416348
|
Filing Dt:
|
10/12/1999
|
Title:
|
LATERAL HIGH-Q INDUCTOR FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09419986
|
Filing Dt:
|
10/18/1999
|
Title:
|
MICROSTRUCTURE CONTROL OF COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09420157
|
Filing Dt:
|
10/18/1999
|
Title:
|
ARTICLE COMPRISING ALIGNED NANOWIRES AND PROCESS FOR FABRICATING ARTICLE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09420234
|
Filing Dt:
|
10/19/1999
|
Title:
|
APPARATUS FOR MEASURING THERMOMECHANICAL PROPERTIES OF PHOTO-SENSITIVE MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09425552
|
Filing Dt:
|
10/22/1999
|
Title:
|
METHOD FOR FORMING INTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09426017
|
Filing Dt:
|
10/25/1999
|
Title:
|
REFERENCE THICKNESS ENDPOINT TECHNIQUES FOR POLISHING OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
09426061
|
Filing Dt:
|
10/22/1999
|
Title:
|
LOW DIELECTRIC CONSTANT SILICON OXIDE-BASED DIELECTRIC LAYER FOR INTEGRATED CIRCUIT STRUCTURES HAVING IMPROVED COMPATIBILITY WITH VIA FILLER MATERIALS, AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09426453
|
Filing Dt:
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10/25/1999
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Title:
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IN-SITU NANO-INTERCONNECTED CIRCUIT DEVICES AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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01/22/2002
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Application #:
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09426457
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Filing Dt:
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10/05/1999
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Title:
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ARTICLE COMPRISING VERTICALLY NANO-INTERCONNECTED CIRCUIT DEVICES AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09427306
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Filing Dt:
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10/26/1999
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Title:
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METHOD OF ELIMINATING AGGLOMERATE PARTICLES IN A POLISHING SLURRY
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09427572
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Filing Dt:
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10/26/1999
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Title:
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PROCESS FOR FORMING METAL INTERCONNECT STACK FOR INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09430147
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Filing Dt:
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10/29/1999
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Title:
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METHOD FOR MAKING INTEGRATED CIRCUITS HAVING FEATURES WITH REDUCED CRITICAL DIMENSIONS
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09430635
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Filing Dt:
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10/29/1999
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Title:
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MIGRATION FROM CONTROL WAFER TO PRODUCT WAFER PARTICLE CHECKS
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09434424
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Filing Dt:
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11/04/1999
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Title:
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METHOD FOR MAKING FIELD EFFECT DEVICES AND CAPACITORS WITH THIN FILM DIELECTRICS AND RESULTING DEVICES
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09437930
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Filing Dt:
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11/10/1999
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Title:
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TESTING INSULATION BETWEEN CONDUCTORS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09438642
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Filing Dt:
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11/12/1999
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Title:
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PROCESS FOR FORMING LOW K SILICON OXIDE DIELECTRIC MATERIAL WHILE SUPPRESSING PRESSURE SPIKING AND INHIBITING INCREASE IN DIELECTRIC CONSTANT
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09439048
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Filing Dt:
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11/12/1999
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Title:
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METHOD AND SYSTEM FOR DETERMINING OPERATOR STAFFING
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Patent #:
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Issue Dt:
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01/01/2002
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Application #:
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09441561
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Filing Dt:
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11/17/1999
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Title:
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METAL SILICIDE AS A BARRIER FOR MOM CAPACITORS IN CMOS TECHNOLOGIES
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09441676
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Filing Dt:
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11/17/1999
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Title:
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METHOD OF FABRICATING A MOM CAPACITOR HAVING A METAL SILICIDE BARRIER
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09442078
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Filing Dt:
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11/16/1999
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Title:
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METHOD AND APPARATUS FOR USING ACROSS WAFER BACK PRESSURE DIFFERENTIALS TO INFLUENCE THE PERFORMANCE OF CHEMICAL MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09442688
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Filing Dt:
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11/18/1999
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Title:
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DISTRIBUTED COMMUNICATIONS SYSTEM FOR REDUCING EQUIPMENT DOWN-TIME
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09444817
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Filing Dt:
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11/22/1999
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Title:
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METHOD OF POLISHING SEMICONDUCTOR STRUCTURES USING A TWO-STEP CHEMICAL MECHANICAL PLANARIZATION WITH SLURRY PARTICLES HAVING DIFFERENT PARTICLE BULK DENSITIES
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09451053
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Filing Dt:
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11/30/1999
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Title:
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SURFACE TREATMENT ANNEAL OF HYDROGENATED SILICON-OXY-CARBIDE DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09454257
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Filing Dt:
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12/02/1999
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Title:
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SLURRY FILLING A RECESS FORMED DURING SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09454909
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Filing Dt:
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12/03/1999
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Title:
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METHODS FOR FABRICATING A MULTILEVEL INTERCONNECTION FOR AN INTEGRATED CIRCUIT DEVICE UTILIZING A SELECTIVE OVERLAYER
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09456210
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Filing Dt:
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12/07/1999
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Title:
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PROCESS FOR FABRICATING INTEGRATED CIRCUIT DEVICES HAVING THIN FILM TRANSISTORS
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09456224
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Filing Dt:
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12/07/1999
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Title:
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METHOD OF FORMING AN ALIGNMENT FEATURE IN OR ON A MULTILAYERED SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09456807
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Filing Dt:
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12/08/1999
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Title:
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ARTICLE COMPRISING A DIELECTRIC MATERIAL OF ZR-GE-TI-O OR HF-GE-TI-O AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09459708
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Filing Dt:
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12/13/1999
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Title:
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CURVILINEAR CHEMICAL MECHANICAL PLANARIZATION DEVICE AND METHOD
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09464225
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Filing Dt:
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12/15/1999
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Title:
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CORROSION SENSITIVITY STRUCTURES FOR VIAS AND CONTACT HOLES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09464297
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Filing Dt:
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12/15/1999
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Title:
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PROCESS FOR ETCHING A CONTROLLABLE THICKNESS OF OXIDE ON AN INTEGRATED CIRCUIT STRUCTURE ON A SEMICONDUCTOR SUBSTRATE USING NITROGEN PLASMA AND PLASMA AND AN RF BIAS APPLIED TO THE SUBSTRATE
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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09465880
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Filing Dt:
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12/16/1999
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Title:
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METHOD AND APPARATUS FOR THICKNESS CONTROL AND REPRODUCIBILITY OF DIELECTRIC FILM DEPOSITION
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09467340
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Filing Dt:
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12/20/1999
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Title:
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NON-LINEAR CIRCUIT ELEMENTS ON INTEGRATED CIRCUITS
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