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09/02/2003
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09654689
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09/05/2000
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INTEGRATED CIRCUIT ISOLATION SYSTEM
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12/17/2002
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09659668
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09/11/2000
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12/03/2002
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09661465
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09/13/2000
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PROCESS FOR PLANARIZATION OF INTEGRATED CIRCUIT STRUCTURE WHICH INHIBITS CRACKING OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL ADJACENT UNDERLYING RAISED STRUCTURES
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05/06/2003
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09665279
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09/19/2000
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06/17/2003
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09666507
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09/20/2000
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EXHAUST FLOW CONTROL SYSTEM
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10/29/2002
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09675109
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09/28/2000
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05/06/2003
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09692012
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10/19/2000
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Title:
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DUAL LEVEL GATE PROCESS FOR HOT CARRIER CONTROL IN DOUBLE DIFFUSED MOS TRANSISTORS
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10/23/2001
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09698375
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10/26/2000
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Title:
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Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation
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05/21/2002
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09703616
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10/30/2000
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Title:
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PROCESS FOR CMP REMOVAL OF EXCESS TRENCH OR VIA FILLER METAL WHICH INHIBITS FORMATION OF CONCAVE REGIONS ON OXIDE SURFACE OF INTEGRATED CIRCUIT STRUCTURE
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03/25/2003
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09704200
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10/31/2000
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Title:
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH LOW DIELECTRIC CONSTANT MATERIAL BETWEEN CLOSELY SPACED APART METAL LINES
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04/08/2003
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09706286
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11/03/2000
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03/19/2002
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11/03/2000
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Integrated circuits with tub-ties and shallow trench isolation
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10/28/2003
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09713106
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11/15/2000
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A SEMICONDUCTOR DEVICE
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05/06/2003
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09713504
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11/15/2000
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Title:
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METHOD FOR AVOIDING NOTCHING IN A SEMICONDUCTOR INTERCONNECT DURING A METAL ETCHING STEP
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08/19/2003
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09714000
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11/15/2000
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PROCESS FOR FORMING PLANARIZED ISOLATION TRENCH IN INTEGRATED CIRCUIT STRUCTURE ON SEMICONDUCTOR SUBSTRATE
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06/01/2004
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09715651
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11/17/2000
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METHOD FOR MAKING A RADIO FREQUENCY COMPONENT AND COMPONENT PRODUCED THEREBY
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02/04/2003
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09718935
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11/21/2000
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Title:
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SEMICONDUCTOR POLISHING PAD ALIGNMENT DEVICE FOR A POLISHING APPARATUS AND METHOD OF USE
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09/24/2002
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09723557
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11/28/2000
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BARRIER FOR COPPER METALLIZATION
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02/18/2003
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09724225
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11/28/2000
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Title:
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METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBIRD INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBIRD CIRCUIT
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04/08/2003
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09724444
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11/28/2000
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SILICON GERMANIUM CMOS CHANNEL
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03/25/2003
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09727325
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11/30/2000
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05/30/2002
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INTEGRATED CIRCUIT FABRICATION
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07/01/2003
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09727326
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11/30/2000
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05/30/2002
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METHOD FOR CLEANING TUNGSTEN FROM DEPOSITION WALL CHAMBERS
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07/02/2002
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09730704
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12/06/2000
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06/14/2001
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CMP SLURRY RECYCLING APPARATUS AND METHOD FOR RECYCLING CMP SLURRY
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05/24/2005
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09731402
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02/06/2001
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08/08/2002
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METHOD AND APPARATUS FOR CONDITIONING A POLISHING PAD
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07/01/2003
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09735084
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12/11/2000
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ETCH RESISTANT SHALLOW TRENCH ISOLATION IN A SEMICONDUCTOR WAFER
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04/22/2003
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09737717
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12/15/2000
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06/20/2002
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METHOD OF CLEANING A SEMICONDUCTOR WAFER WITH A CLEANING BRUSH ASSEMBLY HAVING A CONTRACTIBLE AN EXPANDABLE ARBOR
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02/11/2003
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09741667
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12/19/2000
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10/18/2001
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VIRTUAL-GROUND, SPLIT-GATE FLASH MEMORY CELL ARRANGEMENTS AND METHOD FOR PRODUCING SAME
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09/23/2003
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12/19/2000
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07/31/2003
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OPTICAL STRUCTURES AND METHODS FOR X-RAY APPLICATIONS
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08/12/2003
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09745236
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12/19/2000
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11/22/2001
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X-RAY SYSTEM
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08/27/2002
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12/28/2000
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ARRANGEMENT AND METHOD FOR POLISHING A SURFACE OF A SEMICONDUCTOR WAFER
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04/19/2011
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01/04/2001
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12/13/2001
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METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
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05/25/2004
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01/12/2001
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02/20/2003
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ROUTING TECHNIQUE TO ADJUST CLOCK SKEW
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01/21/2003
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01/12/2001
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07/18/2002
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HETEROJUNCTION BIPOLAR TRANSISTOR
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08/27/2002
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01/30/2001
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08/01/2002
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ALIGNMENT MARK FABRICATION PROCESS TO LIMIT ACCUMULATION OF ERRORS IN LEVEL TO LEVEL OVERLAY
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04/20/2004
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02/06/2001
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CLUSTER TOOL REPORTING SYSTEM
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04/08/2003
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02/16/2001
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08/22/2002
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09/30/2003
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02/20/2001
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08/23/2001
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METHOD FOR FABRICATING A MERGED INTEGRATED CIRCUIT DEVICE
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11/26/2002
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02/22/2001
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06/28/2001
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PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE WITH THIN DIELECTRIC BETWEEN AT LEAST LOCAL INTERCONNECT LEVEL AND FIRST METAL INTERCONNECT LEVEL
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03/16/2004
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02/23/2001
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08/29/2002
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METHOD OF FORMING A SEMICONDUCTOR DEVICE
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10/01/2002
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02/23/2001
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METHOD OF PROTECTING ACID-CATALYZED PHOTORESIST FROM CHIP-GENERATED BASIC CONTAMINANTS
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07/01/2003
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03/13/2001
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09/19/2002
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METAL PLANARIZATION SYSTEM
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12/10/2002
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03/14/2001
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POWER MESH BRIDGE
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03/22/2005
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03/15/2001
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09/19/2002
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METHOD FOR DETECTING DEFECTS IN A MATERIAL AND A SYSTEM FOR ACCOMPLISHING THE SAME
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11/05/2002
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03/26/2001
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CONCENTRIC METAL DENSITY POWER ROUTING
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09/09/2003
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03/29/2001
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10/03/2002
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07/22/2003
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04/27/2001
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ANALOG CAPACITOR DUAL DAMASCENE PROCESS
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01/07/2003
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05/02/2001
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11/07/2002
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PROCESS FOR FORMING METAL-FILLED OPENINGS IN LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL WHILE INHIBITING VIA POISONING
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08/13/2002
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05/17/2001
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04/01/2003
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05/24/2001
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11/28/2002
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03/16/2004
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05/29/2001
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01/10/2002
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11/19/2002
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06/11/2001
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10/11/2001
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SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A TANTALUM PENTOXIDE LAYER SANDWICHED BETWEEN SILICON NITRIDE LAYERS
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04/05/2005
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06/11/2001
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12/12/2002
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PLASMA TREATMENT SYSTEM
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12/17/2002
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06/12/2001
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07/20/2004
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06/12/2001
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07/05/2005
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06/14/2001
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01/07/2003
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06/14/2001
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05/27/2003
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06/15/2001
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12/19/2002
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METHOD OF CONVERTING A METAL OXIDE SEMICONDUCTOR TRANSISTOR INTO A BIPOLAR TRANSISTOR
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10/25/2005
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06/15/2001
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12/19/2002
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SEMICONDUCTOR DEVICE HAVING AT LEAST ONE SOURCE/DRAIN REGION FORMED ON AN ISOLATION REGION AND A METHOD OF MANUFACTURE THEREFOR
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08/05/2003
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06/15/2001
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12/19/2002
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FORMATION OF SILICON ON INSULATOR (SOI) DEVICES AS ADD-ON MODULES FOR SYSTEM ON A CHIP PROCESSING
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08/16/2005
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06/19/2001
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PLASMA TREATMENT OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL TO FORM STRUCTURES USEFUL IN FORMATION OF METAL INTERCONNECTS AND/OR FILLED VIAS FOR INTEGRATED CIRCUIT STRUCTURE
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02/08/2005
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06/18/2001
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11/01/2001
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CONFINEMENT DEVICE FOR USE IN DRY ETCHING OF SUBSTRATE SURFACE AND METHOD OF DRY ETCHING A WAFER SURFACE
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11/18/2003
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06/21/2001
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11/01/2001
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INTEGRATED CIRCUIT HAVING A MICROMAGNETIC DEVICE AND METHOD OF MANUFACTURE THEREFOR
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02/15/2005
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06/22/2001
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05/06/2003
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06/27/2001
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH LOW DIELECTRIC CONSTANT MATERIAL BETWEEN CLOSELY SPACED APART METAL LINES
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10/01/2002
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06/28/2001
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11/01/2001
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POLISHING FLUID, POLISHING METHOD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD
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Issue Dt:
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08/27/2002
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Application #:
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09894117
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Filing Dt:
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06/28/2001
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Publication #:
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Pub Dt:
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11/01/2001
| | | | |
Title:
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POLISHING FLUID, POLISHING METHOD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD
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Patent #:
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Issue Dt:
|
11/02/2004
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Application #:
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09896363
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Filing Dt:
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06/28/2001
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Title:
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DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
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Patent #:
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Issue Dt:
|
06/10/2003
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Application #:
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09896669
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Filing Dt:
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06/29/2001
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
Title:
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ELECTROSTATIC DISCHARGE PROTECTION IN DOUBLE DIFFUSED MOS TRANSISTORS
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Patent #:
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|
Issue Dt:
|
03/19/2002
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Application #:
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09896958
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Filing Dt:
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06/29/2001
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Title:
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SILICON CARBIDE CMOS CHANNEL
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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09901073
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Filing Dt:
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07/09/2001
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Publication #:
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Pub Dt:
|
11/22/2001
| | | | |
Title:
|
Lateral high-Q inductor for semiconductor devices
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Patent #:
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|
Issue Dt:
|
08/13/2002
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Application #:
|
09906331
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Filing Dt:
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07/16/2001
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Title:
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METHOD OF COUPLING CAPACITANCE REDUCTION
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Patent #:
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|
Issue Dt:
|
11/29/2005
|
Application #:
|
09909175
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Filing Dt:
|
07/19/2001
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Title:
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ARRANGEMENT AND METHOD FOR CONTROLLING THE TRANSMISSION OF A LIGHT SIGNAL BASED ON INTENSITY OF A RECEIVED LIGHT SIGNAL
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Patent #:
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Issue Dt:
|
06/21/2005
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Application #:
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09911035
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Filing Dt:
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07/23/2001
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Publication #:
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Pub Dt:
|
01/23/2003
| | | | |
Title:
|
MIXED SIGNAL INTEGRATED CIRCUIT WITH IMPROVED ISOLATION
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Patent #:
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|
Issue Dt:
|
01/18/2005
|
Application #:
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09911364
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Filing Dt:
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07/23/2001
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Publication #:
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|
Pub Dt:
|
01/23/2003
| | | | |
Title:
|
METHOD AND STRUCTURE FOR DC AND RF SHIELDING OF INTEGRATED CIRCUITS
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|
Patent #:
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|
Issue Dt:
|
04/01/2003
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Application #:
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09917365
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Filing Dt:
|
07/27/2001
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Publication #:
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|
Pub Dt:
|
11/15/2001
| | | | |
Title:
|
PROCESS FOR MAKING MIXED METAL OXIDES
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|
Patent #:
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|
Issue Dt:
|
07/29/2003
|
Application #:
|
09920890
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Filing Dt:
|
08/02/2001
|
Title:
|
PARAMETRIC DEVICE SIGNATURE
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|
Patent #:
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|
Issue Dt:
|
01/07/2003
|
Application #:
|
09927752
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Filing Dt:
|
08/10/2001
|
Title:
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METHOD FOR CONCURRENTLY FORMING AN ESD PROTECTION DEVICE AND A SHALLOW TRENCH ISOLATION REGION
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|
Patent #:
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Issue Dt:
|
06/01/2004
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Application #:
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09928570
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Filing Dt:
|
08/13/2001
|
Title:
|
HIGH SELECTIVITY SIC ETCH IN INTEGRATED CIRCUIT FABRICATION
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|
Patent #:
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|
Issue Dt:
|
08/09/2005
|
Application #:
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09934283
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Filing Dt:
|
08/21/2001
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Publication #:
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|
Pub Dt:
|
01/03/2002
| | | | |
Title:
|
STEPPED ETALON
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|
Patent #:
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|
Issue Dt:
|
04/15/2003
|
Application #:
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09935241
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Filing Dt:
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08/22/2001
|
Publication #:
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|
Pub Dt:
|
02/27/2003
| | | | |
Title:
|
METHOD FOR REDUCING A METAL SEAM IN AN INTERCONNECT STRUCTURE AND A DEVICE MANUFACTURED THEREBY
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Patent #:
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|
Issue Dt:
|
05/24/2005
|
Application #:
|
09942220
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Filing Dt:
|
08/29/2001
|
Title:
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SYSTEM AND METHOD FOR OPTIMIZING THE ELECTROSTATIC REMOVAL OF A WORKPIECE FROM A CHUCK
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|
Patent #:
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|
Issue Dt:
|
02/18/2003
|
Application #:
|
09943403
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Filing Dt:
|
08/30/2001
|
Title:
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SEMICONDUCTOR WAFER ARRANGEMENT AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER
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|
Patent #:
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|
Issue Dt:
|
11/18/2003
|
Application #:
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09943630
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Filing Dt:
|
08/30/2001
|
Publication #:
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|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
POLISHING HEAD FOR PRESSURIZED DELIVERY OF SLURRY
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|
Patent #:
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|
Issue Dt:
|
04/27/2004
|
Application #:
|
09948808
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Filing Dt:
|
09/07/2001
|
Title:
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METHOD OF TESTING THE PROCESSING OF A SEMICONDUCTOR WAFER ON A CMP APPARATUS
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|
Patent #:
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|
Issue Dt:
|
12/16/2003
|
Application #:
|
09950008
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Filing Dt:
|
09/10/2001
|
Title:
|
ALKALINE COPPER PLATING
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|
|
Patent #:
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|
Issue Dt:
|
02/25/2003
|
Application #:
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09951178
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Filing Dt:
|
09/13/2001
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
Title:
|
CAPACITOR HAVING THE LOWER ELECTRODE FOR PREVENTING UNDESIRED DEFECTS AT THE SURFACE OF THE METAL PLUG
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|
Patent #:
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|
Issue Dt:
|
09/16/2003
|
Application #:
|
09952343
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Filing Dt:
|
09/14/2001
|
Title:
|
ION BEAM DUAL DAMASCENE PROCESS
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|
Patent #:
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|
Issue Dt:
|
09/21/2004
|
Application #:
|
09952540
|
Filing Dt:
|
09/14/2001
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING TEMPERATURE OF A SEMICONDUCTOR WAFER DURING FABRICATION THEREOF
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|
Patent #:
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|
Issue Dt:
|
12/09/2003
|
Application #:
|
09954341
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Filing Dt:
|
09/17/2001
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
Title:
|
PAD FOR CHEMICAL MECHANICAL POLISHING
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
09956381
|
Filing Dt:
|
09/18/2001
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
Title:
|
Structure and fabrication method for capacitors integratible with vertical replacement gate transistors
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|
|
Patent #:
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|
Issue Dt:
|
07/06/2004
|
Application #:
|
09956382
|
Filing Dt:
|
09/18/2001
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTOR COMPATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09960765
|
Filing Dt:
|
09/21/2001
|
Title:
|
INDIUM FIELD IMPLANT FOR PUNCHTHROUGH PROTECTION IN SEMICONDUCTOR DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
02/03/2004
|
Application #:
|
09961477
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Filing Dt:
|
09/21/2001
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
Title:
|
MULTIPLE OPERATING VOLTAGE VERTICAL REPLACEMENT-GATE (VRG) TRANSISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09964041
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Filing Dt:
|
09/26/2001
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A BURIED LAYER FOR REDUCING LATCHUP AND A METHOD OF MANUFACTURE THEREFOR
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|
Patent #:
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|
Issue Dt:
|
09/16/2003
|
Application #:
|
09964157
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Filing Dt:
|
09/26/2001
|
Title:
|
METHOD AND APPARATUS FOR THE USE OF EMBEDDED RESISTANCE TO LINEARIZE AND IMPROVE THE MATCHING PROPERTIES OF TRANSISTORS
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|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09965739
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Filing Dt:
|
09/28/2001
|
Publication #:
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|
Pub Dt:
|
04/03/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONTROLLING CONTAMINATION DURING THE ELECTROPLATING DEPOSITION OF METALS ONTO A SEMICONDUCTOR WAFER SURFACE
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|
Patent #:
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|
Issue Dt:
|
02/24/2004
|
Application #:
|
09966156
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Filing Dt:
|
09/28/2001
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR MINIMIZING SEMICONDUCTOR WAFER CONTAMINATION
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|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
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09966464
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Filing Dt:
|
09/28/2001
|
Title:
|
METHOD OF FABRICATING A LOCAL INTERCONNECT
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|
Patent #:
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|
Issue Dt:
|
04/27/2004
|
Application #:
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09967074
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Filing Dt:
|
09/28/2001
|
Title:
|
FABRICATION OF METAL CONTACTS FOR DEEP-SUBMICRON TECHNOLOGIES
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|
Patent #:
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|
Issue Dt:
|
03/23/2004
|
Application #:
|
09968234
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Filing Dt:
|
09/28/2001
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
Title:
|
VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
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|