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09968388
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09/28/2001
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04/03/2003
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10/29/2002
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09968944
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10/02/2001
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11/11/2003
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09970392
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10/03/2001
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04/10/2003
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LATENT DEFECT CLASSIFICATION SYSTEM
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12/23/2003
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10/05/2001
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01/02/2003
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THIN FILM MULTI-LAYER HIGH Q TRANSFORMER FORMED IN A SEMICONDUCTOR SUBSTRATE
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12/02/2003
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09974008
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10/10/2001
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HEAVIEST ONLY FAIL POTENTIAL
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02/04/2003
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09974251
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10/10/2001
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02/24/2004
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10/15/2001
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03/28/2002
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02/21/2006
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09991202
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06/15/2004
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11/14/2001
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05/02/2002
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04/15/2003
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09994083
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11/21/2001
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05/11/2004
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10/24/2001
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06/24/2003
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09999872
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10/19/2001
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FIRST STAGE SALICIDATION OF COBALT DURING COBALT DEPOSITION OR SUBSEQUENT TI OR TIN CAP DEPOSITION USING ENERGY FROM A DIRECTIONAL PLASMA
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03/04/2003
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10002831
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10/26/2001
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PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL
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09/02/2003
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10002981
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10/26/2001
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE COMPRISING LAYER OF LOW K DIELECTRIC MATERIAL HAVING ANTIREFLECTIVE PROPERTIES IN AN UPPER SURFACE
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05/18/2004
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10003873
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10/24/2001
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04/24/2003
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SEMICONDUCTOR DEVICE HAVING A DOPED LATTICE MATCHING LAYER AND A METHOD OF MANUFACTURE THEREFOR
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05/20/2003
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10004461
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11/01/2001
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METHOD FOR CREATING SELF-ALIGNED ALLOY CAPPING LAYERS FOR COPPER INTERCONNECT STRUCTURES
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04/22/2003
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10006540
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11/30/2001
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METHOD FOR PREVENTING BORDERLESS CONTACT TO WELL LEAKAGE
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01/27/2004
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10007417
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10/31/2001
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05/01/2003
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INTEGRATED CIRCUIT HAVING STRESS MIGRATION TEST STRUCTURE AND METHOD THEREFOR
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06/08/2004
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10007904
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10/31/2001
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05/01/2003
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STRESS MIGRATION TEST STRUCTURE AND METHOD THEREFOR
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03/09/2004
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10008015
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11/13/2001
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05/15/2003
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MICROELECTRONIC DEVICE LAYER DEPOSITED WITH MULTIPLE ELECTROLYTES
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03/16/2004
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10008170
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10/19/2001
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HIGH SPEED LOW NOISE TRANSISTOR
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04/06/2004
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10012847
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12/10/2001
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METHOD AND APPARATUS FOR DETECTING PRESENCE OF RESIDUAL POLISHING SLURRY SUBSEQUENT TO POLISHING OF A SEMICONDUCTOR WAFER
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09/02/2003
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10013572
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12/11/2001
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06/12/2003
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INTEGRATED INDUCTOR IN SEMICONDUCTOR MANUFACTURING
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05/13/2003
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10015255
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12/11/2001
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Title:
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CONTROL OF REACTION RATE IN FORMATION OF LOW K CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL USING ORGANOSILANE, UNSUBSTITUTED SILANE, AND HYDROGEN PEROXIDE REACTANTS
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02/03/2004
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12/13/2001
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ANTI-REFLECTIVE COATINGS FOR USE AT 248 NM AND 193 NM
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03/30/2004
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12/19/2001
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METHOD OF PREVENTING RESIST POISONING IN DUAL DAMASCENE STRUCTURES
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05/04/2004
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10026407
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12/20/2001
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METHOD OF FORMING SIGE GATE ELECTRODE
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09/23/2003
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10028594
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12/20/2001
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10/24/2002
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MICROMAGNETIC DEVICE HAVING ALLOY OF COBALT, PHOSPHORUS AND IRON
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11/09/2004
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10028614
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12/21/2001
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06/26/2003
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METHOD FOR MAKING A BIPOLAR TRANSISTOR WITH AN OXYGEN IMPLANTED EMITTER WINDOW
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11/16/2004
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10033090
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10/25/2001
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UNIFORM AIRFLOW DIFFUSER
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01/28/2003
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10033164
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10/19/2001
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11/30/2004
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10035346
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12/28/2001
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06/01/2004
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10035501
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10/25/2001
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METHOD FOR GROWING THIN FILMS
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04/27/2004
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10/18/2001
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MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
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08/30/2005
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12/21/2001
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07/13/2004
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12/31/2001
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05/09/2002
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01/11/2005
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11/09/2001
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ADJUSTABLE TRANSMISSION PHASE SHIFT MASK
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06/10/2003
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10/26/2001
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05/15/2003
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04/27/2004
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01/18/2002
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05/23/2002
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01/06/2004
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11/02/2001
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03/23/2004
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01/22/2002
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07/24/2003
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10/05/2004
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01/23/2002
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07/24/2003
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SYSTEM AND METHOD FOR THE ABATEMENT OF TOXIC CONSTITUENTS OF EFFLUENT GASES
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03/23/2004
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01/29/2002
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MULTI PATTERN RETICLE
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06/22/2004
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02/01/2002
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09/16/2003
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02/07/2002
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12/14/2004
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02/15/2002
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08/21/2003
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05/04/2004
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02/21/2002
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07/25/2002
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11/25/2003
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03/08/2002
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09/11/2003
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THERMAL LOW K DIELECTRICS
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05/11/2004
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10106128
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03/19/2002
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09/25/2003
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ANTI-BINDING DEPOSITION RING
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04/12/2005
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04/05/2002
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10/09/2003
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DYNAMIC USE OF PROCESS TEMPERATURE
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NONE
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10120707
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04/11/2002
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09/26/2002
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Process for fabricating copper interconnect for ULSI integrated circuits
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08/31/2004
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10120767
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04/10/2002
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10/16/2003
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METHOD AND APPARATUS FOR DETECTION OF CHEMICAL MECHANICAL PLANARIZATION ENDPOINT AND DEVICE PLANARITY
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06/15/2004
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04/12/2002
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10/16/2003
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CALIBRATION STANDARD FOR HIGH RESOLUTION ELECTRON MICROSCOPY
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11/07/2006
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10123263
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04/15/2002
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08/10/2004
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04/23/2002
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12/26/2002
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WEB-BASED INTERFACE WITH DEFECT DATABASE TO VIEW AND UPDATE FAILURE EVENTS
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02/06/2007
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05/01/2002
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11/06/2003
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METHOD FOR ANALYZING MANUFACTURING DATA
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10/07/2003
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10140536
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05/07/2002
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METHOD AND APPARATUS FOR REMOVING WATER VAPOR AS A BYPRODUCT OF CHEMICAL REACTION IN A WAFER PROCESSING CHAMBER
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12/07/2004
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05/07/2002
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11/13/2003
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SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THAT ELECTRICALLY CONNECTS A CONDUCTIVE MATERIAL AND A DOPED LAYER, AND A METHOD OF MANUFACTURE THEREFOR
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01/27/2004
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05/16/2002
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10/31/2002
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09/28/2004
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05/22/2002
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11/27/2003
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FABRICATION PROCESS FOR A SEMICONDUCTOR DEVICE HAVING A METAL OXIDE DIELECTRIC MATERIAL WITH A HIGH DIELECTRIC CONSTANT, ANNEALED WITH A BUFFERED ANNEAL PROCESS
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NONE
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10152879
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05/21/2002
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01/23/2003
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Microstructure control of copper interconnects
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09/21/2004
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10153011
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05/21/2002
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09/26/2002
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INTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINES
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09/21/2004
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10153011
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05/21/2002
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09/26/2002
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INTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINES
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02/03/2004
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05/21/2002
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11/27/2003
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SEMICONDUCTOR DEVICE BARRIER LAYER
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Issue Dt:
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01/20/2004
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Application #:
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10155173
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
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HIGH K DIELECTRIC MATERIAL AND METHOD OF MAKING A HIGH K DIELECTRIC MATERIAL
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Patent #:
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Issue Dt:
|
03/23/2004
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Application #:
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10156242
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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ABNORMAL PHOTORESIST LINE/SPACE PROFILE DETECTION THROUGH SIGNAL PROCESSING OF METROLOGY WAVEFORM
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Patent #:
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|
Issue Dt:
|
03/08/2005
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Application #:
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10158641
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Filing Dt:
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05/30/2002
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Title:
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GROUNDING MECHANISM FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
01/10/2006
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Application #:
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10158775
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
|
OVERLAY METROLOGY USING SCATTEROMETRY PROFILING
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10159268
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Filing Dt:
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06/03/2002
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Publication #:
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Pub Dt:
|
05/01/2003
| | | | |
Title:
|
HOLDER, SYSTEM, AND PROCESS FOR IMPROVING OVERLAY IN LITHOGRAPHY
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Patent #:
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|
Issue Dt:
|
09/02/2003
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Application #:
|
10160812
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Filing Dt:
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05/31/2002
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Title:
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COMPOSITE SPACER SCHEME WITH LOW OVERLAPPED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
|
10/21/2003
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Application #:
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10164202
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Filing Dt:
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06/06/2002
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Title:
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ULTRA THIN BODY VERTICAL REPLACEMENT GATE MOSFET
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Patent #:
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Issue Dt:
|
04/29/2003
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Application #:
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10164909
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Filing Dt:
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06/07/2002
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Title:
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ARRANGEMENT AND METHOD FOR POLISHING A SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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10171701
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Filing Dt:
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06/14/2002
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
Title:
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Coupling capacitance reduction
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10172849
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Filing Dt:
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06/17/2002
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Publication #:
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|
Pub Dt:
|
12/18/2003
| | | | |
Title:
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METHOD TO IMPROVE THE CONTROL OF SOURCE CHEMICALS DELIVERY BY A CARRIER GAS
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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10179057
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Filing Dt:
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06/25/2002
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Publication #:
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|
Pub Dt:
|
12/25/2003
| | | | |
Title:
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Method and structure for graded gate oxides on vertical and non-planar surfaces
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Patent #:
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|
Issue Dt:
|
11/30/2004
|
Application #:
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10180221
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Filing Dt:
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06/25/2002
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Publication #:
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|
Pub Dt:
|
12/25/2003
| | | | |
Title:
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APPARATUS FOR SCANNING A CRYSTALLINE SAMPLE AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
|
08/10/2004
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Application #:
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10180661
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Filing Dt:
|
06/25/2002
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Title:
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METHOD AND STRUCTURE FOR FORMING DIELECTRIC LAYERS HAVING REDUCED DIELECTRIC CONSTANTS
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Patent #:
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Issue Dt:
|
01/25/2005
|
Application #:
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10180910
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Filing Dt:
|
06/25/2002
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Publication #:
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|
Pub Dt:
|
12/25/2003
| | | | |
Title:
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CAPACITOR FOR A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION THEREFOR
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Patent #:
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|
Issue Dt:
|
03/02/2004
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Application #:
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10185537
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Filing Dt:
|
07/01/2002
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Title:
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METHOD OF FABRICATING AN INTEGRAL CAPACITOR AND GATE TRANSISTOR HAVING NITRIDE AND OXIDE POLISH STOP LAYERS USING CHEMICAL MECHANICAL POLISHING ELIMINATION
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Patent #:
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|
Issue Dt:
|
01/06/2004
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Application #:
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10194578
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Filing Dt:
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07/12/2002
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Title:
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THIN FILM CMOS CALIBRATION STANDARD HAVING PROTECTIVE COVER LAYER
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Patent #:
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Issue Dt:
|
01/06/2004
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Application #:
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10195775
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Filing Dt:
|
07/12/2002
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Title:
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METHOD OF REDUCING PROCESS PLASMA DAMAGE USING OPTICAL SPECTROSCOPY
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10196787
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Filing Dt:
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07/17/2002
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Publication #:
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Pub Dt:
|
11/28/2002
| | | | |
Title:
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EXHAUST FLOW CONTROL SYSTEM
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|
Patent #:
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Issue Dt:
|
10/19/2004
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Application #:
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10197956
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Filing Dt:
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07/16/2002
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Title:
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ADAPTIVE OFF TESTER SCREENING METHOD BASED ON INTRINSIC DIE PARAMETRIC MEASUREMENTS
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10200233
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Filing Dt:
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07/23/2002
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Publication #:
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Pub Dt:
|
01/29/2004
| | | | |
Title:
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PROCESS FOR FABRICATING A MASK
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Patent #:
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|
Issue Dt:
|
06/22/2004
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Application #:
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10200469
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Filing Dt:
|
07/18/2002
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Title:
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PROCESS AND APPARATUS FOR WAFER EDGE PROFILE CONTROL USING GAS FLOW CONTROL RING
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|
Patent #:
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Issue Dt:
|
07/20/2004
|
Application #:
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10207607
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Filing Dt:
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07/29/2002
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Publication #:
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Pub Dt:
|
01/29/2004
| | | | |
Title:
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METHOD TO IMPROVE THE RESOLUTION OF A PHOTOLITHOGRAPHY SYSTEM BY USE OF A COUPLING LAYER BETWEEN THE PHOTO RESIST AND THE ARC
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10211674
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
|
03/27/2003
| | | | |
Title:
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CMOS INTEGRATED CIRCUIT HAVING VERTICAL TRANSISTORS AND A PROCESS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10216425
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Filing Dt:
|
08/08/2002
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Title:
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METHOD OF REDUCING THE EFFECT OF IMPLANTATION DAMAGE TO SHALLOW TRENCH ISOLATION REGIONS DURING THE FORMATION OF VARIABLE THICKNESS GATE LAYERS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10224220
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Filing Dt:
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08/20/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
Title:
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Transistor fabrication method
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10226930
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Filing Dt:
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08/22/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
Title:
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ELECTRO-MECHANICAL DEVICE HAVING A CHARGE DISSIPATION LAYER AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
|
03/01/2005
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Application #:
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10228859
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
01/09/2003
| | | | |
Title:
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CAPACITOR HAVING A TANTALUM LOWER ELECTRODE AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
|
10/24/2006
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Application #:
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10234354
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Filing Dt:
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09/03/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
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PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10238073
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Filing Dt:
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09/09/2002
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Publication #:
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Pub Dt:
|
04/03/2003
| | | | |
Title:
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DIAMOND BARRIER LAYER
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10242165
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Filing Dt:
|
09/11/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
Title:
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GLOBAL CHIP INTERCONNECT
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Patent #:
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Issue Dt:
|
04/26/2005
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Application #:
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10243562
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Filing Dt:
|
09/13/2002
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Title:
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OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
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Patent #:
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Issue Dt:
|
02/15/2005
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Application #:
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10245219
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Filing Dt:
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09/17/2002
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Title:
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LOW-LOSS ON-CHIP TRANSMISSION LINE FOR INTEGRATED CIRCUIT STRUCTURES AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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07/31/2007
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10245447
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09/17/2002
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Publication #:
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Pub Dt:
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03/18/2004
| | | | |
Title:
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METHOD FOR FORMING METAL SILICIDE REGIONS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10251082
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Filing Dt:
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09/20/2002
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Publication #:
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Pub Dt:
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03/25/2004
| | | | |
Title:
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MASK DEFECT ANALYSIS FOR BOTH HORIZONTAL AND VERTICAL PROCESSING EFFECTS
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Patent #:
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Issue Dt:
|
03/30/2004
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Application #:
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10253158
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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01/23/2003
| | | | |
Title:
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PROCESS FOR PLANARIZATION OF INTEGRATED CIRCUIT STRUCTURE WHICH INHIBITS CRACKING OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL ADJACENT UNDERLYING RAISED STRUCTURES
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10256466
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09/27/2002
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Pub Dt:
|
04/03/2003
| | | | |
Title:
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HIGH DOPANT CONCENTRATION DIFFUSED RESISTOR AND METHOD OF MANUFACTURE THEREFOR
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