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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:044886/0001   Pages: 107
Recorded: 12/17/2017
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1129
Page 9 of 12
Pages: 1 2 3 4 5 6 7 8 9 10 11 12
1
Patent #:
Issue Dt:
08/31/2004
Application #:
10260693
Filing Dt:
09/30/2002
Publication #:
Pub Dt:
04/01/2004
Title:
JUNCTION CAPACITOR STRUCTURE AND FABRICATION METHOD THEREFOR IN A DUAL DAMASCENE PROCESS
2
Patent #:
Issue Dt:
10/10/2006
Application #:
10260824
Filing Dt:
09/27/2002
Publication #:
Pub Dt:
04/10/2003
Title:
METHOD OF FORMING A METAL-INSULATOR-METAL CAPACITOR IN AN INTERCONNECT CAVITY
3
Patent #:
Issue Dt:
09/06/2005
Application #:
10261463
Filing Dt:
09/30/2002
Publication #:
Pub Dt:
04/01/2004
Title:
SILICON-RICH LOW THERMAL BUDGET SILICON NITRIDE FOR INTEGRATED CIRCUITS
4
Patent #:
Issue Dt:
09/02/2003
Application #:
10263593
Filing Dt:
10/03/2002
Publication #:
Pub Dt:
02/13/2003
Title:
APPARATUS FOR REMOVING PHOTORESIST EDGE BEADS FROM THIN FILM SUBSTRATES
5
Patent #:
Issue Dt:
03/15/2005
Application #:
10265856
Filing Dt:
10/07/2002
Publication #:
Pub Dt:
04/08/2004
Title:
APPARATUS AND METHOD TO IMPROVE THE RESOLUTION OF PHOTOLITHOGRAPHY SYSTEMS BY IMPROVING THE TEMPERATURE STABILITY OF THE RETICLE
6
Patent #:
Issue Dt:
08/31/2004
Application #:
10267810
Filing Dt:
10/09/2002
Publication #:
Pub Dt:
04/15/2004
Title:
LATERALLY INTERCONNECTING STRUCTURES
7
Patent #:
Issue Dt:
11/04/2003
Application #:
10272767
Filing Dt:
10/16/2002
Title:
INTER-LAYER INTERCONNECTION STRUCTURE FOR LARGE ELECTRICAL CONNECTIONS
8
Patent #:
Issue Dt:
04/20/2004
Application #:
10274765
Filing Dt:
10/21/2002
Title:
SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC AND METHOD OF MANUFACTURE THEREOF
9
Patent #:
Issue Dt:
03/16/2004
Application #:
10288410
Filing Dt:
11/05/2002
Title:
HIGH PERFORMANCE SI-GE DEVICE MODULE WITH CMOS TECHNOLOGY
10
Patent #:
Issue Dt:
01/04/2005
Application #:
10290437
Filing Dt:
11/06/2002
Title:
METHOD AND APPARATUS FOR CLEANING DEPOSITED FILMS FROM THE EDGE OF A WAFER
11
Patent #:
Issue Dt:
07/13/2004
Application #:
10300254
Filing Dt:
11/20/2002
Publication #:
Pub Dt:
05/29/2003
Title:
LDMOS DEVICE HAVING A TAPERED OXIDE
12
Patent #:
Issue Dt:
11/30/2004
Application #:
10300365
Filing Dt:
11/20/2002
Publication #:
Pub Dt:
05/20/2004
Title:
SEMICONDUCTOR DEVICE USING AN INSULATING LAYER HAVING A SEED LAYER
13
Patent #:
Issue Dt:
12/02/2003
Application #:
10304631
Filing Dt:
11/26/2002
Publication #:
Pub Dt:
04/24/2003
Title:
METHOD OF REDUCING SILICONE OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT
14
Patent #:
Issue Dt:
03/15/2005
Application #:
10304974
Filing Dt:
11/26/2002
Publication #:
Pub Dt:
05/27/2004
Title:
THICK METAL TOP LAYER
15
Patent #:
NONE
Issue Dt:
Application #:
10306565
Filing Dt:
11/27/2002
Publication #:
Pub Dt:
05/27/2004
Title:
Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate
16
Patent #:
Issue Dt:
05/24/2005
Application #:
10313333
Filing Dt:
12/06/2002
Publication #:
Pub Dt:
06/10/2004
Title:
PROCESS TO MINIMIZE POLYSILICON GATE DEPLETION AND DOPANT PENETRATION AND TO INCREASE CONDUCTIVITY
17
Patent #:
Issue Dt:
09/05/2006
Application #:
10317147
Filing Dt:
12/11/2002
Publication #:
Pub Dt:
09/18/2003
Title:
METHOD OF VERIFYING IC MASK SETS
18
Patent #:
Issue Dt:
03/16/2004
Application #:
10321250
Filing Dt:
12/16/2002
Title:
SENICONDUCTOR WAFER ARRANGEMENT OF A SEMICONDUCTOR WAFER
19
Patent #:
Issue Dt:
09/06/2005
Application #:
10321938
Filing Dt:
12/16/2002
Title:
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES
20
Patent #:
Issue Dt:
03/15/2005
Application #:
10327283
Filing Dt:
12/19/2002
Title:
DIAMOND METAL-FILLED PATTERNS ACHIEVING LOW PARASITIC COUPLING CAPACITANCE
21
Patent #:
Issue Dt:
04/25/2006
Application #:
10328333
Filing Dt:
12/23/2002
Title:
DUAL DAMASCENE INTERCONNECT STRUCTURE WITH IMPROVED ELECTRO MIGRATION LIFETIMES
22
Patent #:
Issue Dt:
12/06/2005
Application #:
10328614
Filing Dt:
12/23/2002
Title:
LOW K POLYMER E-BEAM PRINTABLE MECHANICAL SUPPORT
23
Patent #:
Issue Dt:
03/21/2006
Application #:
10335470
Filing Dt:
12/31/2002
Title:
INTERCONNECT ROUTING USING PARALLEL LINES AND METHOD OF MANUFACTURE
24
Patent #:
Issue Dt:
01/17/2006
Application #:
10358968
Filing Dt:
02/04/2003
Title:
ALTERNATING APERTURE PHASE-SHIFT MASK FABRICATION METHOD
25
Patent #:
Issue Dt:
05/17/2005
Application #:
10360746
Filing Dt:
02/05/2003
Title:
METHOD FOR PREVENTING BORDERLESS CONTACT TO WELL LEAKAGE
26
Patent #:
Issue Dt:
10/25/2005
Application #:
10368520
Filing Dt:
02/18/2003
Publication #:
Pub Dt:
08/19/2004
Title:
METHODS AND STRUCTURE FOR IC TEMPERATURE SELF-MONITORING
27
Patent #:
Issue Dt:
06/08/2004
Application #:
10368760
Filing Dt:
02/18/2003
Title:
METHOD FOR CREATING SELF-ALIGNED ALLOY CAPPING LAYERS FOR COPPER INTERCONNECT STRUCTURES
28
Patent #:
Issue Dt:
12/20/2005
Application #:
10368811
Filing Dt:
02/18/2003
Publication #:
Pub Dt:
08/07/2003
Title:
SILICON GERMANIUM CMOS CHANNEL
29
Patent #:
Issue Dt:
12/14/2004
Application #:
10383031
Filing Dt:
03/06/2003
Publication #:
Pub Dt:
08/28/2003
Title:
INTEGRATED CIRCUIT ISOLATION SYSTEM
30
Patent #:
Issue Dt:
03/29/2005
Application #:
10383149
Filing Dt:
03/06/2003
Publication #:
Pub Dt:
08/07/2003
Title:
LOCAL INTERCONNECT FOR INTEGRATED CIRCUIT
31
Patent #:
Issue Dt:
04/04/2006
Application #:
10387846
Filing Dt:
03/13/2003
Publication #:
Pub Dt:
08/14/2003
Title:
MICROMAGNETIC DEVICE FOR POWER PROCESSING APPLICATIONS AND METHOD OF MANUFACTURE THEREFOR
32
Patent #:
Issue Dt:
05/24/2005
Application #:
10392206
Filing Dt:
03/19/2003
Publication #:
Pub Dt:
09/23/2004
Title:
METHOD AND INTEGRATED CIRCUIT FOR CAPACITOR MEASUREMENT WITH DIGITAL READOUT
33
Patent #:
Issue Dt:
05/17/2005
Application #:
10400252
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
10/30/2003
Title:
LOW VIA RESISTANCE SYSTEM
34
Patent #:
Issue Dt:
10/04/2005
Application #:
10400278
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
01/29/2004
Title:
METAL PLANARIZATION SYSTEM
35
Patent #:
Issue Dt:
08/09/2005
Application #:
10400279
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
10/02/2003
Title:
LOCAL INTERCONNECT
36
Patent #:
NONE
Issue Dt:
Application #:
10400281
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
10/30/2003
Title:
Ion beam dual damascene process
37
Patent #:
Issue Dt:
04/05/2005
Application #:
10400297
Filing Dt:
03/26/2003
Title:
VIA AND METAL LINE INTERFACE CAPABLE OF REDUCING THE INCIDENCE OF ELECTRO-MIGRATION INDUCED VOIDS
38
Patent #:
Issue Dt:
02/28/2006
Application #:
10406847
Filing Dt:
04/04/2003
Publication #:
Pub Dt:
10/07/2004
Title:
CHROMELESS PHASE SHIFT MASK
39
Patent #:
Issue Dt:
11/23/2004
Application #:
10409423
Filing Dt:
04/08/2003
Publication #:
Pub Dt:
09/11/2003
Title:
ELECTROSTATIC DISCHARGE PROTECTION IN DOUBLE DIFFUSED MOS TRANSISTORS
40
Patent #:
Issue Dt:
11/23/2004
Application #:
10409499
Filing Dt:
04/08/2003
Publication #:
Pub Dt:
09/18/2003
Title:
ANALOG CAPACITOR IN DUAL DAMASCENE PROCESS
41
Patent #:
Issue Dt:
05/25/2004
Application #:
10410925
Filing Dt:
04/09/2003
Title:
MECHANICAL STRESS FREE PROCESSING METHOD
42
Patent #:
Issue Dt:
07/18/2006
Application #:
10412867
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
10/14/2004
Title:
MODIFIED BINARY SEARCH FOR OPTIMIZING EFFICIENCY OF DATA COLLECTION TIME
43
Patent #:
Issue Dt:
08/19/2008
Application #:
10413051
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
10/14/2004
Title:
HIGH K GATE INSULATOR REMOVAL
44
Patent #:
Issue Dt:
06/06/2006
Application #:
10417708
Filing Dt:
04/16/2003
Title:
WAFER CHUCKING APPARATUS AND METHOD FOR SPIN PROCESSOR
45
Patent #:
Issue Dt:
01/03/2006
Application #:
10418375
Filing Dt:
04/18/2003
Publication #:
Pub Dt:
10/21/2004
Title:
ION RECOIL IMPLANTATION AND ENHANCED CARRIER MOBILITY IN CMOS DEVICE
46
Patent #:
Issue Dt:
04/18/2006
Application #:
10421068
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
12/02/2004
Title:
PLANARIZATION WITH REDUCED DISHING
47
Patent #:
Issue Dt:
10/28/2008
Application #:
10421421
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
10/28/2004
Title:
VISUAL WEAR CONFIRMATION POLISHING PAD
48
Patent #:
Issue Dt:
09/14/2004
Application #:
10422270
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
11/06/2003
Title:
PLASMA TREATMENT OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL TO FORM STRUCTURES USEFUL IN FORMATION OF METAL INTERCONNECTS AND/OR FILLED VIAS FOR INTERGRATED CIRCUIT STRUCTURE
49
Patent #:
Issue Dt:
04/20/2004
Application #:
10423096
Filing Dt:
04/25/2003
Title:
PAD CONDITIONING MONITOR
50
Patent #:
Issue Dt:
03/28/2006
Application #:
10429376
Filing Dt:
05/05/2003
Publication #:
Pub Dt:
11/11/2004
Title:
VARIABLE MASK FIELD EXPOSURE
51
Patent #:
Issue Dt:
02/08/2005
Application #:
10435561
Filing Dt:
05/09/2003
Publication #:
Pub Dt:
11/06/2003
Title:
SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL AND PROCESS FOR ITS MANUFACTURE
52
Patent #:
Issue Dt:
03/23/2004
Application #:
10439863
Filing Dt:
05/16/2003
Title:
SPLIT-GATE METAL-OXIDE-SEMICONDUCTOR DEVICE
53
Patent #:
Issue Dt:
03/08/2005
Application #:
10442533
Filing Dt:
05/20/2003
Title:
FABRICATION OF TRENCHES WITH MULTIPLE DEPTHS ON THE SAME SUBSTRATE
54
Patent #:
Issue Dt:
08/17/2004
Application #:
10448082
Filing Dt:
05/29/2003
Title:
INTERCONNECT INTEGRATION
55
Patent #:
Issue Dt:
02/19/2008
Application #:
10452360
Filing Dt:
06/02/2003
Title:
ELECTROPLATING TOOL FOR SEMICONDUCTOR MANUFACTURE HAVING ELECTRIC FIELD CONTROL
56
Patent #:
Issue Dt:
03/08/2005
Application #:
10453118
Filing Dt:
06/03/2003
Title:
METHOD OF INCORPORATING NITROGEN INTO METAL SILICATE BASED DIELECTRICS BY ENERGIZED NITROGEN ION BEAMS
57
Patent #:
Issue Dt:
04/12/2005
Application #:
10454027
Filing Dt:
06/04/2003
Publication #:
Pub Dt:
12/09/2004
Title:
METHOD TO SELECTIVELY IDENTIFY RELIABILITY RISK DIE BASED ON CHARACTERISTICS OF LOCAL REGIONS ON THE WAFER
58
Patent #:
Issue Dt:
11/30/2004
Application #:
10454133
Filing Dt:
06/04/2003
Publication #:
Pub Dt:
12/09/2004
Title:
INCREASED QUALITY FACTOR OF A VARACTOR IN AN INTEGRATED CIRCUIT VIA A HIGH CONDUCTIVE REGION IN A WELL
59
Patent #:
Issue Dt:
09/30/2008
Application #:
10455489
Filing Dt:
06/04/2003
Publication #:
Pub Dt:
12/09/2004
Title:
STRAINED-SILICON FOR CMOS DEVICE USING AMORPHOUS SILICON DEPOSITION OR SILICON EPITAXIAL GROWTH
60
Patent #:
Issue Dt:
05/18/2004
Application #:
10458141
Filing Dt:
06/09/2003
Title:
COMPOSITE SPACER SCHEME WITH LOW OVERLAPPED PARASITIC CAPACITANCE
61
Patent #:
Issue Dt:
10/19/2004
Application #:
10459072
Filing Dt:
06/11/2003
Title:
METHOD FOR COMPOSING A DIELECTRIC LAYER WITHIN AN INTERCONNECT STRUCTURE OF A MULTILAYER SEMICONDUCTOR DEVICE
62
Patent #:
NONE
Issue Dt:
Application #:
10463158
Filing Dt:
06/16/2003
Publication #:
Pub Dt:
10/28/2004
Title:
Integrated inductor in semiconductor manufacturing
63
Patent #:
Issue Dt:
07/05/2011
Application #:
10505197
Filing Dt:
06/10/2005
Publication #:
Pub Dt:
03/09/2006
Title:
MONITORING AND CONTROL OF A FABRICATION PROCESS
64
Patent #:
Issue Dt:
11/07/2006
Application #:
10513121
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
08/04/2005
Title:
MULTI-LAYER INDUCTOR FORMED IN A SEMICONDUCTOR SUBSTRATE AND HAVING A CORE OF FERROMAGNETIC MATERIAL
65
Patent #:
Issue Dt:
05/11/2010
Application #:
10598213
Filing Dt:
08/21/2006
Publication #:
Pub Dt:
08/14/2008
Title:
BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR
66
Patent #:
Issue Dt:
01/09/2007
Application #:
10603041
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
03/31/2005
Title:
DEFINE VIA IN DUAL DAMASCENE PROCESS
67
Patent #:
Issue Dt:
12/27/2005
Application #:
10607116
Filing Dt:
06/26/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD AND APPARATUS TO ADD SLURRY TO A POLISHING SYSTEM
68
Patent #:
Issue Dt:
12/14/2004
Application #:
10607353
Filing Dt:
06/26/2003
Title:
METHOD AND APPARATUS FOR REMOVING WATER VAPOR AS A BYPRODUCT OF CHEMICAL REACTION IN A WAFER PROCESSING CHAMBER
69
Patent #:
Issue Dt:
08/07/2007
Application #:
10614307
Filing Dt:
07/02/2003
Publication #:
Pub Dt:
01/06/2005
Title:
INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
70
Patent #:
Issue Dt:
01/24/2006
Application #:
10615558
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
01/13/2005
Title:
HARD MASK REMOVAL
71
Patent #:
Issue Dt:
05/23/2006
Application #:
10619058
Filing Dt:
07/14/2003
Publication #:
Pub Dt:
01/22/2004
Title:
METHOD OF ION IMPLANTATION FOR ACHIEVING DESIRED DOPANT CONCENTRATION
72
Patent #:
Issue Dt:
01/09/2007
Application #:
10623082
Filing Dt:
07/17/2003
Title:
INTER-LAYER INTERCONNECTION STRUCTURE FOR LARGE ELECTRICAL CONNECTIONS
73
Patent #:
Issue Dt:
11/16/2004
Application #:
10629496
Filing Dt:
07/29/2003
Title:
SELECTIVE HIGH K DIELECTRICS REMOVAL
74
Patent #:
Issue Dt:
09/21/2004
Application #:
10631528
Filing Dt:
07/31/2003
Title:
METHOD AND APPARATUS FOR REDUCING MICROTRENCHING FOR BORDERLESS VIAS CREATED IN A DUAL DAMASCENE PROCESS
75
Patent #:
Issue Dt:
06/27/2006
Application #:
10637385
Filing Dt:
08/08/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD TO IMPROVE THE CONTROL OF ELECTRO-POLISHING BY USE OF A PLATING ELECTRODE AN ELECTROLYTE BATH
76
Patent #:
Issue Dt:
05/16/2006
Application #:
10638248
Filing Dt:
08/08/2003
Publication #:
Pub Dt:
02/12/2004
Title:
HIGH-DENSITY INTER-DIE INTERCONNECT STRUCTURE
77
Patent #:
NONE
Issue Dt:
Application #:
10640530
Filing Dt:
08/13/2003
Publication #:
Pub Dt:
05/06/2004
Title:
Residual oxygen reduction system
78
Patent #:
Issue Dt:
01/17/2006
Application #:
10641768
Filing Dt:
08/14/2003
Title:
METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
79
Patent #:
Issue Dt:
07/19/2005
Application #:
10643687
Filing Dt:
08/19/2003
Publication #:
Pub Dt:
05/13/2004
Title:
HIGH-K DIELECTRIC GATE MATERIAL UNIQUELY FORMED
80
Patent #:
Issue Dt:
07/17/2007
Application #:
10644116
Filing Dt:
08/20/2003
Publication #:
Pub Dt:
02/24/2005
Title:
WHOLE-WAFER PHOTOEMISSION ANALYSIS
81
Patent #:
Issue Dt:
07/11/2006
Application #:
10646997
Filing Dt:
08/22/2003
Publication #:
Pub Dt:
02/24/2005
Title:
A SPIRAL INDUCTOR FORMED IN A SEMICONDUCTOR SUBSTRATE
82
Patent #:
Issue Dt:
11/23/2004
Application #:
10649140
Filing Dt:
08/27/2003
Publication #:
Pub Dt:
08/05/2004
Title:
METHOD OF MAKING ULTRA THIN BODY VERTICAL REPLACEMENT GATE MOSFET
83
Patent #:
Issue Dt:
06/27/2006
Application #:
10650395
Filing Dt:
08/28/2003
Publication #:
Pub Dt:
03/03/2005
Title:
HIGH QUALITY FACTOR SPIRAL INDUCTOR THAT UTILIZES ACTIVE NEGATIVE CAPACITANCE
84
Patent #:
Issue Dt:
08/30/2005
Application #:
10652369
Filing Dt:
08/29/2003
Publication #:
Pub Dt:
03/03/2005
Title:
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
85
Patent #:
Issue Dt:
05/30/2006
Application #:
10655050
Filing Dt:
09/04/2003
Publication #:
Pub Dt:
03/10/2005
Title:
PHASE-SHIFTING MASK AND SEMICONDUCTOR DEVICE
86
Patent #:
Issue Dt:
03/08/2005
Application #:
10658017
Filing Dt:
09/08/2003
Publication #:
Pub Dt:
03/10/2005
Title:
METHOD OF TRANSLATING A NET DESCRIPTION OF AN INTEGRATED CIRCUIT DIE
87
Patent #:
Issue Dt:
07/18/2006
Application #:
10658168
Filing Dt:
09/08/2003
Publication #:
Pub Dt:
03/24/2005
Title:
METHOD OF QUALIFYING A PROCESS TOOL WITH WAFER DEFECT MAPS
88
Patent #:
Issue Dt:
11/21/2006
Application #:
10659134
Filing Dt:
09/10/2003
Publication #:
Pub Dt:
03/10/2005
Title:
APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
89
Patent #:
Issue Dt:
07/25/2006
Application #:
10668021
Filing Dt:
09/22/2003
Publication #:
Pub Dt:
03/24/2005
Title:
PAD CONDITIONER SETUP
90
Patent #:
Issue Dt:
07/04/2006
Application #:
10668875
Filing Dt:
09/23/2003
Publication #:
Pub Dt:
03/24/2005
Title:
HIGH PERFORMANCE VOLTAGE CONTROL DIFFUSION RESISTOR
91
Patent #:
Issue Dt:
08/31/2004
Application #:
10669398
Filing Dt:
09/24/2003
Publication #:
Pub Dt:
04/22/2004
Title:
HIGH DOPANT CONENTRATION DIFFUSED RESISTOR AND METHOD OF MANUFACTURE THEREFOR
92
Patent #:
Issue Dt:
11/21/2006
Application #:
10675569
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
03/31/2005
Title:
BYPASS LOOP GAS FLOW CALIBRATION
93
Patent #:
Issue Dt:
08/28/2007
Application #:
10675572
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
03/31/2005
Title:
REAL-TIME GATE ETCH CRITICAL DIMENSION CONTROL BY OXYGEN MONITORING
94
Patent #:
Issue Dt:
07/07/2009
Application #:
10675575
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
07/01/2004
Title:
IN-SITU REMOVAL OF SURFACE IMPURITIES PRIOR TO ARSENIC-DOPED POLYSILICON DEPOSITION IN THE FABRICATION OF A HETEROJUNCTION BIPOLAR TRANSISTOR
95
Patent #:
Issue Dt:
06/14/2005
Application #:
10675581
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
03/31/2005
Title:
ALTERNATING PULSE DUAL-BEAM APPARATUS, METHODS AND SYSTEMS FOR VOLTAGE CONTRAST BEHAVIOR ASSESSMENT OF MICROCIRCUITS
96
Patent #:
Issue Dt:
08/09/2005
Application #:
10675633
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
03/31/2005
Title:
METAL-OXIDE-SEMICONDUCTOR DEVICE INCLUDING A BURIED LIGHTLY-DOPED DRAIN REGION
97
Patent #:
Issue Dt:
12/27/2005
Application #:
10676602
Filing Dt:
10/01/2003
Publication #:
Pub Dt:
04/21/2005
Title:
SUBSTRATE-BIASED I/O AND POWER ESD PROTECTION CIRCUITS IN DEEP-SUBMICRON TWIN-WELL PROCESS
98
Patent #:
Issue Dt:
01/04/2005
Application #:
10676934
Filing Dt:
09/30/2003
Title:
PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER
99
Patent #:
Issue Dt:
12/06/2005
Application #:
10680503
Filing Dt:
10/06/2003
Title:
METHOD OF REDUCING PROCESS PLASMA DAMAGE USING OPTICAL SPECTROSCOPY
100
Patent #:
Issue Dt:
06/06/2006
Application #:
10684713
Filing Dt:
10/14/2003
Publication #:
Pub Dt:
03/03/2005
Title:
MULTIPLE OPERATING VOLTAGE VERTICAL REPLACEMENT-GATE (VRG) TRANSISTOR
Assignors
1
Exec Dt:
12/08/2017
2
Exec Dt:
12/08/2017
Assignee
1
401 N. MICHIGAN AVE.
SUITE 1600
CHICAGO, ILLINOIS 60611
Correspondence name and address
CHAD S. HILYARD
401 N. MICHIGAN AVE.
SUITE 1600
CHICAGO, IL 60611

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