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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12840535
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Filing Dt:
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07/21/2010
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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12890336
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Filing Dt:
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09/24/2010
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Publication #:
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Pub Dt:
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01/20/2011
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Title:
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Digitally Obtaining Contours of Fabricated Polygons
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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12901588
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Filing Dt:
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10/11/2010
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Publication #:
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Pub Dt:
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04/12/2012
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Title:
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METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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12905301
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Filing Dt:
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10/15/2010
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Publication #:
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Pub Dt:
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04/19/2012
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Title:
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NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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13058176
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Filing Dt:
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02/08/2011
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Publication #:
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Pub Dt:
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06/09/2011
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Title:
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SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADAPTIVE VOLTAGE SCALING OPTIMIZATION
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Patent #:
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Issue Dt:
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03/12/2013
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Application #:
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13099948
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Filing Dt:
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05/03/2011
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Publication #:
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Pub Dt:
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11/08/2012
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Title:
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INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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13103461
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Filing Dt:
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05/09/2011
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Publication #:
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Pub Dt:
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11/15/2012
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Title:
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TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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13114834
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Filing Dt:
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05/24/2011
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Publication #:
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Pub Dt:
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11/29/2012
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Title:
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FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13150607
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Filing Dt:
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06/01/2011
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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STAGED SCENARIO GENERATION
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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13173855
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Filing Dt:
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06/30/2011
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Publication #:
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Pub Dt:
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10/20/2011
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Title:
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METHOD AND APPARATUS FOR BALANCING SIGNAL DELAY SKEW
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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13212427
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Filing Dt:
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08/18/2011
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Publication #:
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Pub Dt:
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12/15/2011
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Title:
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SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13246102
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Filing Dt:
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09/27/2011
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
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TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLTAGE DROP INTO ACCOUNT
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13367094
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Filing Dt:
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02/06/2012
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Publication #:
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Pub Dt:
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08/08/2013
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Title:
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SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
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Patent #:
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Issue Dt:
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07/30/2013
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Application #:
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13407830
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Filing Dt:
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02/29/2012
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Publication #:
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Pub Dt:
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06/21/2012
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Title:
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LOW DEPTH CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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13421710
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Filing Dt:
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03/15/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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13442099
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Filing Dt:
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04/09/2012
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Publication #:
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Pub Dt:
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08/02/2012
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Title:
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AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13453289
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Filing Dt:
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04/23/2012
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Publication #:
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Pub Dt:
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08/16/2012
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Title:
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CIRCUIT TIMING ANALYSIS INCORPORATING THE EFFECTS OF TEMPERATURE INVERSION
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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13467696
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Filing Dt:
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05/09/2012
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Publication #:
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Pub Dt:
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11/14/2013
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Title:
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MULTI-PASS ROUTING TO REDUCE CROSSTALK
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13544632
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Filing Dt:
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07/09/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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A METHOD AND COMPUTER PROGRAM FOR GENERATING GROUNDED SHIELDING WIRES FOR SIGNAL WIRING
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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13547884
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Filing Dt:
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07/12/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
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Patent #:
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Issue Dt:
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03/11/2014
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Application #:
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13549599
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Filing Dt:
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07/16/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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Characterizing Performance of an Electronic System
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13599549
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Filing Dt:
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08/30/2012
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Publication #:
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Pub Dt:
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02/28/2013
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Title:
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SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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13627054
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Filing Dt:
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09/26/2012
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Title:
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CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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13649909
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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02/07/2013
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Title:
|
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
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|
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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13649996
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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04/25/2013
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Title:
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SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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13657000
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Filing Dt:
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10/22/2012
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Publication #:
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Pub Dt:
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02/21/2013
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Title:
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METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13658336
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Filing Dt:
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10/23/2012
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Publication #:
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Pub Dt:
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02/21/2013
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Title:
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Staged Scenario Generation
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Patent #:
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Issue Dt:
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04/08/2014
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Application #:
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13681283
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Filing Dt:
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11/19/2012
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
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IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13761828
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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06/13/2013
| | | | |
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Title:
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OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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13971560
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Filing Dt:
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08/20/2013
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Publication #:
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Pub Dt:
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12/19/2013
| | | | |
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Title:
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HIERARCHICAL DESIGN FLOW GENERATOR
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Patent #:
|
|
Issue Dt:
|
10/14/2014
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Application #:
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14010842
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Filing Dt:
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08/27/2013
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Publication #:
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Pub Dt:
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12/26/2013
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Title:
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INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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14053194
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Filing Dt:
|
10/14/2013
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Publication #:
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Pub Dt:
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02/06/2014
| | | | |
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Title:
|
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
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|
|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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14057441
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Filing Dt:
|
10/18/2013
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|
Publication #:
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|
Pub Dt:
|
03/27/2014
| | | | |
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Title:
|
CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
|
|
|
|
|
Patent #:
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NONE
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Issue Dt:
|
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Application #:
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14093189
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Filing Dt:
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11/29/2013
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
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Title:
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Circuit Timing Analysis Incorporating the Effects of Temperature Inversion
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14305794
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Filing Dt:
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06/16/2014
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Publication #:
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Pub Dt:
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10/02/2014
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Title:
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METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
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