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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:044887/0109   Pages: 80
Recorded: 12/17/2017
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 935
Page 3 of 10
Pages: 1 2 3 4 5 6 7 8 9 10
1
Patent #:
6058254
Issue Dt:
05/02/2000
Application #:
08906948
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR VERTICAL CONGESTION REMOVAL
2
Patent #:
6123736
Issue Dt:
09/26/2000
Application #:
08906949
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR HORIZONTAL CONGESTION REMOVAL
3
Patent #:
6070108
Issue Dt:
05/30/2000
Application #:
08906950
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR CONGESTION DRIVEN PLACEMENT
4
Patent #:
6182269
Issue Dt:
01/30/2001
Application #:
08907183
Filing Dt:
08/06/1997
Title:
METHOD AND DEVICE FOR FAST AND ACCURATE PARASITIC EXTRACTION
5
Patent #:
5900338
Issue Dt:
05/04/1999
Application #:
08912887
Filing Dt:
08/15/1997
Title:
PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS
6
Patent #:
6083269
Issue Dt:
07/04/2000
Application #:
08914493
Filing Dt:
08/19/1997
Title:
DIGITAL INTEGRATED CIRCUIT DESIGN SYSTEM AND METHODOLOGY WITH HARDWARE
7
Patent #:
6072947
Issue Dt:
06/06/2000
Application #:
08933733
Filing Dt:
09/23/1997
Title:
METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING NOISE MODELING AND PREDICTION
8
Patent #:
6425117
Issue Dt:
07/23/2002
Application #:
08937296
Filing Dt:
09/29/1997
Title:
SYSTEM AND METHOD FOR PERFORMING OPTICAL PROXIMITY CORRECTION ON THE INTERFACE BETWEEN OPTICAL PROXIMITY CORRECTED CELLS
9
Patent #:
5828828
Issue Dt:
10/27/1998
Application #:
08939498
Filing Dt:
09/29/1997
Title:
METHOD FOR INSERTING TEST POINTS FOR FULL-AND-PARTIAL-SCAN BUILT-IN SELF-TESTING
10
Patent #:
5903577
Issue Dt:
05/11/1999
Application #:
08940912
Filing Dt:
09/30/1997
Title:
METHOD AND APPARATUS FOR ANALYZING DIGITAL CIRCUITS
11
Patent #:
5978935
Issue Dt:
11/02/1999
Application #:
08947136
Filing Dt:
10/08/1997
Title:
METHOD FOR BUILT-IN SELF-TESTING OF RING-ADDRESS FIFOS HAVING A DATA INPUT REGISTER WITH TRANSPARENT LATCHES
12
Patent #:
6108805
Issue Dt:
08/22/2000
Application #:
08947271
Filing Dt:
10/08/1997
Title:
DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS
13
Patent #:
6135647
Issue Dt:
10/24/2000
Application #:
08956874
Filing Dt:
10/23/1997
Title:
SYSTEM AND METHOD FOR REPRESENTING A SYSTEM LEVEL RTL DESIGN USING HDL INDEPENDENT OBJECTS AND TRANSLATION TO SYNTHESIZABLE RTL CODE
14
Patent #:
5956350
Issue Dt:
09/21/1999
Application #:
08958775
Filing Dt:
10/27/1997
Title:
BUILT IN SELF REPAIR FOR DRAMS USING ON-CHIP TEMPERATURE SENSING AND HEATING
15
Patent #:
6101458
Issue Dt:
08/08/2000
Application #:
08961163
Filing Dt:
10/30/1997
Title:
AUTOMATIC RANGING APPARATUS AND METHOD FOR PRECISE INTEGRATED CIRCUIT CURRENT MEASUREMENTS
16
Patent #:
6052808
Issue Dt:
04/18/2000
Application #:
08962340
Filing Dt:
10/31/1997
Title:
MAINTENANCE REGISTERS WITH BOUNDARY SCAN INTERFACE
17
Patent #:
6000038
Issue Dt:
12/07/1999
Application #:
08964784
Filing Dt:
11/05/1997
Title:
PARALLEL PROCESSING OF INTEGRATED CIRCUIT PIN ARRIVAL TIMES
18
Patent #:
6292924
Issue Dt:
09/18/2001
Application #:
08964997
Filing Dt:
11/05/1997
Publication #:
US20010020289
Pub Dt:
09/06/2001
Title:
MODIFYING TIMING GRAPH TO AVOID GIVEN SET OF PATHS
19
Patent #:
6212655
Issue Dt:
04/03/2001
Application #:
08974846
Filing Dt:
11/20/1997
Title:
IDDQ TEST SOLUTION FOR LARGE ASICS
20
Patent #:
6182270
Issue Dt:
01/30/2001
Application #:
08975250
Filing Dt:
11/20/1997
Title:
LOW-DISPLACEMENT RANK PRECONDITIONERS FOR SIMPLIFIED NON-LINEAR ANALYSIS OF CIRCUITS AND OTHER DEVICES
21
Patent #:
6311146
Issue Dt:
10/30/2001
Application #:
08985975
Filing Dt:
12/05/1997
Title:
CIRCUIT SIMULATION WITH IMPROVED CIRCUIT PARTITIONING
22
Patent #:
5838585
Issue Dt:
11/17/1998
Application #:
08986753
Filing Dt:
12/08/1997
Title:
PHYSICAL DESIGN AUTOMATION SYSTEM AND METHOD USING MONOTONICALLY IMPROVING LINEAR CLUSTERIZATION
23
Patent #:
5870313
Issue Dt:
02/09/1999
Application #:
08987865
Filing Dt:
12/09/1997
Title:
OPTIMIZATION PROCESSING FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM USING PARALLEL MOVING WINDOWS
24
Patent #:
6134702
Issue Dt:
10/17/2000
Application #:
08991419
Filing Dt:
12/16/1997
Title:
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING MULTIWAY PARTITIONING WITH CONSTRAINTS
25
Patent #:
6269472
Issue Dt:
07/31/2001
Application #:
08991785
Filing Dt:
12/12/1997
Title:
OPTICAL PROXIMITY CORRECTION METHOD AND APPARATUS
26
Patent #:
6134687
Issue Dt:
10/17/2000
Application #:
08994430
Filing Dt:
12/19/1997
Title:
PERIPHERAL PARTITIONING AND TREE DECOMPOSITION FOR PARTIAL SCAN
27
Patent #:
6189131
Issue Dt:
02/13/2001
Application #:
09007242
Filing Dt:
01/14/1998
Title:
IMPROVED METHOD OF SELECTING AND SYNTHESIZING METAL INTERCONNECT WIRES IN INTEGRATED CIRCUITS
28
Patent #:
6070259
Issue Dt:
05/30/2000
Application #:
09007407
Filing Dt:
01/15/1998
Title:
DYNAMIC LOGIC ELEMENT HAVING NON-INVASIVE SCAN CHAIN INSERTION
29
Patent #:
6109201
Issue Dt:
08/29/2000
Application #:
09010395
Filing Dt:
01/21/1998
Title:
RESYNTHESIS METHOD FOR SIGNIFICANT DELAY REDUCTION
30
Patent #:
6901571
Issue Dt:
05/31/2005
Application #:
09010396
Filing Dt:
01/21/1998
Title:
TIMING-DRIVEN PLACEMENT METHOD UTILIZING NOVEL INTERCONNECT DELAY MODEL
31
Patent #:
6202196
Issue Dt:
03/13/2001
Application #:
09017378
Filing Dt:
02/03/1998
Title:
METHOD FOR OPTIMIZING ROUTING MESH SEGMENT WIDTH
32
Patent #:
6239609
Issue Dt:
05/29/2001
Application #:
09022353
Filing Dt:
02/11/1998
Title:
REDUCED VOLTAGE QUIESCENT CURRENT TEST METHODOLOGY FOR INTEGRATED CIRCUITS
33
Patent #:
6148425
Issue Dt:
11/14/2000
Application #:
09022759
Filing Dt:
02/12/1998
Title:
BIST ARCHITECTURE FOR DETECTING PATH-DELAY FAULTS IN A SEQUENTIAL CIRCUIT
34
Patent #:
6836877
Issue Dt:
12/28/2004
Application #:
09026790
Filing Dt:
02/20/1998
Title:
AUTOMATIC SYNTHESIS SCRIPT GENERATION FOR SYNOPSYS DESIGN COMPILER
35
Patent #:
6295636
Issue Dt:
09/25/2001
Application #:
09027283
Filing Dt:
02/20/1998
Title:
RTL ANALYSIS FOR IMPROVED LOGIC SYNTHESIS
36
Patent #:
6205572
Issue Dt:
03/20/2001
Application #:
09027399
Filing Dt:
02/20/1998
Title:
BUFFERING TREE ANALYSIS IN MAPPED DESIGN
37
Patent #:
6289498
Issue Dt:
09/11/2001
Application #:
09027422
Filing Dt:
02/20/1998
Title:
VDHL/VERILOG EXPERTISE AND GATE SYNTHESIS AUTOMATION SYSTEM
38
Patent #:
6173435
Issue Dt:
01/09/2001
Application #:
09027423
Filing Dt:
02/20/1998
Title:
INTERNAL CLOCK HANDLING IN SYNTHESIS SCRIPT
39
Patent #:
6378123
Issue Dt:
04/23/2002
Application #:
09027429
Filing Dt:
02/20/1998
Title:
METHOD OF HANDLING MACRO COMPONENTS IN CIRCUIT DESIGN SYNTHESIS
40
Patent #:
6421818
Issue Dt:
07/16/2002
Application #:
09027438
Filing Dt:
02/20/1998
Title:
EFFICIENT TOP-DOWN CHARACTERIZATION METHOD
41
Patent #:
6289491
Issue Dt:
09/11/2001
Application #:
09027501
Filing Dt:
02/20/1998
Title:
NETLIST ANALYSIS TOOL BY DEGREE OF CONFORMITY
42
Patent #:
6263483
Issue Dt:
07/17/2001
Application #:
09027512
Filing Dt:
02/20/1998
Title:
METHOD OF ACCESSING THE GENERIC NETLIST CREATED BY SYNOPSYS DESIGN COMPILIER
43
Patent #:
6292931
Issue Dt:
09/18/2001
Application #:
09027520
Filing Dt:
02/20/1998
Title:
RTL ANALYSIS TOOL
44
Patent #:
6253355
Issue Dt:
06/26/2001
Application #:
09031012
Filing Dt:
02/26/1998
Title:
METHOD FOR FAST ESTIMATION OF STEP RESPONSE BOUND DUE TO CAPACITANCE COUPLING FOR RC CIRCUITS
45
Patent #:
6093214
Issue Dt:
07/25/2000
Application #:
09031956
Filing Dt:
02/26/1998
Title:
STANDARD CELL INTEGRATED CIRCUIT LAYOUT DEFINITION HAVING FUNCTIONALLY UNCOMMITTED BASE CELLS
46
Patent #:
6499003
Issue Dt:
12/24/2002
Application #:
09034544
Filing Dt:
03/03/1998
Publication #:
US20020004714
Pub Dt:
01/10/2002
Title:
METHOD AND APPARATUS FOR APPLICATION OF PROXIMITY CORRECTION WITH UNITARY SEGMENTATION
47
Patent #:
6174630
Issue Dt:
01/16/2001
Application #:
09034550
Filing Dt:
03/03/1998
Title:
METHOD OF PROXIMITY CORRECTION WITH RELATIVE SEGMENTATION
48
Patent #:
6175953
Issue Dt:
01/16/2001
Application #:
09034658
Filing Dt:
03/03/1998
Title:
METHOD AND APPARATUS FOR GENERAL SYSTEMATIC APPLICATION OF PROXIMITY CORRECTION
49
Patent #:
5972541
Issue Dt:
10/26/1999
Application #:
09035110
Filing Dt:
03/04/1998
Title:
RETICLE AND METHOD OF DESIGN TO CORRECT PATTERN FOR DEPTH OF FOCUS PROBLEMS
50
Patent #:
6135649
Issue Dt:
10/24/2000
Application #:
09036846
Filing Dt:
03/09/1998
Title:
METHOD OF MODELING AND ANALYZING ELECTRONIC NOISE USING PADE APPROXIMATION-BASED MODEL-REDUCTION TECHNIQUES
51
Patent #:
6243849
Issue Dt:
06/05/2001
Application #:
09042230
Filing Dt:
03/13/1998
Title:
METHOD AND APPARATUS FOR NETLIST FILTERING AND CELL PLACEMENT
52
Patent #:
6028440
Issue Dt:
02/22/2000
Application #:
09045190
Filing Dt:
03/20/1998
Title:
ESTIMATION OF VOLTAGE DROP AND CURRENT DENSITIES IN ASIC POWER SUPPLY MESH
53
Patent #:
6141631
Issue Dt:
10/31/2000
Application #:
09047877
Filing Dt:
03/25/1998
Title:
PULSE REJECTION CIRCUIT MODEL PROGRAM AND TECHNIQUE IN VHDL
54
Patent #:
6334207
Issue Dt:
12/25/2001
Application #:
09050823
Filing Dt:
03/30/1998
Title:
METHOD FOR DESIGNING APPLICATION SPECIFIC INTEGRATED CIRCUITS
55
Patent #:
6178541
Issue Dt:
01/23/2001
Application #:
09050824
Filing Dt:
03/30/1998
Title:
PLD/ASIC HYBRID INTEGRATED CIRCUIT
56
Patent #:
6065134
Issue Dt:
05/16/2000
Application #:
09052043
Filing Dt:
03/30/1998
Title:
METHOD FOR REPAIRING AN ASIC MEMORY WITH REDUNDANCY ROW AND INPUT LINES
57
Patent #:
6028995
Issue Dt:
02/22/2000
Application #:
09052914
Filing Dt:
03/31/1998
Title:
METHOD OF DETERMINING DELAY IN LOGIC CELL MODELS
58
Patent #:
6353906
Issue Dt:
03/05/2002
Application #:
09053833
Filing Dt:
04/01/1998
Title:
TESTING SYNCHRONIZATION CIRCUITRY USING DIGITAL SIMULATION
59
Patent #:
6065145
Issue Dt:
05/16/2000
Application #:
09058839
Filing Dt:
04/13/1998
Title:
METHOD FOR TESTING PATH DELAY FAULTS IN SEQUENTIAL LOGIC CIRCUITS
60
Patent #:
6289495
Issue Dt:
09/11/2001
Application #:
09062205
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR LOCAL OPTIMIZATION OF THE GLOBAL ROUTING
61
Patent #:
6175950
Issue Dt:
01/16/2001
Application #:
09062217
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR HIERARCHICAL GLOBAL ROUTING DESCEND
62
Patent #:
6253363
Issue Dt:
06/26/2001
Application #:
09062218
Filing Dt:
04/17/1998
Title:
NET ROUTING USING BASIS ELEMENT DECOMPOSITION
63
Patent #:
6154874
Issue Dt:
11/28/2000
Application #:
09062219
Filing Dt:
04/17/1998
Title:
MEMORY-SAVING METHOD AND APPARATUS FOR PARTITIONING HIGH FANOUT NETS
64
Patent #:
6260183
Issue Dt:
07/10/2001
Application #:
09062246
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR COARSE GLOBAL ROUTING
65
Patent #:
6057169
Issue Dt:
05/02/2000
Application #:
09062254
Filing Dt:
04/17/1998
Title:
METHOD FOR I/O DEVICE LAYOUT DURING INTEGRATED CIRCUIT DESIGN
66
Patent #:
6324674
Issue Dt:
11/27/2001
Application #:
09062309
Filing Dt:
04/17/1998
Publication #:
US20010018759
Pub Dt:
08/30/2001
Title:
METHOD AND APPARATUS FOR PARALLEL SIMULTANEOUS GLOBAL AND DETAIL ROUTING
67
Patent #:
6230306
Issue Dt:
05/08/2001
Application #:
09062310
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR MINIMIZATION OF PROCESS DEFECTS WHILE ROUTING
68
Patent #:
6269469
Issue Dt:
07/31/2001
Application #:
09062418
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR PARALLEL ROUTING LOCKING MECHANISM
69
Patent #:
6247167
Issue Dt:
06/12/2001
Application #:
09062432
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR PARALLEL STEINER TREE ROUTING
70
Patent #:
6083271
Issue Dt:
07/04/2000
Application #:
09072566
Filing Dt:
05/05/1998
Title:
METHOD AND APPARATUS FOR SPECIFYING MULTIPLE POWER DOMAINS IN ELECTRONIC CIRCUIT DESIGNS
71
Patent #:
6327696
Issue Dt:
12/04/2001
Application #:
09072570
Filing Dt:
05/05/1998
Title:
METHOD AND APPARATUS FOR ZERO SKEW ROUTING FROM A FIXED H TRUNK
72
Patent #:
6088519
Issue Dt:
07/11/2000
Application #:
09081387
Filing Dt:
05/18/1998
Title:
METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
73
Patent #:
6687661
Issue Dt:
02/03/2004
Application #:
09085143
Filing Dt:
05/26/1998
Title:
UTILIZING A TECHNOLOGY-INDEPENDENT SYSTEM DESCRIPTION INCORPORATING A METAL LAYER DEPENDENT ATTRIBUTE
74
Patent #:
6397117
Issue Dt:
05/28/2002
Application #:
09085717
Filing Dt:
05/28/1998
Title:
DISTRIBUTED COMPUTER AIDED DESIGN SYSTEM AND METHOD
75
Patent #:
6225143
Issue Dt:
05/01/2001
Application #:
09089703
Filing Dt:
06/03/1998
Title:
FLIP-CHIP INTEGRATED CIRCUIT ROUTING TO I/O DEVICES
76
Patent #:
6256759
Issue Dt:
07/03/2001
Application #:
09097488
Filing Dt:
06/15/1998
Title:
HYBRID ALGORITHM FOR TEST POINT SELECTION FOR SCAN-BASED BIST
77
Patent #:
6128757
Issue Dt:
10/03/2000
Application #:
09098172
Filing Dt:
06/16/1998
Title:
LOW VOLTAGE SCREEN FOR IMPROVING THE FAULT COVERAGE OF INTEGRATED CIRCUIT PRODUCTION TEST PROGRAMS
78
Patent #:
6305001
Issue Dt:
10/16/2001
Application #:
09099287
Filing Dt:
06/18/1998
Title:
CLOCK DISTRIBUTION NETWORK PLANNING AND METHOD THEREFOR
79
Patent #:
6480989
Issue Dt:
11/12/2002
Application #:
09106890
Filing Dt:
06/29/1998
Publication #:
US20010049813
Pub Dt:
12/06/2001
Title:
AN INTEGRATED CIRCUIT DESIGN INCORPORATING A POWER MESH
80
Patent #:
6714903
Issue Dt:
03/30/2004
Application #:
09113995
Filing Dt:
07/10/1998
Title:
PLACEMENT AND ROUTING OF A BUFFER CIRCUIT FOR BUFFERING A SIGNAL EXTERNAL TO THE INTEGRATED CIRCUIT BEARING THE SINGLE CELL
81
Patent #:
6240542
Issue Dt:
05/29/2001
Application #:
09115464
Filing Dt:
07/14/1998
Title:
POLY ROUTING FOR CHIP INTERCONNECTS WITH MINIMAL IMPACT ON CHIP PERFORMANCE
82
Patent #:
6051027
Issue Dt:
04/18/2000
Application #:
09116158
Filing Dt:
07/16/1998
Title:
ELLICIENT THREE DIMENSIONAL EXTRACTION
83
Patent #:
6182272
Issue Dt:
01/30/2001
Application #:
09118661
Filing Dt:
07/16/1998
Title:
METAL LAYER ASSIGNMENT
84
Patent #:
6163865
Issue Dt:
12/19/2000
Application #:
09120396
Filing Dt:
07/22/1998
Title:
BUILT-IN SELF-TEST CIRCUIT FOR READ CHANNEL DEVICE
85
Patent #:
6412102
Issue Dt:
06/25/2002
Application #:
09120617
Filing Dt:
07/22/1998
Title:
WIRE ROUTING OPTIMIZATION
86
Patent #:
6170071
Issue Dt:
01/02/2001
Application #:
09123380
Filing Dt:
07/27/1998
Title:
METHOD FOR OPTIMIZING TEST FIXTURES TO MINIMIZE VECTOR LOAD TIME FOR AUTOMATED TEST EQUIPMENT
87
Patent #:
6154716
Issue Dt:
11/28/2000
Application #:
09126013
Filing Dt:
07/29/1998
Title:
SYSTEM AND METHOD FOR SIMULATING ELECTRONIC CIRCUITS
88
Patent #:
6094735
Issue Dt:
07/25/2000
Application #:
09128041
Filing Dt:
08/03/1998
Title:
SPEED-SIGNALING TESTING FOR INTEGRATED CIRCUITS
89
Patent #:
6321181
Issue Dt:
11/20/2001
Application #:
09138701
Filing Dt:
08/24/1998
Title:
DEVICE AND METHOD FOR PARALLEL SIMULATION
90
Patent #:
6345240
Issue Dt:
02/05/2002
Application #:
09138702
Filing Dt:
08/24/1998
Title:
DEVICE AND METHOD FOR PARALLEL SIMULATION TASK GENERATION AND DISTRIBUTION
91
Patent #:
6131174
Issue Dt:
10/10/2000
Application #:
09140564
Filing Dt:
08/27/1998
Title:
SYSTEM AND METHOD FOR TESTING OF EMBEDDED PROCESSOR
92
Patent #:
6687658
Issue Dt:
02/03/2004
Application #:
09144799
Filing Dt:
09/01/1998
Title:
APPARATUS AND METHOD FOR REDUCED-ORDER MODELING OF TIME-VARYING SYSTEMS AND COMPUTER STORAGE MEDIUM CONTAINING THE SAME
93
Patent #:
6370493
Issue Dt:
04/09/2002
Application #:
09151228
Filing Dt:
09/10/1998
Title:
SIMULATION FORMAT CREATION SYSTEM AND METHOD
94
Patent #:
6272671
Issue Dt:
08/07/2001
Application #:
09151900
Filing Dt:
09/11/1998
Title:
EXTRACTOR AND SCHEMATIC VIEWER FOR A DESIGN REPRESENTATION, AND ASSOCIATED METHOD
95
Patent #:
6216241
Issue Dt:
04/10/2001
Application #:
09168409
Filing Dt:
10/08/1998
Title:
METHOD AND SYSTEM FOR TESTING MULTIPORT MEMORIES
96
Patent #:
6317846
Issue Dt:
11/13/2001
Application #:
09170351
Filing Dt:
10/13/1998
Title:
SYSTEM AND METHOD FOR DETECTING FAULTS IN COMPUTER MEMORIES USING A LOOK UP TABLE
97
Patent #:
6397349
Issue Dt:
05/28/2002
Application #:
09170353
Filing Dt:
10/13/1998
Publication #:
US20020019957
Pub Dt:
02/14/2002
Title:
BUILT-IN-SELF-TEST AND SELF-REPAIR METHODS AND DEVICES FOR COMPUTER MEMORIES COMPRISING A RECONFIGURATION MEMORY DEVICE
98
Patent #:
6370664
Issue Dt:
04/09/2002
Application #:
09182543
Filing Dt:
10/29/1998
Title:
METHOD AND APARATUS FOR PARTITIONING LONG SCAN CHAINS IN SCAN BASED BIST ARCHITECHTURE
99
Patent #:
6174742
Issue Dt:
01/16/2001
Application #:
09183292
Filing Dt:
10/30/1998
Title:
OFF-GRID METAL LAYER UTILIZATION
100
Patent #:
6275973
Issue Dt:
08/14/2001
Application #:
09183637
Filing Dt:
10/30/1998
Title:
INTEGRATED CIRCUIT DESIGN WITH DELAYED CELL SELECTION
Assignors
1
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Exec Dt:
12/08/2017
2
BROADCOM CORPORATION
Exec Dt:
12/08/2017
Assignee
1
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE.
SUITE 1600
CHICAGO, ILLINOIS 60611
Correspondence name and address
CHAD S. HILYARD
401 N. MICHIGAN AVE.
SUITE 1600
CHICAGO, IL 60611

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