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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09187505
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Filing Dt:
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11/06/1998
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Title:
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QUADRATURE SOLUTIONS FOR 3D CAPACITANCE EXTRACTION
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09197977
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Filing Dt:
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11/23/1998
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Title:
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ARRANGEMENT FOR FAULT DETECTION IN CIRCUIT INTERCONNECTIONS
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09199018
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Filing Dt:
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11/24/1998
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Title:
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INSERTION OF TEST POINTS IN RTL DESIGNS
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09207191
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Filing Dt:
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12/08/1998
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Title:
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FILE DRIVEN MASK INSERTION FOR AUTOMATIC TEST EQUIPMENT TEST PATTERN GENERATION
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09207878
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Filing Dt:
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12/08/1998
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Title:
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MODIFIED DESIGN REPRESENTATION FOR FAST FAULT SIMULATION OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09212769
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Filing Dt:
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12/16/1998
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Title:
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INTEGRATED CIRCUIT DESIGN USING A FREQUENCY SYNTHESIZER THAT AUTOMATICALLY ENSURES TESTABILITY
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09233529
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Filing Dt:
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01/20/1999
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Title:
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METASTABILITY RISK SIMULATION ANALYSIS TOOL AND METHOD
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09233885
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Filing Dt:
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01/20/1999
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Title:
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HYBRID AERIAL IMAGE SIMULATION
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09234422
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Filing Dt:
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01/19/1999
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Title:
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GEOMETRIC AERIAL IMAGE SIMULATION
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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09240432
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Filing Dt:
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01/29/1999
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Title:
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APPARATUS AND METHOD FOR ANALYZING CIRCUITS USING REDUCED-ORDER MODELING OF LARGE LINEAR SUBCIRCUITS
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09265510
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Filing Dt:
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03/09/1999
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Title:
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PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09265932
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Filing Dt:
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03/11/1999
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Title:
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INTEGRATED CIRCUIT TESTING USING A HIGH SPEED DATA INTERFACE BUS
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09268867
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Filing Dt:
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03/16/1999
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Title:
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FLOOR PLAN-BASED POWER BUS ANALYSIS AND DESIGN TOOL FOR INTEGRATED CIRCUTIS
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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09268902
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Filing Dt:
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03/16/1999
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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FLOOR PLAN DEVELOPMENT ELECTROMIGRATION AND VOLTAGE DROP ANALYSIS TOOL
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09283392
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND APPARATUS FOR MODELING ELECTROMAGNETIC INTERACTIONS IN ELECTRICAL CIRCUIT METALIZATIONS TO SIMULATE THEIR ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09283393
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Filing Dt:
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04/01/1999
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Title:
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MEHTOD AND APPARATUS FOR QUASI FULL-WAVE MODELING OF INTERACTIONS IN CIRCUITS
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09283394
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND APPARATUS FOR MODELING ELECTROMAGNETIC INTERACTIONS IN ELECTRICAL CIRCUIT METALIZATIONS TO SIMULATE THEIR ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09283395
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND APPARATUS FOR MODELING ELECTROMAGNETIC INTERACTIONS IN ELECTRICAL CIRCUIT METALIZATIONS TO SIMULATE THEIR ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09287862
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Filing Dt:
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04/07/1999
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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CHIP-ON-CHIP TESTING USING BIST
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09290321
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Filing Dt:
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04/12/1999
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Title:
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DERIVING STATISTICAL DEVICE MODELS FROM ELECTRICAL TEST DATA
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09291157
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Filing Dt:
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04/12/1999
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Title:
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DERIVING STATISTICAL DEVICE MODELS FROM WORST-CASE FILES
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09291448
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Filing Dt:
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04/13/1999
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Title:
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BUILT-IN SELF-TEST FOR GENERATING A USAGE PROFILE TO IDENTIFY IDLE FUNCTIONAL UNIT OF AN INTEGRATED CIRCUIT DURING OPERATION FOR ON-LINE TESTING OF THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09299967
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Filing Dt:
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04/26/1999
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Title:
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COMPARING AERIAL IMAGE TO ACTUAL PHOTORESIST PATTERN FOR MASKING PROCESS CHARACTERIZATION
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09338338
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Filing Dt:
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06/23/1999
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Title:
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METHOD FOR IMPLEMENTING A BIST SCHEME INTO INTEGRATED CIRCUITS FOR TESTING RTL CONTROLLER-DATA PATHS IN THE INTEGRATED CIRCUITS.
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Patent #:
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Issue Dt:
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09/29/2009
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Application #:
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09344169
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Filing Dt:
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06/24/1999
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Title:
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DETERMINING TIMING OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09347628
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Filing Dt:
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07/02/1999
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Title:
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METHOD FOR IDENTIFYING CYCLICITY IN CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09350645
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Filing Dt:
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07/09/1999
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Title:
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SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE USING FFT ANALYSIS BASED ON A NON-ITERATIVE FFT COHERENCY ANALYSIS ALGORITHM
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09363311
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Filing Dt:
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07/28/1999
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Title:
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FUNCTIONAL-PATTERN MANAGEMENT SYSTEM FOR DEVICE VERIFICATION
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09400686
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Filing Dt:
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09/22/1999
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Title:
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SILICON VERIFICATION WITH EMBEDDED TESTBENCHES
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09408371
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Filing Dt:
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09/29/1999
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Title:
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ALMOST FULL-SCAN BIST METHOD AND SYSTEM HAVING HIGHER FAULT COVERAGE AND SHORTER TEST APPLICATION TIME
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09410405
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Filing Dt:
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10/01/1999
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Title:
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FLEXIBLE WIDTH CELL LAYOUT ARCHITECTURE
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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09427238
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Filing Dt:
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10/26/1999
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Title:
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SYSTEM AND METHOD FOR DETERMINING CAPACITANCE FOR LARGE-SCALE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09433702
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Filing Dt:
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11/03/1999
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Title:
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RATE EQUATION METHOD AND APPARATUS FOR SIMULATION OF CURRENT IN A MOS DEVICE
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09434961
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Filing Dt:
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11/05/1999
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Title:
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METHOD AND APPARATUS FOR EVALUATING AND CORRECTING ERRORS IN INTEGRATED CIRCUIT CHIP DESIGNS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09444975
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Filing Dt:
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11/22/1999
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Publication #:
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Pub Dt:
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06/14/2001
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09449324
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Filing Dt:
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11/24/1999
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Title:
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CAPACITANCE ESTIMATION
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09464623
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Filing Dt:
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12/16/1999
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Title:
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PROGRAMMABLE ASIC
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09464741
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Filing Dt:
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12/16/1999
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Title:
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METHOD FOR PROGRAMMING AN FPGA AND IMPLEMENTING AN FPGA INTERCONNECT USING CLOCK CONTROLS
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09470362
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Filing Dt:
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12/22/1999
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Title:
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CYCLE MODELING IN CYCLE ACCURATE SOFTWARE SIMULATORS OF HARDWARE MODULES FOR SOFTWARE/SOFTWARE CROSS-SIMULATION AND HARDWARE/SOFTWARE CO-SIMULATION
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09492881
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Filing Dt:
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01/26/2000
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Title:
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I/O DEVICE LAYOUT DURING INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09493467
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Filing Dt:
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01/28/2000
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Title:
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SPARE CELLS PLACEMENT METHODOLOGY
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09494605
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Filing Dt:
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01/31/2000
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Title:
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SYSTEMATIC SKEW REDUCTION THROUGH BUFFER RESIZING
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09497521
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Filing Dt:
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02/04/2000
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Title:
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PERIPHERAL PARTITIONING AND TREE DECOMPOSITION FOR PARTIAL SCAN
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09503691
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Filing Dt:
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02/14/2000
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Title:
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Advanced modular cell placement system with overlap remover with minimal noise
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09515250
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Filing Dt:
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02/29/2000
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Title:
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4K DERATING SCHEME FOR PROPAGATION DELAY AND SERUP/HOLD TIME COMPUTATION
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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09515376
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Filing Dt:
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02/29/2000
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Title:
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4 POINT DERATING SCHEMEM FOR PROPAGATION DELAY AND SETUP/HOLD TIME COMPUTATION
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09523224
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Filing Dt:
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03/10/2000
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Title:
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INTEGRATED CIRCUIT HAVING ON-CHIP CAPACITORS FOR SUPPLYING POWER TO PORTIONS OF THE CIRCUIT REQUIRING HIGH-TRANSIENT PEAK POWER
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09550764
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Filing Dt:
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04/17/2000
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Title:
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AUTOMATED SYSTEM FOR INSERTING AND READING OF PROBE POINTS IN SILICON EMBEDDED TESTBENCHES
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09564062
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Filing Dt:
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05/03/2000
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Title:
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WIRE ROUTING TO CONTROL SKEW
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09564438
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Filing Dt:
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05/04/2000
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Title:
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ON-CHIP DEBUGGER
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09567606
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Filing Dt:
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05/10/2000
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Title:
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METHOD AND APPARATUS FOR MATCHING CAPACITANCE OF FILTERS HAVING DIFFERENT CIRCUIT TOPOLOGIES
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09568049
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Filing Dt:
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05/10/2000
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Title:
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PERIPHERAL PARTITIONING AND TREE DECOMPOSITION FOR PARTIAL SCAN
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09573806
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Filing Dt:
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05/18/2000
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Title:
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SYSTEM AND METHOD FOR EFFICIENT LAYOUT OF FUNCTIONALLY EXTRANEOUS CELLS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09592749
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Filing Dt:
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06/13/2000
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Title:
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ITERARIVE PREDICTION OF CIRCUIT DELAYS
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09597433
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Filing Dt:
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06/20/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR RELEVANT LOGIC CELLS OF A CIRCUIT USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09626037
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Filing Dt:
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07/27/2000
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Title:
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METHOD AND APPARATUS FOR LOCATING CONSTANTS IN COMBINATIONAL CIRCUITS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09633795
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Filing Dt:
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08/07/2000
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Title:
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BOUNDARY SCAN CHAIN ROUTING
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09659090
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Filing Dt:
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09/11/2000
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Title:
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HARDWARE/SOFTWARE CO-SYNTHESIS OF HETEROGENEOUS LOW-POWER AND FAULT-TOLERANT SYSTEMS-ON-A CHIP
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09677276
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR DETECING EQUIVALENT AND ANTI-EQUIVALENT PINS
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09677475
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR TIMING DRIVEN RESYNTHESIS
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09677940
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR QUICK SEARCH FOR IDENTITIES APPLICABLE TO SPECIFIED FORMULA
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09678201
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Filing Dt:
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10/01/2000
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Title:
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METHOD AND APPARATUS FOR FORMULAE AREA AND DELAY MINIMIZATION
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09678478
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR DYNAMIC BUFFER AND INVERTER TREE OPTIMIZATION
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09678479
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR LOCAL RESYNTHESIS OF LOGIC TREES WITH MULTIPLE COST FUNCTIONS
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09678481
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR OPTIMAL CRITICAL NETLIST AREA SELECTION
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09680893
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR ANALYSIS OF TIMING MARGINS AND SIGNAL SKEWS OF RELEVANT LOGIC CELLS USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09684770
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR ISOLATING FAULTS FROM MULTIPLE FAILING PATHS IN A CIRCUIT USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09684868
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Filing Dt:
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10/06/2000
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Title:
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DIAGNOSTIC ARCHITECTURE USING FPGA CORE IN SYSTEM ON A CHIP DESIGN
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09685990
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Filing Dt:
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10/10/2000
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Title:
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METHOD AND APPARATUS FOR MINIMIZATION OF NET DELAY BY OPTIMAL BUFFER INSERTION
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Patent #:
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Issue Dt:
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01/15/2002
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Application #:
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09693014
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Filing Dt:
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10/20/2000
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Title:
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Off-grid metal layer utilization
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09710359
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Filing Dt:
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11/09/2000
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Title:
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METHOD TO TRANSLATE UDPS USING GATE PRIMITIVES
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09714370
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Filing Dt:
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11/14/2000
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Title:
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METHOD AND APPARATUS FOR APPLICATION OF PROXIMITY CORRECTION WITH RELATIVE SEGMENTATION
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09715814
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Filing Dt:
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11/17/2000
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Title:
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STANDARD LIBRARY GENERATOR FOR CELL TIMING MODEL
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09727426
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Filing Dt:
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11/30/2000
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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PIN PLACEMENT METHOD FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09734539
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Filing Dt:
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12/11/2000
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Title:
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A METHOD FOR MINIMIZING CLOCK SKEW BY RELOCATING A CLOCK BUFFER UNTIL CLOCK SKEW IS WITHIN A TOLERABLE LIMIT
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Patent #:
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Issue Dt:
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01/22/2002
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Application #:
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09735233
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Filing Dt:
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12/11/2000
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Title:
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Designing memory for testability to support scan capability in an asic design
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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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09735255
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Filing Dt:
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12/12/2000
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Title:
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DELAY/LOAD ESTIMATION FOR USE IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09735837
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Filing Dt:
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12/13/2000
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Title:
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CELL PIN EXTENSIONS FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09736571
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Filing Dt:
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12/14/2000
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Title:
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NETLIST RESYNTHESIS PROGRAM USING STRUCTURE CO-FACTORING
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09737239
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Filing Dt:
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12/14/2000
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Title:
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NETLIST RESYNTHESIS PROGRAM BASED ON PHYSICAL DELAY CALCULATION
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09756506
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Filing Dt:
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01/08/2001
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Title:
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FLIP CHIP TRACE LIBRARY GENERATOR
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09756561
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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Optimal clock timing schedule for an integrated circuit
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09756568
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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Process for fast cell placement in integrated circuit design
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09765827
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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09/13/2001
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Title:
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FLIP-CHIP INTEGRATED CIRCUIT ROUTING TO I/O DEVICES
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09771272
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Filing Dt:
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01/26/2001
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Title:
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ELMORE MODEL ENHANCEMENT
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09780861
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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SEQUENTIAL TEST PATTERN GENERATION USING COMBINATIONAL TECHNIQUES
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09788257
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Filing Dt:
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02/15/2001
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Title:
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BALANCED CLOCK PLACEMENT FOR INTEGRATED CIRCUITS CONTAINING MEGACELLS
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09789108
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Filing Dt:
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02/20/2001
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Title:
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PLACEMENT-BASED INTEGRATED CIRCUIT RE-SYNTHESIS TOOL USING ESTIMATED MAXIMUM INTERCONNECT CAPACITANCES
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09800532
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Filing Dt:
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03/06/2001
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Title:
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METHOD FOR MINIMIZING CLOCK SKEW FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09801392
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Filing Dt:
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03/07/2001
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Title:
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CELL INTERCONNECT DELAY LIBRARY FOR INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09802043
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Filing Dt:
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03/08/2001
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Title:
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GRIDLESS ROUTER USING MAZE AND LINE PROBE TECHNIQUES
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09802198
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Filing Dt:
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03/08/2001
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Title:
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BUILT-IN-SELF REPAIR CIRCUITRY UTILIZING PERMANENT RECORD OF DEFECTS
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09804939
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Filing Dt:
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03/13/2001
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Title:
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CHANNEL ROUTER WITH BUFFER INSERTION
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09805642
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Filing Dt:
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03/13/2001
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Title:
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METHOD OF DATAPATH CELL PLACEMENT FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09808510
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Filing Dt:
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03/14/2001
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Title:
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METHOD FOR ESTIMATING POROSITY OF HARDMACS
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09808549
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Filing Dt:
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03/14/2001
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Title:
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FULL-CHIP EXTRACTION OF INTERCONNECT PARASITIC DATA
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09814417
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Filing Dt:
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03/21/2001
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Title:
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DRIVER WAVEFORM MODELING WITH MULTIPLE EFFECTIVE CAPACITANCES
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09820059
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Filing Dt:
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03/28/2001
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Title:
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DISTRIBUTION DEPENDENT CLUSTERING IN BUFFER INSERTION OF HIGH FANOUT NETS
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09823184
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Filing Dt:
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03/29/2001
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Title:
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METHOD OF DATAPATH CELL PLACEMENT FOR BITWISE AND NON-BITWISE INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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09827434
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Filing Dt:
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04/06/2001
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Title:
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WIRE DELAY DISTRIBUTED MODEL
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