USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	044887/0109			Pages:	80
		Recorded:	12/17/2017
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 935
Page 6 of 10
Pages: 1 2 3 4 5 6 7 8 9 10

Patent #:	6735747	Issue Dt:	05/11/2004	Application #:	10166797	Filing Dt:	06/10/2002
Publication #:	US20030229864	Pub Dt:	12/11/2003
Title:	PRE-SILICON VERIFICATION PATH COVERAGE

Patent #:	7818157	Issue Dt:	10/19/2010	Application #:	10174681	Filing Dt:	06/19/2002
Publication #:	US20030237059	Pub Dt:	12/25/2003
Title:	INSTANTANEOUS VOLTAGE DROP SENSITIVITY ANALYSIS TOOL (IVDSAT)

Patent #:	7003510	Issue Dt:	02/21/2006	Application #:	10177591	Filing Dt:	06/19/2002
Publication #:	US20030236774	Pub Dt:	12/25/2003
Title:	TABLE MODULE COMPILER EQUIVALENT TO ROM

Patent #:	6842883	Issue Dt:	01/11/2005	Application #:	10178193	Filing Dt:	06/24/2002
Publication #:	US20030237062	Pub Dt:	12/25/2003
Title:	APPLICATION OF CO-VERIFICATION TOOLS TO THE TESTING OF IC DESIGNS

Patent #:	6769097	Issue Dt:	07/27/2004	Application #:	10185740	Filing Dt:	06/27/2002
Publication #:	US20040003354	Pub Dt:	01/01/2004
Title:	SCALE-INVARIANT TOPOLOGY AND TRAFFIC ALLOCATION IN MULTI-NODE SYSTEM-ON-CHIP SWITCHING FABRICS

Patent #:	7127692	Issue Dt:	10/24/2006	Application #:	10186263	Filing Dt:	06/27/2002
Publication #:	US20040003362	Pub Dt:	01/01/2004
Title:	TIMING ABSTRACTION AND PARTITIONING STRATEGY

Patent #:	6810505	Issue Dt:	10/26/2004	Application #:	10192989	Filing Dt:	07/10/2002
Publication #:	US20040010761	Pub Dt:	01/15/2004
Title:	INTEGRATED CIRCUIT DESIGN FLOW WITH CAPACITIVE MARGIN

Patent #:	6532431	Issue Dt:	03/11/2003	Application #:	10194134	Filing Dt:	07/12/2002
Title:	RATIO TESTING

Patent #:	6857108	Issue Dt:	02/15/2005	Application #:	10210651	Filing Dt:	07/31/2002
Publication #:	US20040025119	Pub Dt:	02/05/2004
Title:	INTERACTIVE REPRESENTATION OF STRUCTURAL DEPENDENCIES IN SEMICONDUCTOR DESIGN FLOWS

Patent #:	6775818	Issue Dt:	08/10/2004	Application #:	10223931	Filing Dt:	08/20/2002
Publication #:	US20040040000	Pub Dt:	02/26/2004
Title:	DEVICE PARAMETER AND GATE PERFORMANCE SIMULATION BASED ON WAFER IMAGE PREDICTION

Patent #:	6802047	Issue Dt:	10/05/2004	Application #:	10224019	Filing Dt:	08/19/2002
Title:	CALCULATING RESISTANCE OF CONDUCTOR LAYER FOR INTEGRATED CIRCUIT DESIGN

Patent #:	6785871	Issue Dt:	08/31/2004	Application #:	10225909	Filing Dt:	08/21/2002
Publication #:	US20040040002	Pub Dt:	02/26/2004
Title:	AUTOMATIC RECOGNITION OF AN OPTICALLY PERIODIC STRUCTURE IN AN INTEGRATED CIRCUIT DESIGN

Patent #:	6874108	Issue Dt:	03/29/2005	Application #:	10228444	Filing Dt:	08/27/2002
Title:	FAULT TOLERANT OPERATION OF RECONFIGURABLE DEVICES UTILIZING AN ADJUSTABLE SYSTEM CLOCK

Patent #:	7212961	Issue Dt:	05/01/2007	Application #:	10231641	Filing Dt:	08/30/2002
Publication #:	US20040044875	Pub Dt:	03/04/2004
Title:	INTERFACE FOR RAPID PROTOTYPING SYSTEM

Patent #:	7299427	Issue Dt:	11/20/2007	Application #:	10231643	Filing Dt:	08/30/2002
Publication #:	US20040044876	Pub Dt:	03/04/2004
Title:	RAPID PROTOTYPING SYSTEM

Patent #:	6748579	Issue Dt:	06/08/2004	Application #:	10231904	Filing Dt:	08/30/2002
Publication #:	US20040044983	Pub Dt:	03/04/2004
Title:	METHOD OF USING FILLLER METAL FOR IMPLEMENTING CHANGES IN AN INTEGRATED CIRCUIT DESIGN

Patent #:	6851098	Issue Dt:	02/01/2005	Application #:	10232423	Filing Dt:	08/28/2002
Publication #:	US20040044976	Pub Dt:	03/04/2004
Title:	STATIC TIMING ANALYSIS AND PERFORMANCE DIAGNOSTIC DISPLAY TOOL

Patent #:	6782525	Issue Dt:	08/24/2004	Application #:	10236207	Filing Dt:	09/05/2002
Publication #:	US20040049760	Pub Dt:	03/11/2004
Title:	WAFER PROCESS CRITICAL DIMENSION, ALIGNMENT, AND REGISTRATION ANALYSIS SIMULATION TOOL

Patent #:	7043703	Issue Dt:	05/09/2006	Application #:	10241317	Filing Dt:	09/11/2002
Publication #:	US20040049604	Pub Dt:	03/11/2004
Title:	ARCHITECTURE AND/OR METHOD FOR USING INPUT/OUTPUT AFFINITY REGION FOR FLEXIBLE USE OF HARD MACRO I/O BUFFERS

Patent #:	6894762	Issue Dt:	05/17/2005	Application #:	10246286	Filing Dt:	09/17/2002
Title:	DUAL SOURCE LITHOGRAPHY FOR DIRECT WRITE APPLICATION

Patent #:	6747473	Issue Dt:	06/08/2004	Application #:	10252488	Filing Dt:	09/23/2002
Publication #:	US20040059971	Pub Dt:	03/25/2004
Title:	DEVICE UNDER TEST INTERFACE CARD WITH ON-BOARD TESTING

Patent #:	6701495	Issue Dt:	03/02/2004	Application #:	10253006	Filing Dt:	09/23/2002
Title:	MODEL OF THE CONTACT REGION OF INTEGRATED CIRCUIT RESISTORS

Patent #:	6893800	Issue Dt:	05/17/2005	Application #:	10254083	Filing Dt:	09/24/2002
Publication #:	US20040058255	Pub Dt:	03/25/2004
Title:	SUBSTRATE TOPOGRAPHY COMPENSATION AT MASK DESIGN: 3D OPC TOPOGRAPHY ANCHORED

Patent #:	6810515	Issue Dt:	10/26/2004	Application #:	10254380	Filing Dt:	09/25/2002
Publication #:	US20040060012	Pub Dt:	03/25/2004
Title:	PROCESS OF RESTRUCTURING LOGICS IN ICS FOR SETUP AND HOLD TIME OPTIMIZATION

Patent #:	6760896	Issue Dt:	07/06/2004	Application #:	10254607	Filing Dt:	09/25/2002
Publication #:	US20040060027	Pub Dt:	03/25/2004
Title:	PROCESS LAYOUT OF BUFFER MODULES IN INTEGRATED CIRCUITS

Patent #:	6804811	Issue Dt:	10/12/2004	Application #:	10254616	Filing Dt:	09/25/2002
Publication #:	US20040060029	Pub Dt:	03/25/2004
Title:	PROCESS FOR LAYOUT OF MEMORY MATRICES IN INTEGRATED CIRCUITS

Patent #:	6871333	Issue Dt:	03/22/2005	Application #:	10265803	Filing Dt:	10/07/2002
Publication #:	US20040068704	Pub Dt:	04/08/2004
Title:	BENT GATE TRANSISTOR MODELING

Patent #:	6782523	Issue Dt:	08/24/2004	Application #:	10271026	Filing Dt:	10/15/2002
Publication #:	US20040073883	Pub Dt:	04/15/2004
Title:	PARALLEL CONFIGURABLE IP DESIGN METHODOLOGY

Patent #:	6880142	Issue Dt:	04/12/2005	Application #:	10272182	Filing Dt:	10/16/2002
Publication #:	US20040078765	Pub Dt:	04/22/2004
Title:	METHOD OF DELAY CALCULATION FOR VARIATION IN INTERCONNECT METAL PROCESS

Patent #:	6941533	Issue Dt:	09/06/2005	Application #:	10277398	Filing Dt:	10/21/2002
Publication #:	US20040078766	Pub Dt:	04/22/2004
Title:	CLOCK TREE SYNTHESIS WITH SKEW FOR MEMORY DEVICES

Patent #:	6795954	Issue Dt:	09/21/2004	Application #:	10278150	Filing Dt:	10/21/2002
Publication #:	US20040076067	Pub Dt:	04/22/2004
Title:	METHOD OF DECREASING INSTANTANEOUS CURRENT WITHOUT AFFECTING TIMING

Patent #:	7322021	Issue Dt:	01/22/2008	Application #:	10285301	Filing Dt:	10/31/2002
Publication #:	US20040088668	Pub Dt:	05/06/2004
Title:	VIRTUAL PATH FOR INTERCONNECT FABRIC USING BANDWIDTH PROCESS

Patent #:	6961915	Issue Dt:	11/01/2005	Application #:	10290019	Filing Dt:	11/06/2002
Publication #:	US20040088669	Pub Dt:	05/06/2004
Title:	DESIGN METHODOLOGY FOR DUMMY LINES

Patent #:	7103868	Issue Dt:	09/05/2006	Application #:	10291982	Filing Dt:	11/12/2002
Publication #:	US20040093578	Pub Dt:	05/13/2004
Title:	OPTIMIZING DEPTHS OF CIRCUITS FOR BOOLEAN FUNCTIONS

Patent #:	6868536	Issue Dt:	03/15/2005	Application #:	10299564	Filing Dt:	11/19/2002
Publication #:	US20040098676	Pub Dt:	05/20/2004
Title:	METHOD TO FIND BOOLEAN FUNCTION SYMMETRIES

Patent #:	7082583	Issue Dt:	07/25/2006	Application #:	10301069	Filing Dt:	11/20/2002
Publication #:	US20040098677	Pub Dt:	05/20/2004
Title:	METHOD FOR REDUCING A PARASITIC GRAPH IN MOMENT COMPUTATION IN VLSI SYSTEMS

Patent #:	7024636	Issue Dt:	04/04/2006	Application #:	10301182	Filing Dt:	11/20/2002
Publication #:	US20040098689	Pub Dt:	05/20/2004
Title:	CHIP MANAGEMENT SYSTEM

Patent #:	7017126	Issue Dt:	03/21/2006	Application #:	10304289	Filing Dt:	11/26/2002
Publication #:	US20030226120	Pub Dt:	12/04/2003
Title:	METACORES: DESIGN AND OPTIMIZATION TECHNIQUES

Patent #:	6768958	Issue Dt:	07/27/2004	Application #:	10305673	Filing Dt:	11/26/2002
Publication #:	US20040102912	Pub Dt:	05/27/2004
Title:	AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR

Patent #:	6597189	Issue Dt:	07/22/2003	Application #:	10306064	Filing Dt:	11/27/2002
Title:	SOCKETLESS/BOARDLESS TEST INTERPOSER CARD

Patent #:	6701499	Issue Dt:	03/02/2004	Application #:	10308557	Filing Dt:	12/03/2002
Publication #:	US20030237068	Pub Dt:	12/25/2003
Title:	EFFECTIVE APPROXIMATED CALCULATION OF SMOOTH FUNCTIONS

Patent #:	6757883	Issue Dt:	06/29/2004	Application #:	10316594	Filing Dt:	12/11/2002
Publication #:	US20040117751	Pub Dt:	06/17/2004
Title:	ESTIMATING FREE SPACE IN IC CHIPS

Patent #:	7069523	Issue Dt:	06/27/2006	Application #:	10318623	Filing Dt:	12/13/2002
Publication #:	US20040117744	Pub Dt:	06/17/2004
Title:	AUTOMATED SELECTION AND PLACEMENT OF MEMORY DURING DESIGN OF AN INTEGRATED CIRCUIT

Patent #:	6922823	Issue Dt:	07/26/2005	Application #:	10318639	Filing Dt:	12/13/2002
Publication #:	US20040117748	Pub Dt:	06/17/2004
Title:	METHOD FOR CREATING DERIVATIVE INTEGRATED CIRCUIT LAYOUTS FOR RELATED PRODUCTS

Patent #:	6948139	Issue Dt:	09/20/2005	Application #:	10326717	Filing Dt:	12/19/2002
Publication #:	US20040123251	Pub Dt:	06/24/2004
Title:	METHOD FOR COMBINING STATES

Patent #:	7093228	Issue Dt:	08/15/2006	Application #:	10327304	Filing Dt:	12/20/2002
Publication #:	US20040123265	Pub Dt:	06/24/2004
Title:	METHOD AND SYSTEM FOR CLASSIFYING AN INTEGRATED CIRCUT FOR OPTICAL PROXIMITY CORRECTION

Patent #:	6898780	Issue Dt:	05/24/2005	Application #:	10327314	Filing Dt:	12/20/2002
Publication #:	US20040123266	Pub Dt:	06/24/2004
Title:	METHOD AND SYSTEM FOR CONSTRUCTING A HIERARCHY-DRIVEN CHIP COVERING FOR OPTICAL PROXIMITY CORRECTION

Patent #:	6911285	Issue Dt:	06/28/2005	Application #:	10327451	Filing Dt:	12/20/2002
Publication #:	US20040121242	Pub Dt:	06/24/2004
Title:	SIDELOBE CORRECTION FOR ATTENUATED PHASE SHIFT MASKS

Patent #:	7313508	Issue Dt:	12/25/2007	Application #:	10330929	Filing Dt:	12/27/2002
Publication #:	US20040128118	Pub Dt:	07/01/2004
Title:	PROCESS WINDOW COMPLIANT CORRECTIONS OF DESIGN LAYOUT

Patent #:	6854103	Issue Dt:	02/08/2005	Application #:	10331521	Filing Dt:	12/30/2002
Publication #:	US20040128637	Pub Dt:	07/01/2004
Title:	APPARATUS AND METHOD FOR VISUALIZING AND ANALYZING RESISTANCE NETWORKS

Patent #:	6823502	Issue Dt:	11/23/2004	Application #:	10334568	Filing Dt:	12/31/2002
Publication #:	US20040128626	Pub Dt:	07/01/2004
Title:	PLACEMENT OF CONFIGURABLE INPUT/OUTPUT BUFFER STRUCTURES DURING DESIGN OF INTEGRATED CIRCUITS

Patent #:	6757885	Issue Dt:	06/29/2004	Application #:	10334570	Filing Dt:	12/31/2002
Publication #:	US20040128640	Pub Dt:	07/01/2004
Title:	LENGTH MATRIX GENERATOR FOR REGISTER TRANSFER LEVEL CODE

Patent #:	6848094	Issue Dt:	01/25/2005	Application #:	10334731	Filing Dt:	12/31/2002
Publication #:	US20040128632	Pub Dt:	07/01/2004
Title:	NETLIST REDUNDANCY DETECTION AND GLOBAL SIMPLIFICATION

Patent #:	6907588	Issue Dt:	06/14/2005	Application #:	10334743	Filing Dt:	12/31/2002
Publication #:	US20040128639	Pub Dt:	07/01/2004
Title:	CONGESTION ESTIMATION FOR REGISTER TRANSFER LEVEL CODE

Patent #:	7055113	Issue Dt:	05/30/2006	Application #:	10335360	Filing Dt:	12/31/2002
Publication #:	US20040128641	Pub Dt:	07/01/2004
Title:	SIMPLIFIED PROCESS TO DESIGN INTEGRATED CIRCUITS

Patent #:	7005873	Issue Dt:	02/28/2006	Application #:	10335540	Filing Dt:	12/31/2002
Publication #:	US20040128600	Pub Dt:	07/01/2004
Title:	BUILT-IN SELF-TEST HIERARCHY FOR AN INTEGRATED CIRCUIT

Patent #:	6898770	Issue Dt:	05/24/2005	Application #:	10339821	Filing Dt:	01/09/2003
Publication #:	US20040139408	Pub Dt:	07/15/2004
Title:	SPLIT AND MERGE DESIGN FLOW CONCEPT FOR FAST TURNAROUND TIME OF CIRCUIT LAYOUT DESIGN

Patent #:	6934929	Issue Dt:	08/23/2005	Application #:	10341119	Filing Dt:	01/13/2003
Publication #:	US20040139420	Pub Dt:	07/15/2004
Title:	METHOD FOR IMPROVING OPC MODELING

Patent #:	6817004	Issue Dt:	11/09/2004	Application #:	10349564	Filing Dt:	01/22/2003
Publication #:	US20040143809	Pub Dt:	07/22/2004
Title:	NET SEGMENT ANALYZER FOR CHIP CAD LAYOUT

Patent #:	6978428	Issue Dt:	12/20/2005	Application #:	10369269	Filing Dt:	02/14/2003
Publication #:	US20040163055	Pub Dt:	08/19/2004
Title:	A MODE REGISTER IN AN INTEGRATED CIRCUIT THAT STORES TEST SCRIPTS AND OPERATING PARAMETERS

Patent #:	6901573	Issue Dt:	05/31/2005	Application #:	10382036	Filing Dt:	03/05/2003
Publication #:	US20040177330	Pub Dt:	09/09/2004
Title:	METHOD FOR EVALUATING LOGIC FUNCTIONS BY LOGIC CIRCUITS HAVING OPTIMIZED NUMBER OF AND/OR SWITCHES

Patent #:	7200785	Issue Dt:	04/03/2007	Application #:	10387988	Filing Dt:	03/13/2003
Publication #:	US20040181719	Pub Dt:	09/16/2004
Title:	SEQUENTIAL TESTER FOR LONGEST PREFIX SEARCH ENGINES

Patent #:	6807656	Issue Dt:	10/19/2004	Application #:	10407065	Filing Dt:	04/03/2003
Publication #:	US20040199882	Pub Dt:	10/07/2004
Title:	DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS

Patent #:	6922817	Issue Dt:	07/26/2005	Application #:	10408205	Filing Dt:	04/04/2003
Publication #:	US20040199879	Pub Dt:	10/07/2004
Title:	SYSTEM AND METHOD FOR ACHIEVING TIMING CLOSURE IN FIXED PLACED DESIGNS AFTER IMPLEMENTING LOGIC CHANGES

Patent #:	7284211	Issue Dt:	10/16/2007	Application #:	10417007	Filing Dt:	04/16/2003
Publication #:	US20040221197	Pub Dt:	11/04/2004
Title:	EXTENSIBLE IO TESTING IMPLEMENTATION

Patent #:	7127698	Issue Dt:	10/24/2006	Application #:	10417706	Filing Dt:	04/17/2003
Publication #:	US20040210595	Pub Dt:	10/21/2004
Title:	METHOD FOR REDUCING RETICLE SET COST

Patent #:	6728936	Issue Dt:	04/27/2004	Application #:	10425155	Filing Dt:	04/29/2003
Title:	DATAPATH BITSLICE TECHNOLOGY

Patent #:	7062726	Issue Dt:	06/13/2006	Application #:	10426549	Filing Dt:	04/30/2003
Publication #:	US20040221247	Pub Dt:	11/04/2004
Title:	METHOD FOR GENERATING TECH-LIBRARY FOR LOGIC FUNCTION

Patent #:	7082584	Issue Dt:	07/25/2006	Application #:	10427609	Filing Dt:	04/30/2003
Publication #:	US20040221249	Pub Dt:	11/04/2004
Title:	AUTOMATED ANALYSIS OF RTL CODE CONTAINING ASIC VENDOR RULES

Patent #:	6771085	Issue Dt:	08/03/2004	Application #:	10428200	Filing Dt:	04/30/2003
Publication #:	US20040100292	Pub Dt:	05/27/2004
Title:	SOCKETLESS/BOARDLESS TEST INTERPOSER CARD

Patent #:	7263470	Issue Dt:	08/28/2007	Application #:	10429312	Filing Dt:	05/05/2003
Publication #:	US20040225481	Pub Dt:	11/11/2004
Title:	DIGITAL GAUSSIAN NOISE SIMULATOR

Patent #:	7020852	Issue Dt:	03/28/2006	Application #:	10435168	Filing Dt:	05/08/2003
Publication #:	US20040225972	Pub Dt:	11/11/2004
Title:	AUTOMATION OF THE DEVELOPMENT, TESTING, AND RELEASE OF A FLOW FRAMEWORK AND METHODOLOGY TO DESIGN INTEGRATED CIRCUITS

Patent #:	6990651	Issue Dt:	01/24/2006	Application #:	10438530	Filing Dt:	05/14/2003
Publication #:	US20040230919	Pub Dt:	11/18/2004
Title:	ADVANCED DESIGN FORMAT LIBRARY FOR INTEGRATED CIRCUIT DESIGN SYNTHESIS AND FLOORPLANNING TOOLS

Patent #:	7007248	Issue Dt:	02/28/2006	Application #:	10439373	Filing Dt:	05/15/2003
Publication #:	US20040230920	Pub Dt:	11/18/2004
Title:	METHOD AND APPARATUS FOR IMPLEMENTING ENGINEERING CHANGE ORDERS

Patent #:	7047470	Issue Dt:	05/16/2006	Application #:	10441000	Filing Dt:	05/19/2003
Publication #:	US20040210806	Pub Dt:	10/21/2004
Title:	FLEXIBLE AND EXTENSIBLE IMPLEMENTATION OF SHARING TEST PINS IN ASIC

Patent #:	7899659	Issue Dt:	03/01/2011	Application #:	10452260	Filing Dt:	06/02/2003
Publication #:	US20040243372	Pub Dt:	12/02/2004
Title:	RECORDING AND DISPLAYING LOGIC CIRCUIT SIMULATION WAVEFORMS

Patent #:	7020859	Issue Dt:	03/28/2006	Application #:	10452689	Filing Dt:	06/02/2003
Publication #:	US20040241990	Pub Dt:	12/02/2004
Title:	PROCESS SKEW RESULTS FOR INTEGRATED CIRCUITS

Patent #:	7069535	Issue Dt:	06/27/2006	Application #:	10453182	Filing Dt:	06/03/2003
Publication #:	US20040250232	Pub Dt:	12/09/2004
Title:	OPTICAL PROXIMITY CORRECTION METHOD USING WEIGHTED PRIORITIES

Patent #:	6948142	Issue Dt:	09/20/2005	Application #:	10453819	Filing Dt:	06/02/2003
Publication #:	US20040243956	Pub Dt:	12/02/2004
Title:	INTELLIGENT ENGINE FOR PROTECTION AGAINST INJECTED CROSSTALK DELAY

Patent #:	7043708	Issue Dt:	05/09/2006	Application #:	10458547	Filing Dt:	06/09/2003
Publication #:	US20040250225	Pub Dt:	12/09/2004
Title:	INTELLIGENT CROSSTALK DELAY ESTIMATOR FOR INTEGRATED CIRCUIT DESIGN FLOW

Patent #:	6871154	Issue Dt:	03/22/2005	Application #:	10459158	Filing Dt:	06/11/2003
Publication #:	US20040254755	Pub Dt:	12/16/2004
Title:	METHOD AND APPARATUS FOR AUTOMATICALLY CONFIGURING AND/OR INSERTING CHIP RESOURCES FOR MANUFACTURING TESTS

Patent #:	6959428	Issue Dt:	10/25/2005	Application #:	10465186	Filing Dt:	06/19/2003
Publication #:	US20040261050	Pub Dt:	12/23/2004
Title:	DESIGNING AND TESTING THE INTERCONNECTION OF ADDRESSABLE DEVICES OF INTEGRATED CIRCUITS

Patent #:	7412343	Issue Dt:	08/12/2008	Application #:	10516583	Filing Dt:	03/24/2005
Publication #:	US20050154552	Pub Dt:	07/14/2005
Title:	METHODS FOR DELAY-FAULT TESTING IN FIELD-PROGRAMMABLE GATE ARRAYS

Patent #:	7020865	Issue Dt:	03/28/2006	Application #:	10602570	Filing Dt:	06/24/2003
Publication #:	US20050005255	Pub Dt:	01/06/2005
Title:	PROCESS FOR DESIGNING COMPARATORS AND ADDERS OF SMALL DEPTH

Patent #:	7062736	Issue Dt:	06/13/2006	Application #:	10602937	Filing Dt:	06/24/2003
Publication #:	US20040268279	Pub Dt:	12/30/2004
Title:	TIMING CONSTRAINT GENERATOR

Patent #:	7287238	Issue Dt:	10/23/2007	Application #:	10603905	Filing Dt:	06/25/2003
Publication #:	US20040267517	Pub Dt:	12/30/2004
Title:	METHOD AND APPARATUS FOR EXPOSING PRE-DIFFUSED IP BLOCKS IN A SEMICONDUCTOR DEVICE FOR PROTOTYPING BASED ON HARDWARE EMULATION

Patent #:	7096442	Issue Dt:	08/22/2006	Application #:	10616623	Filing Dt:	07/10/2003
Publication #:	US20050010884	Pub Dt:	01/13/2005
Title:	OPTIMIZING IC CLOCK STRUCTURES BY MINIMIZING CLOCK UNCERTAINTY

Patent #:	6946866	Issue Dt:	09/20/2005	Application #:	10620057	Filing Dt:	07/15/2003
Publication #:	US20040251925	Pub Dt:	12/16/2004
Title:	MEASUREMENT OF PACKAGE INTERCONNECT IMPEDANCE USING TESTER AND SUPPORTING TESTER

Patent #:	7743391	Issue Dt:	06/22/2010	Application #:	10620581	Filing Dt:	07/15/2003
Publication #:	US20050015439	Pub Dt:	01/20/2005
Title:	FLEXIBLE ARCHITECTURE COMPONENT (FAC) FOR EFFICIENT DATA INTEGRATION AND INFORMATION INTERCHANGE USING WEB SERVICES

Patent #:	7082593	Issue Dt:	07/25/2006	Application #:	10621737	Filing Dt:	07/17/2003
Publication #:	US20050013155	Pub Dt:	01/20/2005
Title:	METHOD AND APPARATUS OF IC IMPLEMENTATION BASED ON C++ LANGUAGE DESCRIPTION

Patent #:	7096440	Issue Dt:	08/22/2006	Application #:	10624347	Filing Dt:	07/22/2003
Publication #:	US20050022058	Pub Dt:	01/27/2005
Title:	METHODS AND SYSTEMS FOR AUTOMATIC VERIFICATION OF SPECIFICATION DOCUMENT TO HARDWARE DESIGN

Patent #:	7058906	Issue Dt:	06/06/2006	Application #:	10626825	Filing Dt:	07/23/2003
Publication #:	US20040139415	Pub Dt:	07/15/2004
Title:	ARCHITECTURE FOR A SEA OF PLATFORMS

Patent #:	7007259	Issue Dt:	02/28/2006	Application #:	10632622	Filing Dt:	07/31/2003
Publication #:	US20050028121	Pub Dt:	02/03/2005
Title:	METHOD FOR PROVIDING CLOCK-NET AWARE DUMMY METAL USING DUMMY REGIONS

Patent #:	6988252	Issue Dt:	01/17/2006	Application #:	10633856	Filing Dt:	08/04/2003
Publication #:	US20050030067	Pub Dt:	02/10/2005
Title:	UNIVERSAL GATES FOR ICS AND TRANSFORMATION OF NETLISTS FOR THEIR IMPLEMENTATION

Patent #:	7051297	Issue Dt:	05/23/2006	Application #:	10634634	Filing Dt:	08/04/2003
Publication #:	US20050034088	Pub Dt:	02/10/2005
Title:	METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES

Patent #:	6925626	Issue Dt:	08/02/2005	Application #:	10640738	Filing Dt:	08/13/2003
Publication #:	US20050039154	Pub Dt:	02/17/2005
Title:	METHOD OF ROUTING A REDISTRIBUTION LAYER TRACE IN AN INTEGRATED CIRCUIT DIE

Patent #:	6825688	Issue Dt:	11/30/2004	Application #:	10641799	Filing Dt:	08/15/2003
Title:	SYSTEM FOR YIELD ENHANCEMENT IN PROGRAMMABLE LOGIC

Patent #:	7076759	Issue Dt:	07/11/2006	Application #:	10649215	Filing Dt:	08/26/2003
Publication #:	US20050050504	Pub Dt:	03/03/2005
Title:	METHODOLOGY FOR GENERATING A MODIFIED VIEW OF A CIRCUIT LAYOUT

Patent #:	7039891	Issue Dt:	05/02/2006	Application #:	10650296	Filing Dt:	08/27/2003
Publication #:	US20050050497	Pub Dt:	03/03/2005
Title:	METHOD OF CLOCK DRIVEN CELL PLACEMENT AND CLOCK TREE SYNTHESIS FOR INTEGRATED CIRCUIT DESIGN

100

Patent #:	7028276	Issue Dt:	04/11/2006	Application #:	10659138	Filing Dt:	09/10/2003
Publication #:	US20050055649	Pub Dt:	03/10/2005
Title:	FIRST TIME SILICON AND PROTO TEST CELL NOTIFICATION

Assignors

AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Exec Dt:

12/08/2017

BROADCOM CORPORATION

Exec Dt:

12/08/2017

Assignee

BELL SEMICONDUCTOR, LLC

401 N. MICHIGAN AVE.

SUITE 1600

CHICAGO, ILLINOIS 60611

Correspondence name and address
	CHAD S. HILYARD
	401 N. MICHIGAN AVE.
	SUITE 1600
	CHICAGO, IL 60611

Search Results as of: 05/13/2024 02:29 PM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6