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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:044887/0109   Pages: 80
Recorded: 12/17/2017
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 935
Page 8 of 10
Pages: 1 2 3 4 5 6 7 8 9 10
1
Patent #:
7257791
Issue Dt:
08/14/2007
Application #:
10992999
Filing Dt:
11/19/2004
Publication #:
US20060112363
Pub Dt:
05/25/2006
Title:
MULTIPLE BUFFER INSERTION IN GLOBAL ROUTING
2
Patent #:
7189498
Issue Dt:
03/13/2007
Application #:
10993603
Filing Dt:
11/19/2004
Publication #:
US20050153246
Pub Dt:
07/14/2005
Title:
PROCESS AND APPARATUS FOR GENERATING A STRONG PHASE SHIFT OPTICAL PATTERN FOR USE IN AN OPTICAL DIRECT WRITE LITHOGRAPHY PROCESS
3
Patent #:
7213223
Issue Dt:
05/01/2007
Application #:
10994114
Filing Dt:
11/19/2004
Publication #:
US20060112158
Pub Dt:
05/25/2006
Title:
METHOD OF ESTIMATING A TOTAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN WITH STOCHASTICALLY WEIGHTED CONSERVATISM
4
Patent #:
7434180
Issue Dt:
10/07/2008
Application #:
10995777
Filing Dt:
11/23/2004
Publication #:
US20060112376
Pub Dt:
05/25/2006
Title:
VIRTUAL DATA REPRESENTATION THROUGH SELECTIVE BIDIRECTIONAL TRANSLATION
5
Patent #:
7305634
Issue Dt:
12/04/2007
Application #:
10996074
Filing Dt:
11/23/2004
Publication #:
US20060109462
Pub Dt:
05/25/2006
Title:
METHOD TO SELECTIVELY IDENTIFY AT RISK DIE BASED ON LOCATION WITHIN THE RETICLE
6
Patent #:
7315993
Issue Dt:
01/01/2008
Application #:
10999468
Filing Dt:
11/30/2004
Publication #:
US20060117281
Pub Dt:
06/01/2006
Title:
VERIFICATION OF RRAM TILING NETLIST
7
Patent #:
7216278
Issue Dt:
05/08/2007
Application #:
10999493
Filing Dt:
11/30/2004
Publication #:
US20060156088
Pub Dt:
07/13/2006
Title:
METHOD AND BIST ARCHITECTURE FOR FAST MEMORY TESTING IN PLATFORM-BASED INTEGRATED CIRCUIT
8
Patent #:
7200826
Issue Dt:
04/03/2007
Application #:
11000104
Filing Dt:
11/30/2004
Publication #:
US20060117284
Pub Dt:
06/01/2006
Title:
RRAM MEMORY TIMING LEARNING TOOL
9
Patent #:
7493577
Issue Dt:
02/17/2009
Application #:
11002576
Filing Dt:
12/01/2004
Publication #:
US20060117292
Pub Dt:
06/01/2006
Title:
AUTOMATIC RECOGNITION OF GEOMETRIC POINTS IN A TARGET IC DESIGN FOR OPC MASK QUALITY CALCULATION
10
Patent #:
7246336
Issue Dt:
07/17/2007
Application #:
11004309
Filing Dt:
12/03/2004
Publication #:
US20060123369
Pub Dt:
06/08/2006
Title:
RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
11
Patent #:
7424690
Issue Dt:
09/09/2008
Application #:
11005690
Filing Dt:
12/07/2004
Publication #:
US20060123377
Pub Dt:
06/08/2006
Title:
INTERCONNECT INTEGRITY VERIFICATION
12
Patent #:
7373626
Issue Dt:
05/13/2008
Application #:
11006349
Filing Dt:
12/06/2004
Publication #:
US20060123281
Pub Dt:
06/08/2006
Title:
METHOD AND TIMING HARNESS FOR SYSTEM LEVEL STATIC TIMING ANALYSIS
13
Patent #:
7246337
Issue Dt:
07/17/2007
Application #:
11007039
Filing Dt:
12/08/2004
Publication #:
US20060123373
Pub Dt:
06/08/2006
Title:
DENSITY DRIVEN LAYOUT FOR RRAM CONFIGURATION MODULE
14
Patent #:
7363608
Issue Dt:
04/22/2008
Application #:
11008854
Filing Dt:
12/09/2004
Publication #:
US20060125485
Pub Dt:
06/15/2006
Title:
ACCELERATING PCB DEVELOPMENT AND DEBUG IN ADVANCE OF PLATFORM ASIC PROTOTYPE SAMPLES
15
Patent #:
7334206
Issue Dt:
02/19/2008
Application #:
11010745
Filing Dt:
12/13/2004
Publication #:
US20060129962
Pub Dt:
06/15/2006
Title:
CELL BUILDER FOR DIFFERENT LAYER STACKS
16
Patent #:
7376260
Issue Dt:
05/20/2008
Application #:
11011384
Filing Dt:
12/14/2004
Publication #:
US20050100802
Pub Dt:
05/12/2005
Title:
METHOD FOR POST-OPC MULTI LAYER OVERLAY QUALITY INSPECTION
17
Patent #:
7260814
Issue Dt:
08/21/2007
Application #:
11012618
Filing Dt:
12/14/2004
Publication #:
US20060129966
Pub Dt:
06/15/2006
Title:
OPC EDGE CORRECTION BASED ON A SMOOTHED MASK DESIGN
18
Patent #:
7197735
Issue Dt:
03/27/2007
Application #:
11012741
Filing Dt:
12/15/2004
Publication #:
US20060129963
Pub Dt:
06/15/2006
Title:
FLOORPLAN VISUALIZATION METHOD USING GATE COUNT AND GATE DENSITY ESTIMATIONS
19
Patent #:
7210083
Issue Dt:
04/24/2007
Application #:
11013641
Filing Dt:
12/16/2004
Publication #:
US20060156128
Pub Dt:
07/13/2006
Title:
SYSTEM AND METHOD FOR IMPLEMENTING POSTPONED QUASI-MASKING TEST OUTPUT COMPRESSION IN INTEGRATED CIRCUIT
20
Patent #:
7185298
Issue Dt:
02/27/2007
Application #:
11015114
Filing Dt:
12/17/2004
Publication #:
US20060136850
Pub Dt:
06/22/2006
Title:
METHOD OF PARASITIC EXTRACTION FROM A PREVIOUSLY CALCULATED CAPACITANCE SOLUTION
21
Patent #:
7231626
Issue Dt:
06/12/2007
Application #:
11015123
Filing Dt:
12/17/2004
Publication #:
US20060136855
Pub Dt:
06/22/2006
Title:
METHOD OF IMPLEMENTING AN ENGINEERING CHANGE ORDER IN AN INTEGRATED CIRCUIT DESIGN BY WINDOWS
22
Patent #:
7290194
Issue Dt:
10/30/2007
Application #:
11016192
Filing Dt:
12/17/2004
Publication #:
US20060156142
Pub Dt:
07/13/2006
Title:
SYSTEM FOR PERFORMING AUTOMATIC TEST PIN ASSIGNMENT FOR A PROGRAMMABLE DEVICE
23
Patent #:
7398492
Issue Dt:
07/08/2008
Application #:
11017015
Filing Dt:
12/20/2004
Publication #:
US20050273736
Pub Dt:
12/08/2005
Title:
RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
24
Patent #:
7404156
Issue Dt:
07/22/2008
Application #:
11017017
Filing Dt:
12/20/2004
Publication #:
US20050273737
Pub Dt:
12/08/2005
Title:
LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
25
Patent #:
7340697
Issue Dt:
03/04/2008
Application #:
11019885
Filing Dt:
12/22/2004
Publication #:
US20060136860
Pub Dt:
06/22/2006
Title:
INTEGRATED COMPUTER-AIDED CIRCUIT DESIGN KIT FACILITATING VERIFICATION OF DESIGNS ACROSS DIFFERENT PROCESS TECHNOLOGIES
26
Patent #:
7290224
Issue Dt:
10/30/2007
Application #:
11027266
Filing Dt:
12/31/2004
Publication #:
US20050273738
Pub Dt:
12/08/2005
Title:
GUIDED CAPTURE, CREATION, AND SEAMLESS INTEGRATION WITH SCALABLE COMPLEXITY OF A CLOCK SPECIFICATION INTO A DESIGN FLOW OF AN INTEGRATED CIRCUIT
27
Patent #:
7181713
Issue Dt:
02/20/2007
Application #:
11028403
Filing Dt:
01/03/2005
Publication #:
US20050114811
Pub Dt:
05/26/2005
Title:
STATIC TIMING AND RISK ANALYSIS TOOL
28
Patent #:
7234122
Issue Dt:
06/19/2007
Application #:
11032720
Filing Dt:
01/10/2005
Publication #:
US20050235235
Pub Dt:
10/20/2005
Title:
THREE-DIMENSIONAL INTERCONNECT RESISTANCE EXTRACTION USING VARIATIONAL METHOD
29
Patent #:
7207021
Issue Dt:
04/17/2007
Application #:
11036822
Filing Dt:
01/14/2005
Publication #:
US20060190853
Pub Dt:
08/24/2006
Title:
METHOD FOR ESTIMATING A FREQUENCY-BASED RAMPTIME LIMIT
30
Patent #:
7299435
Issue Dt:
11/20/2007
Application #:
11037306
Filing Dt:
01/18/2005
Publication #:
US20060190879
Pub Dt:
08/24/2006
Title:
FREQUENCY DEPENDENT TIMING MARGIN
31
Patent #:
7243324
Issue Dt:
07/10/2007
Application #:
11041489
Filing Dt:
01/24/2005
Publication #:
US20060190901
Pub Dt:
08/24/2006
Title:
METHOD OF BUFFER INSERTION TO ACHIEVE PIN SPECIFIC DELAYS
32
Patent #:
7057261
Issue Dt:
06/06/2006
Application #:
11053505
Filing Dt:
02/08/2005
Publication #:
US20050147913
Pub Dt:
07/07/2005
Title:
MIXED LVR AND HVR RETICLE SET DESIGN FOR THE PROCESSING OF GATE ARRAYS, EMBEDDED ARRAYS AND RAPID CHIP PRODUCTS
33
Patent #:
7028274
Issue Dt:
04/11/2006
Application #:
11054460
Filing Dt:
02/09/2005
Title:
RRAM BACKEND FLOW
34
Patent #:
NONE
Issue Dt:
Application #:
11054879
Filing Dt:
02/10/2005
Publication #:
US20050149884
Pub Dt:
07/07/2005
Title:
System and method for coevolutionary circuit design
35
Patent #:
7328423
Issue Dt:
02/05/2008
Application #:
11055752
Filing Dt:
02/10/2005
Publication #:
US20050149302
Pub Dt:
07/07/2005
Title:
METHOD FOR EVALUATING LOGIC FUNCTIONS BY LOGIC CIRCUITS HAVING OPTIMIZED NUMBER OF AND/OR SWITCHES
36
Patent #:
7494752
Issue Dt:
02/24/2009
Application #:
11056838
Filing Dt:
02/11/2005
Publication #:
US20060183039
Pub Dt:
08/17/2006
Title:
METHOD AND SYSTEMS FOR UTILIZING SIMPLIFIED RESIST PROCESS MODELS TO PERFORM OPTICAL AND PROCESS CORRECTIONS
37
Patent #:
7202656
Issue Dt:
04/10/2007
Application #:
11061292
Filing Dt:
02/18/2005
Title:
METHODS AND STRUCTURE FOR IMPROVED HIGH-SPEED TDF TESTING USING ON-CHIP PLL
38
Patent #:
7228516
Issue Dt:
06/05/2007
Application #:
11061581
Filing Dt:
02/18/2005
Publication #:
US20060190859
Pub Dt:
08/24/2006
Title:
NEGATIVE BIAS TEMPERATURE INSTABILITY MODELING
39
Patent #:
7331031
Issue Dt:
02/12/2008
Application #:
11071623
Filing Dt:
03/03/2005
Publication #:
US20060200788
Pub Dt:
09/07/2006
Title:
METHOD FOR DESCRIBING AND DEPLOYING DESIGN PLATFORM SETS
40
Patent #:
7299431
Issue Dt:
11/20/2007
Application #:
11074173
Filing Dt:
03/07/2005
Publication #:
US20060200787
Pub Dt:
09/07/2006
Title:
METHOD FOR TRACING PATHS WITHIN A CIRCUIT
41
Patent #:
7023530
Issue Dt:
04/04/2006
Application #:
11075239
Filing Dt:
03/07/2005
Title:
DUAL SOURCE LITHOGRAPHY FOR DIRECT WRITE APPLICATION
42
Patent #:
7376918
Issue Dt:
05/20/2008
Application #:
11079017
Filing Dt:
03/11/2005
Publication #:
US20060206843
Pub Dt:
09/14/2006
Title:
PROBABILISTIC NOISE ANALYSIS
43
Patent #:
7620924
Issue Dt:
11/17/2009
Application #:
11079439
Filing Dt:
03/14/2005
Publication #:
US20060236292
Pub Dt:
10/19/2006
Title:
BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME
44
Patent #:
7263678
Issue Dt:
08/28/2007
Application #:
11079998
Filing Dt:
03/15/2005
Publication #:
US20060218515
Pub Dt:
09/28/2006
Title:
METHOD OF IDENTIFYING FLOORPLAN PROBLEMS IN AN INTEGRATED CIRCUIT LAYOUT
45
Patent #:
7523426
Issue Dt:
04/21/2009
Application #:
11092406
Filing Dt:
03/29/2005
Publication #:
US20060230373
Pub Dt:
10/12/2006
Title:
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
46
Patent #:
7206983
Issue Dt:
04/17/2007
Application #:
11097936
Filing Dt:
03/31/2005
Publication #:
US20060236176
Pub Dt:
10/19/2006
Title:
SEGMENTED ADDRESSABLE SCAN ARCHITECTURE AND METHOD FOR IMPLEMENTING SCAN-BASED TESTING OF INTEGRATED CIRCUITS
47
Patent #:
7313775
Issue Dt:
12/25/2007
Application #:
11099772
Filing Dt:
04/06/2005
Publication #:
US20060230375
Pub Dt:
10/12/2006
Title:
INTEGRATED CIRCUIT WITH RELOCATABLE PROCESSOR HARDMAC
48
Patent #:
7398489
Issue Dt:
07/08/2008
Application #:
11100986
Filing Dt:
04/06/2005
Publication #:
US20060226530
Pub Dt:
10/12/2006
Title:
ADVANCED STANDARD CELL POWER CONNECTION
49
Patent #:
7139991
Issue Dt:
11/21/2006
Application #:
11107585
Filing Dt:
04/14/2005
Publication #:
US20050204235
Pub Dt:
09/15/2005
Title:
AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN-TEST (BIST) MODULES IN ASIC MEMORY DESIGNS
50
Patent #:
7373629
Issue Dt:
05/13/2008
Application #:
11113615
Filing Dt:
04/25/2005
Publication #:
US20060239052
Pub Dt:
10/26/2006
Title:
DISTRIBUTED RELOCATABLE VOLTAGE REGULATOR
51
Patent #:
7543261
Issue Dt:
06/02/2009
Application #:
11115798
Filing Dt:
04/27/2005
Publication #:
US20060248491
Pub Dt:
11/02/2006
Title:
I /O PLANNING WITH LOCK AND INSERTION FEATURES
52
Patent #:
7240264
Issue Dt:
07/03/2007
Application #:
11116616
Filing Dt:
04/28/2005
Publication #:
US20060248418
Pub Dt:
11/02/2006
Title:
SCAN TEST EXPANSION MODULE
53
Patent #:
7292063
Issue Dt:
11/06/2007
Application #:
11120067
Filing Dt:
05/02/2005
Publication #:
US20060279326
Pub Dt:
12/14/2006
Title:
METHOD OF INTERCONNECT FOR MULTI-SLOT METAL-MASK PROGRAMMABLE RELOCATABLE FUNCTION PLACED IN AN I/O REGION
54
Patent #:
7305646
Issue Dt:
12/04/2007
Application #:
11125307
Filing Dt:
05/09/2005
Publication #:
US20060253825
Pub Dt:
11/09/2006
Title:
RELOCATABLE MIXED-SIGNAL FUNCTIONS
55
Patent #:
7272802
Issue Dt:
09/18/2007
Application #:
11126880
Filing Dt:
05/11/2005
Publication #:
US20060259892
Pub Dt:
11/16/2006
Title:
R-CELLS CONTAINING CDM CLAMPS
56
Patent #:
7373622
Issue Dt:
05/13/2008
Application #:
11129547
Filing Dt:
05/13/2005
Publication #:
US20060259841
Pub Dt:
11/16/2006
Title:
RELOCATABLE BUILT-IN SELF TEST (BIST) ELEMENTS FOR RELOCATABLE MIXED-SIGNAL ELEMENTS
57
Patent #:
7328386
Issue Dt:
02/05/2008
Application #:
11131990
Filing Dt:
05/18/2005
Publication #:
US20060282728
Pub Dt:
12/14/2006
Title:
METHODS FOR USING CHECKSUMS IN X-TOLERANT TEST RESPONSE COMPACTION IN SCAN-BASED TESTING OF INTEGRATED CIRCUITS
58
Patent #:
7478354
Issue Dt:
01/13/2009
Application #:
11133815
Filing Dt:
05/20/2005
Publication #:
US20060263933
Pub Dt:
11/23/2006
Title:
USE OF CONFIGURABLE MIXED-SIGNAL BUILDING BLOCK FUNCTIONS TO ACCOMPLISH CUSTOM FUNCTIONS
59
Patent #:
7360178
Issue Dt:
04/15/2008
Application #:
11136180
Filing Dt:
05/24/2005
Publication #:
US20060271901
Pub Dt:
11/30/2006
Title:
MIXED-SIGNAL FUNCTIONS USING R-CELLS
60
Patent #:
7340700
Issue Dt:
03/04/2008
Application #:
11140392
Filing Dt:
05/27/2005
Publication #:
US20060271904
Pub Dt:
11/30/2006
Title:
METHOD FOR ABSTRACTION OF MANUFACTURING TEST ACCESS AND CONTROL PORTS TO SUPPORT AUTOMATED RTL MANUFACTURING TEST INSERTION FLOW FOR REUSABLE MODULES
61
Patent #:
7380229
Issue Dt:
05/27/2008
Application #:
11151043
Filing Dt:
06/13/2005
Publication #:
US20060282808
Pub Dt:
12/14/2006
Title:
AUTOMATIC GENERATION OF CORRECT MINIMAL CLOCKING CONSTRAINTS FOR A SEMICONDUCTOR PRODUCT
62
Patent #:
7430725
Issue Dt:
09/30/2008
Application #:
11156319
Filing Dt:
06/18/2005
Publication #:
US20050240892
Pub Dt:
10/27/2005
Title:
SUITE OF TOOLS TO DESIGN INTEGRATED CIRCUITS
63
Patent #:
7178121
Issue Dt:
02/13/2007
Application #:
11165778
Filing Dt:
06/24/2005
Publication #:
US20060294482
Pub Dt:
12/28/2006
Title:
METHOD AND COMPUTER PROGRAM FOR ESTIMATING SPEED-UP AND SLOW-DOWN NET DELAYS FOR AN INTEGRATED CIRCUIT DESIGN
64
Patent #:
7451426
Issue Dt:
11/11/2008
Application #:
11176514
Filing Dt:
07/07/2005
Publication #:
US20070011642
Pub Dt:
01/11/2007
Title:
APPLICATION SPECIFIC CONFIGURABLE LOGIC IP
65
Patent #:
7827509
Issue Dt:
11/02/2010
Application #:
11182615
Filing Dt:
07/15/2005
Publication #:
US20070013695
Pub Dt:
01/18/2007
Title:
DIGITALLY OBTAINING CONTOURS OF FABRICATED POLYGONS
66
Patent #:
7401318
Issue Dt:
07/15/2008
Application #:
11184401
Filing Dt:
07/19/2005
Publication #:
US20050268272
Pub Dt:
12/01/2005
Title:
METHOD AND APPARATUS FOR OPTIMIZING FRAGMENTATION OF BOUNDARIES FOR OPTICAL PROXIMITY CORRECTION (OPC) PURPOSES
67
Patent #:
7444275
Issue Dt:
10/28/2008
Application #:
11187455
Filing Dt:
07/22/2005
Publication #:
US20070022392
Pub Dt:
01/25/2007
Title:
MULTI-VARIABLE POLYNOMIAL MODELING TECHNIQUES FOR USE IN INTEGRATED CIRCUIT DESIGN
68
Patent #:
7260801
Issue Dt:
08/21/2007
Application #:
11192526
Filing Dt:
07/29/2005
Publication #:
US20070028199
Pub Dt:
02/01/2007
Title:
DELAY COMPUTATION SPEED UP AND INCREMENTALITY
69
Patent #:
7464345
Issue Dt:
12/09/2008
Application #:
11194299
Filing Dt:
08/01/2005
Publication #:
US20070028196
Pub Dt:
02/01/2007
Title:
RESOURCE ESTIMATION FOR DESIGN PLANNING
70
Patent #:
7480874
Issue Dt:
01/20/2009
Application #:
11198930
Filing Dt:
08/05/2005
Publication #:
US20070033555
Pub Dt:
02/08/2007
Title:
RELIABILITY ANALYSIS OF INTEGRATED CIRCUITS
71
Patent #:
7299446
Issue Dt:
11/20/2007
Application #:
11204669
Filing Dt:
08/16/2005
Publication #:
US20070044058
Pub Dt:
02/22/2007
Title:
ENABLING EFFICIENT DESIGN REUSE IN PLATFORM ASICS
72
Patent #:
7469398
Issue Dt:
12/23/2008
Application #:
11204670
Filing Dt:
08/16/2005
Publication #:
US20070044059
Pub Dt:
02/22/2007
Title:
IP PLACEMENT VALIDATION
73
Patent #:
7512918
Issue Dt:
03/31/2009
Application #:
11205365
Filing Dt:
08/17/2005
Publication #:
US20070044053
Pub Dt:
02/22/2007
Title:
MULTIMODE DELAY ANALYSIS FOR SIMPLIFYING INTEGRATED CIRCUIT DESIGN TIMING MODELS
74
Patent #:
7325215
Issue Dt:
01/29/2008
Application #:
11216918
Filing Dt:
08/31/2005
Publication #:
US20070050745
Pub Dt:
03/01/2007
Title:
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
75
Patent #:
7340706
Issue Dt:
03/04/2008
Application #:
11239977
Filing Dt:
09/30/2005
Publication #:
US20070079277
Pub Dt:
04/05/2007
Title:
METHOD AND SYSTEM FOR ANALYZING THE QUALITY OF AN OPC MASK
76
Patent #:
7406671
Issue Dt:
07/29/2008
Application #:
11243839
Filing Dt:
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Pub Dt:
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Title:
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Filing Dt:
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Pub Dt:
04/05/2007
Title:
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Filing Dt:
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Pub Dt:
04/05/2007
Title:
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Issue Dt:
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Filing Dt:
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Publication #:
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Pub Dt:
04/12/2007
Title:
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Issue Dt:
10/21/2008
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Filing Dt:
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Pub Dt:
04/12/2007
Title:
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Issue Dt:
06/15/2010
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Filing Dt:
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Publication #:
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Pub Dt:
04/26/2007
Title:
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Issue Dt:
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Application #:
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Filing Dt:
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Publication #:
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Pub Dt:
04/26/2007
Title:
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Issue Dt:
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Application #:
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Filing Dt:
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Publication #:
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Pub Dt:
04/26/2007
Title:
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Issue Dt:
02/17/2009
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Filing Dt:
10/24/2005
Publication #:
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Pub Dt:
04/26/2007
Title:
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Issue Dt:
07/15/2008
Application #:
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Filing Dt:
10/26/2005
Publication #:
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Pub Dt:
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Title:
METHOD AND APPARATUS FOR CONTROLLING CONGESTION DURING INTEGRATED CIRCUIT DESIGN RESYNTHESIS
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Issue Dt:
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Filing Dt:
10/27/2005
Publication #:
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Pub Dt:
07/19/2007
Title:
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Issue Dt:
12/16/2008
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Filing Dt:
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Publication #:
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Pub Dt:
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Title:
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Issue Dt:
01/29/2008
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Filing Dt:
11/09/2005
Publication #:
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Pub Dt:
05/10/2007
Title:
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7424687
Issue Dt:
09/09/2008
Application #:
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Filing Dt:
11/16/2005
Publication #:
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Pub Dt:
05/17/2007
Title:
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Issue Dt:
06/17/2008
Application #:
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Filing Dt:
11/16/2005
Publication #:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Issue Dt:
02/24/2009
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Filing Dt:
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Publication #:
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Pub Dt:
05/31/2007
Title:
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07/29/2008
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Filing Dt:
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Pub Dt:
06/07/2007
Title:
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Filing Dt:
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Pub Dt:
06/14/2007
Title:
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07/29/2008
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12/16/2005
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Pub Dt:
06/21/2007
Title:
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08/19/2008
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Pub Dt:
06/21/2007
Title:
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7546568
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06/09/2009
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Filing Dt:
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Pub Dt:
06/21/2007
Title:
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Publication #:
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Pub Dt:
06/21/2007
Title:
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7480878
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12/29/2005
Publication #:
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Pub Dt:
07/05/2007
Title:
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7434198
Issue Dt:
10/07/2008
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11323401
Filing Dt:
12/29/2005
Publication #:
US20070157152
Pub Dt:
07/05/2007
Title:
METHOD AND COMPUTER PROGRAM PRODUCT FOR DETECTING POTENTIAL FAILURES IN AN INTEGRATED CIRCUIT DESIGN AFTER OPTICAL PROXIMITY CORRECTION
Assignors
1
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Exec Dt:
12/08/2017
2
BROADCOM CORPORATION
Exec Dt:
12/08/2017
Assignee
1
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE.
SUITE 1600
CHICAGO, ILLINOIS 60611
Correspondence name and address
CHAD S. HILYARD
401 N. MICHIGAN AVE.
SUITE 1600
CHICAGO, IL 60611

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