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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11323468
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Filing Dt:
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12/30/2005
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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YIELD-LIMITING DESIGN-RULES-COMPLIANT PATTERN LIBRARY GENERATION AND LAYOUT INSPECTION
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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11324082
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Filing Dt:
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12/29/2005
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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SYSTEM FOR AVOIDING FALSE PATH PESSIMISM IN ESTIMATING NET DELAY FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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11324084
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Filing Dt:
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12/29/2005
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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METHOD AND APPARATUS FOR DETECTING DEFECTS IN INTEGRATED CIRCUIT DIE FROM STIMULATION OF STATISTICAL OUTLIER SIGNATURES
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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11324105
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Filing Dt:
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12/29/2005
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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METHOD AND END CELL LIBRARY FOR AVOIDING SUBSTRATE NOISE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/17/2010
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Application #:
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11324119
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Filing Dt:
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12/30/2005
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Title:
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SOCKETLESS/BOARDLESS TEST INTERPOSER CARD
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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11349356
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Filing Dt:
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02/07/2006
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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CDM ESD EVENT PROTECTION IN APPLICATION CIRCUITS
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11349358
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Filing Dt:
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02/07/2006
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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CDM ESD EVENT SIMULATION AND REMEDIATION THEREOF IN APPLICATION CIRCUITS
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11351091
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Filing Dt:
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02/09/2006
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Publication #:
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Pub Dt:
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08/09/2007
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Title:
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GENERATION OF AN EXTRACTED TIMING MODEL FILE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11364142
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Filing Dt:
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02/27/2006
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Publication #:
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Pub Dt:
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08/30/2007
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Title:
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Device for analyzing log files generated by process automation tools
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11376600
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Filing Dt:
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03/15/2006
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Publication #:
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Pub Dt:
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09/20/2007
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Title:
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METHODS AND APPARATUS FOR REDUCING TIMING SKEW
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Patent #:
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Issue Dt:
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08/18/2009
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Application #:
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11376781
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Filing Dt:
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03/15/2006
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Publication #:
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Pub Dt:
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09/20/2007
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Title:
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VERIFICATION OF AN EXTRACTED TIMING MODEL FILE
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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11377778
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Filing Dt:
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03/16/2006
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Publication #:
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Pub Dt:
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04/26/2007
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Title:
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METHODS FOR MEASUREMENT AND PREDICTION OF HOLD-TIME AND EXCEEDING HOLD TIME LIMITS DUE TO CELLS WITH TIED INPUT PINS
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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11402146
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Filing Dt:
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04/11/2006
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Publication #:
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Pub Dt:
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08/24/2006
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Title:
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OPTIMIZING IC CLOCK STRUCTURES BY MINIMIZING CLOCK UNCERTAINTY
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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11413236
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Filing Dt:
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04/28/2006
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Publication #:
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Pub Dt:
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11/01/2007
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Title:
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METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
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Patent #:
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Issue Dt:
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05/26/2009
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Application #:
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11421722
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Filing Dt:
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06/01/2006
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Publication #:
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Pub Dt:
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11/09/2006
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Title:
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REDUCING A PARASITIC GRAPH IN MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEMS
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11438644
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Filing Dt:
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05/22/2006
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Publication #:
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Pub Dt:
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11/22/2007
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Title:
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METHOD AND APPARATUS FOR AUTOMATIC CREATION AND PLACEMENT OF A FLOOR-PLAN REGION
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11460680
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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12/14/2006
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Title:
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ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CONTROL STRUCTURES IN RTL CODE
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Patent #:
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Issue Dt:
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01/20/2009
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Application #:
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11465662
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Filing Dt:
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08/18/2006
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Publication #:
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Pub Dt:
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02/21/2008
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Title:
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METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY DE-RATING AND CLOCK CONSERVATISM REDUCTION
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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11469028
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Filing Dt:
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08/31/2006
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Publication #:
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Pub Dt:
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03/06/2008
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Title:
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INPUT/OUTPUT BUFFER INFORMATION SPECIFICATION (IBIS) MODEL GENERATION FOR MULTI-CHIP MODULES (MCM) AND SIMILAR DEVICES
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Patent #:
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Issue Dt:
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02/10/2009
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Application #:
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11478044
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Filing Dt:
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06/29/2006
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Publication #:
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Pub Dt:
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01/03/2008
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Title:
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AUTOMATIC GENERATION OF TIMING CONSTRAINTS FOR THE VALIDATION/SIGNOFF OF TEST STRUCTURES
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Patent #:
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Issue Dt:
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09/15/2009
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Application #:
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11509370
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Filing Dt:
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08/24/2006
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Publication #:
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Pub Dt:
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02/28/2008
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Title:
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METHOD AND APPARATUS FOR FIXING BEST CASE HOLD TIME VIOLATIONS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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11538187
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Filing Dt:
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10/03/2006
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Publication #:
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Pub Dt:
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06/26/2008
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Title:
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DEVICE FOR AVOIDING TIMING VIOLATIONS RESULTING FROM PROCESS DEFECTS IN A BACKFILLED METAL LAYER OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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11550448
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Filing Dt:
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10/18/2006
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Publication #:
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Pub Dt:
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04/26/2007
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Title:
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METHODS AND APPARATUS FOR MAKING PLACEMENT SENSITIVE LOGIC MODIFICATIONS
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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11551573
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Filing Dt:
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10/20/2006
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Publication #:
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Pub Dt:
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03/01/2007
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Title:
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METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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11567986
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Filing Dt:
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12/07/2006
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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CELL MODELING FOR INTEGRATED CIRCUIT DESIGN WITH CHARACTERIZATION OF UPSTREAM DRIVER STRENGTH
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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11610825
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Filing Dt:
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12/14/2006
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Publication #:
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Pub Dt:
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06/19/2008
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Title:
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ELECTROSTATIC DISCHARGE DEVICE VERIFICATION IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/09/2009
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Application #:
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11634683
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Filing Dt:
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12/06/2006
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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OPTIMIZATION OF FLIP FLOP INITIALIZATION STRUCTURES WITH RESPECT TO DESIGN SIZE AND DESIGN CLOSURE EFFORT FROM RTL TO NETLIST
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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11682914
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Filing Dt:
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03/07/2007
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Publication #:
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Pub Dt:
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07/12/2007
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Title:
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METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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11693081
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Filing Dt:
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03/29/2007
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Publication #:
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Pub Dt:
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10/02/2008
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Title:
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MODIFYING INTEGRATED CIRCUIT DESIGNS TO ACHIEVE MULTIPLE OPERATING FREQUENCY TARGETS
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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11706943
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Filing Dt:
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02/13/2007
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Publication #:
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Pub Dt:
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11/29/2007
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Title:
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SEQUENTIAL TESTER FOR LONGEST PREFIX SEARCH ENGINES
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Patent #:
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Issue Dt:
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03/09/2010
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Application #:
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11724143
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Filing Dt:
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03/14/2007
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Publication #:
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Pub Dt:
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09/18/2008
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Title:
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TRACE OPTIMIZATION IN FLATTENED NETLIST BY STORING AND RETRIEVING INTERMEDIATE RESULTS
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Patent #:
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Issue Dt:
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02/16/2010
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Application #:
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11724663
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Filing Dt:
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03/15/2007
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Publication #:
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Pub Dt:
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07/12/2007
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Title:
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CUSTOMIZABLE DEVELOPMENT AND DEMONSTRATION PLATFORM FOR STRUCTURED ASICS
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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11728366
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Filing Dt:
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03/26/2007
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Publication #:
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Pub Dt:
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10/02/2008
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Title:
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GENERIC METHODOLOGY TO SUPPORT CHIP LEVEL INTEGRATION OF IP CORE INSTANCE CONSTRAINTS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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11732092
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Filing Dt:
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04/02/2007
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Publication #:
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Pub Dt:
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10/02/2008
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Title:
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CELL LIBRARY MANAGEMENT FOR POWER OPTIMIZATION
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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11749904
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Filing Dt:
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05/17/2007
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Publication #:
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Pub Dt:
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11/22/2007
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Title:
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COMMAND-LANGUAGE-BASED FUNCTIONAL ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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11757200
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Filing Dt:
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06/01/2007
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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DENSITY DRIVEN LAYOUT FOR RRAM CONFIGURATION MODULE
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Patent #:
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Issue Dt:
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07/28/2009
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Application #:
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11757229
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Filing Dt:
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06/01/2007
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Publication #:
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Pub Dt:
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10/04/2007
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Title:
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RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11758975
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Filing Dt:
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06/06/2007
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Publication #:
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Pub Dt:
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10/04/2007
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Title:
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DIGITAL GAUSSIAN NOISE SIMULATOR
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Patent #:
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Issue Dt:
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12/07/2010
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Application #:
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11765691
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Filing Dt:
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06/20/2007
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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EFFICIENT CELL SWAPPING SYSTEM FOR LEAKAGE POWER REDUCTION IN A MULTI-THRESHOLD VOLTAGE PROCESS
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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11775956
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Filing Dt:
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07/11/2007
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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GENERALIZED BIST FOR MULTIPORT MEMORIES
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Patent #:
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Issue Dt:
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01/20/2009
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Application #:
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11832516
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Filing Dt:
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08/01/2007
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Publication #:
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Pub Dt:
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01/24/2008
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Title:
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NQL - NETLIST QUERY LANGUAGE
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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11849391
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Filing Dt:
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09/04/2007
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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STATISTICAL DESIGN CLOSURE
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11946243
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Filing Dt:
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11/28/2007
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Publication #:
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Pub Dt:
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03/27/2008
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Title:
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TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
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Patent #:
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Issue Dt:
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07/05/2011
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11949187
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12/03/2007
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Publication #:
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Pub Dt:
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06/04/2009
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Title:
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STAGED SCENARIO GENERATION
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Patent #:
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Issue Dt:
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08/09/2011
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12015925
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01/17/2008
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Publication #:
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Pub Dt:
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07/23/2009
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Title:
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SIGNAL DELAY SKEW REDUCTION SYSTEM
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Issue Dt:
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02/09/2010
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12046169
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Filing Dt:
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03/11/2008
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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PROBABILISTIC NOISE ANALYSIS
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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12072478
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02/26/2008
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Publication #:
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Pub Dt:
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08/27/2009
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Title:
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Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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12103825
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Filing Dt:
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04/16/2008
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Publication #:
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Pub Dt:
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10/22/2009
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Title:
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ON CHIP LOCAL MOSFET SIZING
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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12109501
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Filing Dt:
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04/25/2008
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Publication #:
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Pub Dt:
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10/29/2009
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Title:
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UNIFIED LAYER STACK ARCHITECTURE
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Patent #:
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Issue Dt:
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04/09/2013
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Application #:
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12111836
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Filing Dt:
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04/29/2008
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Publication #:
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Pub Dt:
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10/29/2009
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Title:
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OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
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Patent #:
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Issue Dt:
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11/30/2010
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Application #:
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12117381
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Filing Dt:
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05/08/2008
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Publication #:
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Pub Dt:
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11/12/2009
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Title:
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OPTIMIZING TEST CODE GENERATION FOR VERIFICATION ENVIRONMENT
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12117760
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Filing Dt:
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05/09/2008
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Publication #:
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Pub Dt:
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09/04/2008
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Title:
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METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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08/28/2012
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Application #:
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12120894
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
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11/19/2009
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Title:
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CHARACTERIZING PERFORMANCE OF AN ELECTRONIC SYSTEM
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Patent #:
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