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Patent Assignment Details

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Reel/Frame:	045007/0891			Pages:	4
		Recorded:	02/22/2018
Attorney Dkt #:	510200US
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	7135724	Issue Dt:	11/14/2006	Application #:	10711637	Filing Dt:	09/29/2004
Publication #:	US20060065914	Pub Dt:	03/30/2006
Title:	STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER

Patent #:	8483227	Issue Dt:	07/09/2013	Application #:	10718302	Filing Dt:	11/20/2003
Publication #:	US20050111354	Pub Dt:	05/26/2005
Title:	CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS

Patent #:	7055077	Issue Dt:	05/30/2006	Application #:	10744917	Filing Dt:	12/23/2003
Publication #:	US20050138509	Pub Dt:	06/23/2005
Title:	SYSTEMS AND METHODS FOR CIRCUIT TESTING

Patent #:	7030658	Issue Dt:	04/18/2006	Application #:	10764179	Filing Dt:	01/23/2004
Publication #:	US20050162186	Pub Dt:	07/28/2005
Title:	SYSTEMS AND METHODS FOR OPERATING LOGIC CIRCUITS

Patent #:	7053668	Issue Dt:	05/30/2006	Application #:	10852863	Filing Dt:	05/25/2004
Publication #:	US20050264324	Pub Dt:	12/01/2005
Title:	SOI SENSE AMPLIFIER WITH CROSS-COUPLED BODY TERMINAL

Patent #:	7046045	Issue Dt:	05/16/2006	Application #:	10852889	Filing Dt:	05/25/2004
Publication #:	US20050264323	Pub Dt:	12/01/2005
Title:	SOI SENSE AMPLIFIER WITH CROSS-COUPLED BIT LINE STRUCTURE

Patent #:	7085147	Issue Dt:	08/01/2006	Application #:	11003084	Filing Dt:	12/03/2004
Publication #:	US20060120127	Pub Dt:	06/08/2006
Title:	SYSTEMS AND METHODS FOR PREVENTING MALFUNCTION OF CONTENT ADDRESSABLE MEMORY RESULTING FROM CONCURRENT WRITE AND LOOKUP OPERATIONS

Patent #:	7218152	Issue Dt:	05/15/2007	Application #:	11033612	Filing Dt:	01/12/2005
Publication #:	US20060152247	Pub Dt:	07/13/2006
Title:	SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION ASSOCIATED WITH THE CAPACITANCE OF INACTIVE PORTIONS OF A MULTIPLEXER

Patent #:	7689776	Issue Dt:	03/30/2010	Application #:	11145844	Filing Dt:	06/06/2005
Publication #:	US20060277351	Pub Dt:	12/07/2006
Title:	METHOD AND SYSTEM FOR EFFICIENT CACHE LOCKING MECHANISM

Patent #:	7444600	Issue Dt:	10/28/2008	Application #:	11205421	Filing Dt:	08/17/2005
Publication #:	US20070044048	Pub Dt:	02/22/2007
Title:	SYSTEM AND METHOD FOR CIRCUIT NOISE ANALYSIS

Patent #:	7590774	Issue Dt:	09/15/2009	Application #:	11291735	Filing Dt:	12/01/2005
Publication #:	US20070162640	Pub Dt:	07/12/2007
Title:	METHOD AND SYSTEM FOR EFFICIENT CONTEXT SWAPPING

Patent #:	7484153	Issue Dt:	01/27/2009	Application #:	11295057	Filing Dt:	12/06/2005
Publication #:	US20070130489	Pub Dt:	06/07/2007
Title:	SYSTEMS AND METHODS FOR LBIST TESTING USING ISOLATABLE SCAN CHAINS

Patent #:	7645656	Issue Dt:	01/12/2010	Application #:	11463777	Filing Dt:	08/10/2006
Publication #:	US20060292779	Pub Dt:	12/28/2006
Title:	STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER

Patent #:	8145804	Issue Dt:	03/27/2012	Application #:	12563756	Filing Dt:	09/21/2009
Publication #:	US20110072170	Pub Dt:	03/24/2011
Title:	SYSTEMS AND METHODS FOR TRANSFERRING DATA TO MAINTAIN PREFERRED SLOT POSITIONS IN A BI-ENDIAN PROCESSOR

Assignor

Exec Dt:

02/16/2018

Assignee

1-1, SHIBAURA 1-CHOME

MINATO-KU

TOKYO, JAPAN

Correspondence name and address
	OBLON, ET AL.
	1940 DUKE STREET
	ALEXANDRIA, VA 22314

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