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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 1 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
05/05/1992
Application #:
07576182
Filing Dt:
08/30/1990
Title:
APPARATUS FOR ISOLATION OF FLUX MATERIALS IN "FLIP-CHIP" MANUFACTURING
2
Patent #:
Issue Dt:
06/23/1992
Application #:
07591646
Filing Dt:
10/02/1990
Title:
STRUCTURE FOR FILTERING CVD CHAMBER PROCESS GASES
3
Patent #:
Issue Dt:
01/19/1993
Application #:
07592014
Filing Dt:
10/02/1990
Title:
APPARATUS FOR CONDUCTING A REFRACTORY METAL DEPOSITION PROCESS
4
Patent #:
Issue Dt:
03/09/1999
Application #:
07707365
Filing Dt:
05/30/1991
Title:
METHOD FOR FORMING SELF ALIGNED POLYSILICON CONTACT
5
Patent #:
Issue Dt:
04/28/1998
Application #:
07719699
Filing Dt:
06/25/1991
Title:
DIELECTRIC FILM DEPOSITION METHOD AND APPARATUS
6
Patent #:
Issue Dt:
02/21/1995
Application #:
07739773
Filing Dt:
07/29/1991
Title:
TUNGSTEN DEPOSITION PROCESS FOR LOW CONTACT RESISTIVITY TO SILICON
7
Patent #:
Issue Dt:
12/01/1992
Application #:
07775009
Filing Dt:
10/11/1991
Title:
METHOD AND APPARATUS FOR ISOLATION OF FLUX MATERIALS IN FLIP-CHIP MANUFACTURING
8
Patent #:
Issue Dt:
04/20/1993
Application #:
07794780
Filing Dt:
11/18/1991
Title:
METHOD FOR PERFORMING IN-SITU ETCH OF A CVD CHAMBER
9
Patent #:
Issue Dt:
05/18/1993
Application #:
07809104
Filing Dt:
12/12/1991
Title:
APPARATUS FOR PERFORMING IN-SITU ETCH OF CVD CHAMBER
10
Patent #:
Issue Dt:
03/09/1999
Application #:
07815316
Filing Dt:
12/30/1991
Title:
SELF-ALIGNED CONTACT WINDOW
11
Patent #:
Issue Dt:
11/03/1998
Application #:
07828468
Filing Dt:
01/30/1992
Title:
POWER PLANE FOR SEMICONDUCTOR DEVICE
12
Patent #:
Issue Dt:
11/16/1993
Application #:
07834182
Filing Dt:
02/07/1992
Title:
PARTIALLY-MOLDED, PCB CHIP CARRIER PACKAGE
13
Patent #:
Issue Dt:
10/21/1997
Application #:
07866942
Filing Dt:
04/03/1992
Title:
FET WITH GATE SPACER
14
Patent #:
Issue Dt:
08/16/1994
Application #:
07911846
Filing Dt:
07/10/1992
Title:
METHOD AND APPARATUS FOR INTERIM, IN-SITU TESTING OF AN ELECTRONIC SYSTEM WITH AN INCHOATE ASIC
15
Patent #:
Issue Dt:
08/23/1994
Application #:
07916328
Filing Dt:
07/17/1992
Title:
METHOD OF INCREASING THE LAYOUT EFFICIENCY OF DIES ON A WAFER AND INCREASING THE RATIO OF I/O AREA TO ACTIVE AREA PER DIE
16
Patent #:
Issue Dt:
07/12/1994
Application #:
07933430
Filing Dt:
08/21/1992
Title:
SEMICONDUCTOR PACKAGING TECHNIQUE YIELDING INCREASED INNER LEAD COUNT FOR A GIVEN DIE-RECEIVING AREA
17
Patent #:
Issue Dt:
04/05/1994
Application #:
07935449
Filing Dt:
08/25/1992
Title:
TECHNIQUE OF INCREASING BOND PAD DENSITY ON A SEMICONDUCTOR DIE
18
Patent #:
Issue Dt:
05/13/1997
Application #:
07937643
Filing Dt:
08/31/1992
Title:
METHOD AND APPARATUS FOR INTERIM IN-SITU TESTING OF AN ELECTRONIC SYSTEM WITH AN INCHOATE ASIC
19
Patent #:
Issue Dt:
06/20/2000
Application #:
07940157
Filing Dt:
09/03/1992
Title:
METHOD FOR ASSEMBLING MULTICHIP MODULES
20
Patent #:
Issue Dt:
09/28/1993
Application #:
07947854
Filing Dt:
09/18/1992
Title:
COMPOSITE BOND PADS FOR SEMICONDUCTOR DEVICES
21
Patent #:
Issue Dt:
03/21/1995
Application #:
07975185
Filing Dt:
11/12/1992
Title:
MULTI-CHIP SEMICONDUCTOR ARRANGEMENTS USING FLIP CHIP DIES
22
Patent #:
Issue Dt:
08/23/1994
Application #:
07978483
Filing Dt:
11/18/1992
Title:
METHOD OF INCREASING THE LAYOUT EFFICIENCY OF DIES ON A WAFER, AND INCREASING THE RATIO OF I/O AREA TO ACTIVE AREA PER DIE
23
Patent #:
Issue Dt:
09/09/1997
Application #:
07980492
Filing Dt:
11/23/1992
Title:
FLEXIBLE DESIGN SYSTEM
24
Patent #:
Issue Dt:
04/05/1994
Application #:
07981096
Filing Dt:
11/24/1992
Title:
METHOD AND APPARATUS FOR ISOLATION OF FLUX MATERIALS IN FLIP-CHIP MANUFACTURING
25
Patent #:
Issue Dt:
02/08/1994
Application #:
07984206
Filing Dt:
11/30/1992
Title:
SEMICONDUCTOR BOND PADS
26
Patent #:
Issue Dt:
04/04/1995
Application #:
07995644
Filing Dt:
12/18/1992
Title:
SEMICONDUCTOR DIE HAVING A HIGH DENSITY ARRAY OF COMPOSITE BOND PADS
27
Patent #:
Issue Dt:
08/23/1994
Application #:
08051028
Filing Dt:
04/21/1993
Title:
IMAGE-SENSING DISPLAY PANELS WITH LCD DISPLAY PANEL AND PHOTOSENSING E ELEMENT ARRAY
28
Patent #:
Issue Dt:
12/12/2000
Application #:
08079310
Filing Dt:
06/17/1993
Title:
PROCESSES USING PHOTOSENSITIVE MATERIALS INCLUDING A NITRO BENZYL ESTER PHOTOACID GENERATOR
29
Patent #:
Issue Dt:
07/18/1995
Application #:
08079499
Filing Dt:
06/18/1993
Title:
PARTIALLY-MOLDED, PCB CHIP CARRIER PACKAGE FOR CERTAIN NON-SQUARE DIE SHAPES
30
Patent #:
Issue Dt:
04/02/1996
Application #:
08105547
Filing Dt:
08/12/1993
Title:
PROCESS FOR SOLDER BALL INTERCONNECTING A SEMICONDUCTOR DEVICE TO A SUBSTRATE USING A NOBLE METAL FOIL EMBEDDED INTERPOSER SUBSTRATE
31
Patent #:
Issue Dt:
09/13/1994
Application #:
08105838
Filing Dt:
08/12/1993
Title:
PREFORMED PLANAR STRUCTURES EMPLOYING EMBEDDED CONDUCTORS
32
Patent #:
Issue Dt:
02/06/1996
Application #:
08106157
Filing Dt:
08/12/1993
Title:
FLEXIBLE PREFORMED PLANAR STRUCTURES FOR INTERPOSING BETWEEN A CHIP AND A SUBSTRATE
33
Patent #:
Issue Dt:
11/10/1998
Application #:
08111765
Filing Dt:
08/25/1993
Title:
ARTICLES COMPRISING DOPED SEMICONDUCTOR MATERIAL
34
Patent #:
Issue Dt:
07/01/1997
Application #:
08116309
Filing Dt:
09/03/1993
Title:
LOW TEMPERATURE DEPOSITION OF SILICON OXIDES FOR DEVICE FABRICATION
35
Patent #:
Issue Dt:
11/17/1998
Application #:
08118109
Filing Dt:
09/08/1993
Title:
INTEGRATED CIRCUIT WITH GATE CONDUCTOR DEFINED RESISTOR
36
Patent #:
Issue Dt:
11/21/1995
Application #:
08150261
Filing Dt:
11/17/1993
Title:
ACTIVE NEURAL NETWORK CONTROL OF WAFER ATTRIBUTES IN A PLASMA ETCH PROCESS
37
Patent #:
Issue Dt:
11/09/1999
Application #:
08156953
Filing Dt:
11/19/1993
Title:
CONDUCTIVE OXIDE FILMS
38
Patent #:
Issue Dt:
09/28/1999
Application #:
08163967
Filing Dt:
12/08/1993
Title:
SEMICONDUCTOR DEVICE HAVING A HIGH VOLTAGE TERMINATION IMPROVEMENT
39
Patent #:
Issue Dt:
04/25/1995
Application #:
08170102
Filing Dt:
12/20/1993
Title:
LOCATION AND STANDOFF PINS FOR CHIP ON TAPE
40
Patent #:
Issue Dt:
08/01/1995
Application #:
08176600
Filing Dt:
01/03/1994
Title:
METHOD OF FABRICATING GATE STACK HAVING A REDUCED HEIGHT
41
Patent #:
Issue Dt:
07/25/1995
Application #:
08192081
Filing Dt:
02/04/1994
Title:
INTEGRATED CIRCUIT HAVING A COPLANAR SOLDER BALL CONTACT ARRAY
42
Patent #:
Issue Dt:
10/28/1997
Application #:
08192228
Filing Dt:
02/04/1994
Title:
METHOD OF DOPING METAL LAYERS FOR ELECTROMIGRATION RESISTANCE
43
Patent #:
Issue Dt:
05/02/1995
Application #:
08194241
Filing Dt:
02/10/1994
Title:
METHOD AND APPARATUS FOR ISOLATION OF FLUX MATERIALS IN "FLIP-CHIP" MANUFACTURING
44
Patent #:
Issue Dt:
04/03/2001
Application #:
08199910
Filing Dt:
02/22/1994
Title:
SEMI-INSULATED INDIUM PHOSPHIDE BASED COMPOSITIONS
45
Patent #:
Issue Dt:
07/01/1997
Application #:
08203919
Filing Dt:
03/01/1994
Title:
INTEGRATED CIRCUIT PACKAGES WITH DISTINCTIVE COLORATION
46
Patent #:
Issue Dt:
12/10/2002
Application #:
08229616
Filing Dt:
04/19/1994
Title:
OPTIMIZATION PROCESSING FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM USING OPTIMALLY SWITCHED FITNESS IMPROVEMENT ALGORITHMS
47
Patent #:
Issue Dt:
06/22/1999
Application #:
08229624
Filing Dt:
04/19/1994
Title:
CONGESTION BASED COST FACTOR COMPUTING APPARATUS FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
48
Patent #:
Issue Dt:
09/17/1996
Application #:
08229821
Filing Dt:
04/19/1994
Title:
CELL PLACEMENT ALTERATION APPARATUS FOR INTEGRATED CIRCUIT CHIP PHYSICAL DESIGN AUTOMATION SYSTEM
49
Patent #:
Issue Dt:
02/27/1996
Application #:
08229826
Filing Dt:
04/19/1994
Title:
INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM UTILIZING OPTIMIZATION PROCESS DECOMPOSITION AND PARALLEL PROCESSING
50
Patent #:
Issue Dt:
10/28/1997
Application #:
08229949
Filing Dt:
04/19/1994
Title:
OPTIMIZATION PROCESSING FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM USING CHAOTIC FITNESS IMPROVEMENT METHOD
51
Patent #:
Issue Dt:
09/29/1998
Application #:
08229954
Filing Dt:
04/19/1994
Title:
FAIL-SAFE DISTRIBUTIVE PROCESSING METHOD FOR PRODUCING A HIGHEST FITNESS CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP
52
Patent #:
Issue Dt:
12/05/2000
Application #:
08230383
Filing Dt:
04/19/1994
Title:
CELL PLACEMENT REPRESENTATION AND TRANSPOSITION FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
53
Patent #:
Issue Dt:
01/14/1997
Application #:
08233607
Filing Dt:
04/22/1994
Title:
TECHNIQUES FOR FORMING SUPERCONDUCTIVE LINES
54
Patent #:
Issue Dt:
12/24/1996
Application #:
08233791
Filing Dt:
04/22/1994
Title:
APPARATUS AND METHOD FOR LOGIC OPTIMIZATION BY REDUNDANCY ADDITION AND REMOVAL
55
Patent #:
Issue Dt:
05/12/1998
Application #:
08236706
Filing Dt:
05/02/1994
Title:
PROCESS FOR FABRICATING A DEVICE
56
Patent #:
Issue Dt:
10/17/1995
Application #:
08242246
Filing Dt:
05/13/1994
Title:
GATE ARRAY LAYOUT TO ACCOMMODATE MULTI ANGLE ION IMPLANTATION
57
Patent #:
Issue Dt:
08/15/1995
Application #:
08251058
Filing Dt:
05/31/1994
Title:
METHOD OF LAYING OUT BOND PADS ON A SEMICONDUCTOR DIE
58
Patent #:
Issue Dt:
02/20/1996
Application #:
08252231
Filing Dt:
06/01/1994
Title:
SPECIFICATION AND DESIGN OF COMPLEX DIGITAL SYSTEMS
59
Patent #:
Issue Dt:
04/30/1996
Application #:
08254218
Filing Dt:
06/06/1994
Title:
METHOD AND APPARATUS FOR DETERMINING THE REACHABLE STATES IN A HYBRID MODEL STATE MACHINE
60
Patent #:
Issue Dt:
08/13/2002
Application #:
08259575
Filing Dt:
06/14/1994
Title:
METHOD OF FORMING SOURCE AND DRAIN REGIONS FOR CMOS DEVICES
61
Patent #:
Issue Dt:
11/21/1995
Application #:
08260078
Filing Dt:
06/15/1994
Title:
PROCESS FOR INTERCONNECTING CONDUCTIVE SUBSTRATES USING AN INTERPOSER HAVING CONDUCTIVE PLASTIC FILLED VIAS
62
Patent #:
Issue Dt:
04/22/1997
Application #:
08267109
Filing Dt:
06/27/1994
Title:
METHOD AND APPARATUS FOR GENERATING CONFORMANCE TEST DATA SEQUENCES
63
Patent #:
Issue Dt:
10/22/1996
Application #:
08268920
Filing Dt:
06/29/1994
Title:
MODELING AND ESTIMATING CROSSTALK NOISE AND DETECTING FALSE LOGIC
64
Patent #:
Issue Dt:
07/16/1996
Application #:
08269230
Filing Dt:
06/30/1994
Title:
APPARATUS AND METHOD FOR ANALYZING CIRCUITS
65
Patent #:
Issue Dt:
01/09/1996
Application #:
08277344
Filing Dt:
07/19/1994
Title:
INTEGRATED CIRCUIT WITH ON-CHIP GROUND PLANE
66
Patent #:
Issue Dt:
11/25/1997
Application #:
08277852
Filing Dt:
07/20/1994
Title:
PROCESS FOR CONTROLLED DEPROTECTION OF POLYMERS AND A PROCESS FOR FABRICATING A DEVICE UTILIZING PARTIALLY DEPROTECTED RESIST POLYMERS
67
Patent #:
Issue Dt:
03/06/2001
Application #:
08278688
Filing Dt:
07/21/1994
Title:
METHOD COMPRISING REMOVAL OF MATERIAL FROM A DIAMOND FILM
68
Patent #:
Issue Dt:
06/25/1996
Application #:
08280429
Filing Dt:
07/26/1994
Title:
METHOD OF PREPARING SILICON WAFERS
69
Patent #:
Issue Dt:
12/12/1995
Application #:
08283296
Filing Dt:
07/29/1994
Title:
UNIFORM AND REPEATABLE PLASMA PROCESSING
70
Patent #:
Issue Dt:
12/05/1995
Application #:
08286606
Filing Dt:
08/05/1994
Title:
METHOD OF ETCHING SILICON NITRIDE
71
Patent #:
Issue Dt:
06/02/1998
Application #:
08287128
Filing Dt:
08/08/1994
Title:
ELECTRONIC CAMERA WITH BINARY LENS ELEMENT ARRAY
72
Patent #:
Issue Dt:
05/21/1996
Application #:
08287204
Filing Dt:
08/08/1994
Title:
COLOR ELECTRONIC CAMERA INCLUDING PHOTOSENSOR ARRAY HAVING BINARY DIFFRACTIVE LENS ELEMENTS
73
Patent #:
Issue Dt:
01/23/1996
Application #:
08287653
Filing Dt:
08/09/1994
Title:
PROCESS MONITOR FOR CMOS INTEGRATED CIRCUITS
74
Patent #:
Issue Dt:
03/19/1996
Application #:
08287989
Filing Dt:
08/09/1994
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING DIFFUSION CONTROL
75
Patent #:
Issue Dt:
07/11/1995
Application #:
08294076
Filing Dt:
08/22/1994
Title:
IMAGE-SENSING DISPLAY PANELS WITH LCD DISPLAY PANEL AND PHOTOSENSOR ARRAY
76
Patent #:
Issue Dt:
03/25/1997
Application #:
08294973
Filing Dt:
08/24/1994
Title:
HIGH-SPEED INTERNAL INTERCONNECTION TECHNIQUE FOR INTEGRATED CIRCUITS THAT REDUCES THE NUMBER OF SIGNAL LINES THROUGH MULTIPLEXING
77
Patent #:
Issue Dt:
06/10/1997
Application #:
08295094
Filing Dt:
08/24/1994
Title:
SEPARABLE CELLS HAVING WIRING CHANNELS FOR ROUTING SIGNALS BETWEEN SURROUNDING CELLS
78
Patent #:
Issue Dt:
10/24/1995
Application #:
08295303
Filing Dt:
08/24/1994
Title:
ARTICLE COMPRISING A BIPOLAR TRANSISTOR WITH FLOATING BASE
79
Patent #:
Issue Dt:
11/14/1995
Application #:
08299209
Filing Dt:
08/31/1994
Title:
FIXTURE FOR ATTACHING MULTIPLE LIDS TO MULTI-CHIP MODULE (MCM) INTEGRATED CIRCUIT
80
Patent #:
Issue Dt:
04/02/1996
Application #:
08299470
Filing Dt:
08/31/1994
Title:
SPACED-GATE EMISSION DEVICE AND METHOD FOR MAKING SAME
81
Patent #:
Issue Dt:
04/23/1996
Application #:
08299701
Filing Dt:
08/31/1994
Title:
ELECTROCHEMICAL GENERATION OF SILANE
82
Patent #:
Issue Dt:
12/24/1996
Application #:
08301687
Filing Dt:
09/07/1994
Title:
METHOD FOR ESTIMATING ROUTABILITY AND CONGESTION IN A CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP
83
Patent #:
Issue Dt:
05/06/1997
Application #:
08302598
Filing Dt:
10/31/1994
Title:
INTEGRATED CIRCUIT TEST RETICLE AND ALIGNMENT MARK OPTIMIZATION METHOD
84
Patent #:
Issue Dt:
10/15/1996
Application #:
08306088
Filing Dt:
09/14/1994
Title:
METHOD FOR IDENTIFYING UNTESTABLE FAULTS IN LOGIC CIRCUITS
85
Patent #:
Issue Dt:
04/08/1997
Application #:
08306182
Filing Dt:
09/13/1994
Title:
METHOD OF CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP COMPRISING CHAOTIC PLACEMENT AND CELL OVERLAP REMOVAL
86
Patent #:
Issue Dt:
06/10/1997
Application #:
08306189
Filing Dt:
09/13/1994
Title:
OPTIMAL PAD LOCATION METHOD FOR MICROELECTRONIC CIRCUIT CELL PLACEMENT
87
Patent #:
Issue Dt:
10/22/1996
Application #:
08306385
Filing Dt:
09/13/1994
Title:
METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
88
Patent #:
Issue Dt:
09/03/1996
Application #:
08307942
Filing Dt:
09/16/1994
Title:
METHOD FOR DESIGNING LOW PROFILE VARIABLE WIDTH INPUT/OUTPUT CELLS
89
Patent #:
Issue Dt:
08/27/1996
Application #:
08316745
Filing Dt:
10/03/1994
Title:
INSPECTION APPARATUS AND METHOD
90
Patent #:
Issue Dt:
10/28/1997
Application #:
08318275
Filing Dt:
10/05/1994
Title:
CELL PLACEMENT METHOD FOR MICROELECTRONIC INTEGRATED CIRCUIT COMBINING CLUSTERING, CLUSTER PLACEMENT AND DE-CLUSTERING
91
Patent #:
Issue Dt:
03/19/1996
Application #:
08321362
Filing Dt:
10/11/1994
Title:
MASKS WITH LOW STRESS MULTILAYER FILMS AND A PROCESS FOR CONTROLLING THE STRESS OF MULTILAYER FILMS
92
Patent #:
Issue Dt:
10/07/1997
Application #:
08323817
Filing Dt:
10/17/1994
Title:
METHOD FOR MOUNTING A MICROELECTRONIC CIRCUIT PERIPHERALLY-LEADED PACKAGE INCLUDING INTEGRAL SUPPORT MEMBER WITH SPACER
93
Patent #:
Issue Dt:
07/30/1996
Application #:
08323945
Filing Dt:
10/17/1994
Title:
IMAGING ACTIVE PIXEL DEVICE HAVING A NON-DESTRUCTIVE READ-OUT GATE
94
Patent #:
Issue Dt:
02/25/2003
Application #:
08324842
Filing Dt:
10/18/1994
Title:
PROCESS FOR THE ELECTROLESS DEPOSITION OF METAL ON A SUBSTRATE
95
Patent #:
Issue Dt:
04/23/1996
Application #:
08326444
Filing Dt:
10/20/1994
Title:
DEVICE FABRICATION USING DUV/EUV PATTERN DELINEATION
96
Patent #:
Issue Dt:
05/28/1996
Application #:
08326449
Filing Dt:
10/20/1994
Title:
PATTERN DELINEATING APPARATUS FOR USE IN THE EUV SPECTRUM
97
Patent #:
Issue Dt:
02/25/1997
Application #:
08327338
Filing Dt:
10/21/1994
Title:
DELAY TESTING OF HIGH-PERFORMANCE DIGITAL COMPONENTS BY A SLOW-SPEED TESTER
98
Patent #:
Issue Dt:
11/27/2001
Application #:
08329806
Filing Dt:
10/26/1994
Title:
TUNGSTEN FORMATION PROCESS
99
Patent #:
Issue Dt:
07/16/1996
Application #:
08331251
Filing Dt:
10/28/1994
Title:
ENCAPSULATION OF ELECTRONIC COMPONENTS
100
Patent #:
Issue Dt:
06/10/1997
Application #:
08331458
Filing Dt:
10/31/1994
Title:
FIELD EMISSION DEVICES EMPLOYING ENHANCED DIAMOND FIELD EMITTERS
Assignors
1
Exec Dt:
01/24/2018
2
Exec Dt:
01/24/2018
3
Exec Dt:
01/24/2018
Assignee
1
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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