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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09602797
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Filing Dt:
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06/23/2000
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Title:
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SEMICONDUCTOR WAFER HAVING A LAYER-TO-LAYER ALIGNMENT MARK
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09603340
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Filing Dt:
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06/26/2000
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Title:
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ADDITIONAL ETCHING TO DECREASE POLISHING TIME FOR SHALLOW-TRENCH ISOLATION IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09603717
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Filing Dt:
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06/27/2000
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Title:
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METHOD OF TESTING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09604020
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Filing Dt:
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06/26/2000
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Title:
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METHOD FOR REGULAR DETECTION OF PHOSPHORUS STRIATIONS IN A MULT-LAYERED FILM STACK
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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09604519
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Filing Dt:
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06/27/2000
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Title:
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INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09604865
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Filing Dt:
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06/28/2000
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Title:
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LASER FAULT CORRECTION OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09605380
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Filing Dt:
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06/27/2000
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Title:
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COMPOSITE LOW DIELECTRIC CONSTANT FILM FOR INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09605382
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Filing Dt:
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06/27/2000
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Title:
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Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation of the low dielectric constant dielectric film with hydrogen ions
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Patent #:
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Issue Dt:
|
06/11/2002
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Application #:
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09605507
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Filing Dt:
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06/28/2000
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Title:
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Process for fabricating organic semiconductor device involving selective patterning
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09606833
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Filing Dt:
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06/29/2000
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Title:
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Technique for reducing dishing in Cu-based interconnects
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09607169
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Filing Dt:
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06/29/2000
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Title:
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APPARATUS AND METHOD FOR PLANARIZING THE SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09607177
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Filing Dt:
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06/29/2000
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Title:
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APPARATUS AND METHOD FOR LINEARLY PLANARIZING A SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09607511
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Filing Dt:
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06/28/2000
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Title:
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Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09607512
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Filing Dt:
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06/28/2000
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Title:
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PROCESS FOR FORMING TRENCHES AND VIAS IN LAYERS OF LOW DIELECTRIC CONSTANT CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL OF AN INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09609527
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Filing Dt:
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07/03/2000
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Title:
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SYSTEM TO IMPROVE SER IMMUNITY AND PUNCHTHROUGH
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09609582
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Filing Dt:
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06/30/2000
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Title:
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FLIP CHIP SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09611581
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Filing Dt:
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07/07/2000
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Title:
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TECHNIQUE FOR REDUCING SLIVERS ON OPTICAL COMPONENTS RESULTING FROM FRICTION PROCESSES
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09611844
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Filing Dt:
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07/07/2000
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Title:
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OXIDE ETCH
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09611907
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Filing Dt:
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07/07/2000
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Title:
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SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR STRUCTURE WITH TRENCH INCLUDING A CONDUCTIVE LAYER
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09612867
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Filing Dt:
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07/10/2000
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Title:
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METHOD OF PLANARIZING DIE SOLDER BALLS BY EMPLOYING A DIE'S WEIGHT
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09614854
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Filing Dt:
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07/12/2000
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Title:
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Technique for reducing dambar burrs
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09614992
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Filing Dt:
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07/12/2000
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Title:
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THIN FILM RESISTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09617550
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Filing Dt:
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07/17/2000
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Title:
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LOW VIA RESISTANCE SYSTEM
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09617687
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Filing Dt:
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07/17/2000
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH MONOLITHICALLY FORMED RESISTOR-CAPACITOR PORTION
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09618211
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Filing Dt:
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07/10/2000
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Title:
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POLYMERIC DIELECTRIC LAYERS HAVING LOW DIELECTRIC CONSTANTS AND IMPROVED ADHESION TO METAL LINES
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09620939
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Filing Dt:
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07/21/2000
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Title:
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INTEGRATED CIRCUIT PACKAGE HAVING PARTIALLLY EXPOSED CONDUCTIVE LAYER
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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09621110
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Filing Dt:
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07/21/2000
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Title:
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METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09626037
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Filing Dt:
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07/27/2000
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Title:
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METHOD AND APPARATUS FOR LOCATING CONSTANTS IN COMBINATIONAL CIRCUITS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09628067
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Filing Dt:
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07/28/2000
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Title:
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INTEGRATED CIRCUIT PACKAGE
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09630463
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Filing Dt:
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08/02/2000
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Title:
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HIGH SPEED LOW VOLTAGE SEMICONDUCTOR DEVICES METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09631150
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Filing Dt:
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08/02/2000
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Title:
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Vacuum-assisted integrated circuit test socket
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09631545
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Filing Dt:
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08/03/2000
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Title:
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METHOD OF FOCUSED ION BEAM PATTERN TRANSFER USING A SMART DYNAMIC TEMPLATE
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09631546
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Filing Dt:
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08/03/2000
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Title:
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DEVICE AND METHOD FOR FORMING SEMICONDUCTOR INTERCONNECTIONS IN AN INTEGRATED CIRCUIT SUBSTRATE
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09631755
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Filing Dt:
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08/03/2000
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Title:
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BIPOLAR TRANISTOR HAVING A LOW K MATERIAL IN THE EMITTER REGION
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09631862
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Filing Dt:
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08/03/2000
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Title:
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SUBSTRATE ISOLATION FOR ANALOG/DIGITAL IC CHIPS
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09632445
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Filing Dt:
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08/04/2000
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Title:
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TWO PHASE CHEMICAL/MECHANICAL POLISHING PROCESS FOR TUNGSTEN LAYERS
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09633241
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Filing Dt:
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08/07/2000
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Title:
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SILICON CARBIDE BARRIER LAYERS FOR POROUS LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09633795
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Filing Dt:
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08/07/2000
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Title:
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BOUNDARY SCAN CHAIN ROUTING
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09634021
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Filing Dt:
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08/08/2000
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Title:
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MITIGATION OF DELETERIOUS EFFECTS OF MICROPIPES IN SILICON CARBIDE DEVICES
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09634401
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Filing Dt:
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08/09/2000
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Title:
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NOVEL PROCESS FOR GATE OXIDE SIDE-WALL PROTECTION FROM PLASMA DAMAGE TO FORM HIGHLY RELIABLE GATE DIELECTRICS
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09636447
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Filing Dt:
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08/11/2000
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Title:
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METHOD FOR MAKING A MERGED CONTACT WINDOW IN A TRANSISTOR TO ELECTRICALLY CONNECT THE GATE TO EITHER THE SOURCE OR THE DRAIN
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09636498
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Filing Dt:
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08/11/2000
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Title:
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METHOD OF RAPID WAFER BUMPING
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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09637496
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Filing Dt:
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08/11/2000
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Title:
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BIPOLAR TRANSISTOR HAVING AN ISOLATION STRUCTURE LOCATED UNDER THE BASE, EMITTER AND COLLECTOR AND A METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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09639288
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Filing Dt:
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08/15/2000
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Title:
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INTEGRATED CIRCUIT DIE FOR WIRE BONDING AND FLIP-CHIP MOUNTING
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09639440
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Filing Dt:
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08/15/2000
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Title:
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STATISTICAL DECISION SYSTEM
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09639449
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Filing Dt:
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08/15/2000
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Title:
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CLEANLINESS VERIFICATION SYSTEM
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09640329
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Filing Dt:
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08/16/2000
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Title:
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Hydrogenated silicon carbide as a liner for self-aligning contact vias
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09641086
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Filing Dt:
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08/17/2000
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Title:
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USE OF SELECTIVE OXIDATION TO IMPROVE LDMOS POWER TRANSISTORS
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09641160
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Filing Dt:
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08/17/2000
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Title:
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PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A METAL OXIDE OR A METAL SILICATE GATE DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09641661
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Filing Dt:
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08/18/2000
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Title:
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TEST LIMITS BASED ON POSITION
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09641899
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Filing Dt:
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08/18/2000
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Title:
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INTEGRATED CIRCUIT PACKAGE WITH IMPROVED ESD PROTECTION FOR NO-CONNECT PINS
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09642216
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Filing Dt:
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08/18/2000
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Title:
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Oxide-bondable solder
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09642376
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Filing Dt:
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08/21/2000
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Title:
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MODULAR SEMICONDUCTOR SUBSTRATES
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09643784
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Filing Dt:
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08/22/2000
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Title:
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Method of making article comprising vertically nano-interconnected circuit devices and method for making the same
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09648015
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Filing Dt:
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08/25/2000
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Title:
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Acoustic time of flight and acoustic resonance methods for detecting endpoint in plasma processes
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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09648164
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Filing Dt:
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08/25/2000
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Title:
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ARCHITECTURE FOR CIRCUIT CONNECTION OF A VERTICAL TRANSISTOR
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09650038
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Filing Dt:
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08/29/2000
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Title:
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PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES IN WHICH THE DISTRIBUTION OF DOPANTS IS CONTROLLED
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09650164
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Filing Dt:
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08/29/2000
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Title:
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RESIDUAL OXYGEN REDUCTION SYSTEM
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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09650604
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Filing Dt:
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08/30/2000
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Title:
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FIELD PLATED RESISTOR WITH ENHANCED ROUTING AREA THEREOVER
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09650606
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Filing Dt:
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08/30/2000
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Title:
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METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09651308
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Filing Dt:
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08/30/2000
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Title:
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THIN FORM FACTOR FLIP CHIP BALL GRID ARRAY
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09651447
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Filing Dt:
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08/30/2000
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Title:
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METHOD FOR MAKING AN INTEGRATED CIRCUIT DEVICE INCLUDING A GRADED, GROWN, HIGH QUALITY GATE OXIDE LAYER AND A NITRIDE LAYER
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09651661
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Filing Dt:
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08/29/2000
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Title:
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USE OF SMALL OPENINGS IN LARGE TOPOGRAPHY FEATURES TO IMPROVE DIELECTRIC THICKNESS CONTROL AND A METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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09651696
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Filing Dt:
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08/30/2000
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Title:
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ON-CHIP VACUUM TUBE DEVICE AND PROCESS FOR MAKING DEVICE
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09652479
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Filing Dt:
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08/31/2000
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Title:
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Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09652571
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Filing Dt:
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08/31/2000
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Title:
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INTEGRATED CIRCUIT INCLUDING ESD CIRCUITS FOR A MULTI-CHIP MODULE AND A METHOD THEREFOR
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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09653295
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Filing Dt:
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08/31/2000
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Title:
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STACKED STRUCTURE FOR PARALLEL CAPACITORS AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09653297
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Filing Dt:
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08/31/2000
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Title:
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LOW K DIELECTRIC INSULATOR AND METHOD OF FORMING SEMICONDUCTOR CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09653364
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Filing Dt:
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08/31/2000
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Title:
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MONITORING SYSTEM FOR DETERMINING PROGRESS IN A FABRICATION ACTIVITY
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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09653531
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Filing Dt:
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08/31/2000
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Title:
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TRANSISTOR DEVICE HAVING AN ISOLATION STRUCTURE LOCATED UNDER A SOURCE REGION, DRAIN REGION AND CHANNEL REGION AND A METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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09653616
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Filing Dt:
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08/31/2000
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Title:
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FIELD PLATED SCHOTTKY DIODE
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09654689
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Filing Dt:
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09/05/2000
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Title:
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INTEGRATED CIRCUIT ISOLATION SYSTEM
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09659090
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Filing Dt:
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09/11/2000
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Title:
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HARDWARE/SOFTWARE CO-SYNTHESIS OF HETEROGENEOUS LOW-POWER AND FAULT-TOLERANT SYSTEMS-ON-A CHIP
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09659668
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Filing Dt:
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09/11/2000
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Title:
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METHOD OF FABRICATING A DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09661465
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Filing Dt:
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09/13/2000
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Title:
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PROCESS FOR PLANARIZATION OF INTEGRATED CIRCUIT STRUCTURE WHICH INHIBITS CRACKING OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL ADJACENT UNDERLYING RAISED STRUCTURES
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09665279
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Filing Dt:
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09/19/2000
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Title:
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APPARATUS AND METHOD FOR RECLAMATION OF USED POLISHING SLURRY
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09665988
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Filing Dt:
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09/20/2000
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Title:
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CONCENTRIC OPTICAL CABLE WITH FULL DUPLEX CONNECTORS
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09666507
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Filing Dt:
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09/20/2000
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Title:
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EXHAUST FLOW CONTROL SYSTEM
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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09667046
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Filing Dt:
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09/21/2000
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Title:
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DUAL DAMASCENE PROCESS WITH NO PASSING METAL FEATURES
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09669278
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Filing Dt:
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09/26/2000
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Title:
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DUAL IN-LINE BGA BALL MOUNTER
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09669979
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Filing Dt:
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09/26/2000
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Title:
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Planarization system
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09670448
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Filing Dt:
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09/26/2000
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Title:
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SHALLOW JUNCTION FORMATION
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09670975
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Filing Dt:
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09/27/2000
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Title:
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TEMPERATURE CONTROL SYSTEM
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09670998
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Filing Dt:
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09/27/2000
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Title:
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PROCESS FOR PLANARIZING AN ISOLATION STRUCTURE IN A SUBSTRATE
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09675109
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Filing Dt:
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09/28/2000
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Title:
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REDUCED SOFT ERROR RATE (SER) CONSTRUCTION FOR INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09677276
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR DETECING EQUIVALENT AND ANTI-EQUIVALENT PINS
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09677475
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR TIMING DRIVEN RESYNTHESIS
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09677940
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR QUICK SEARCH FOR IDENTITIES APPLICABLE TO SPECIFIED FORMULA
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09678201
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Filing Dt:
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10/01/2000
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Title:
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METHOD AND APPARATUS FOR FORMULAE AREA AND DELAY MINIMIZATION
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09678478
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR DYNAMIC BUFFER AND INVERTER TREE OPTIMIZATION
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09678479
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR LOCAL RESYNTHESIS OF LOGIC TREES WITH MULTIPLE COST FUNCTIONS
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09678481
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR OPTIMAL CRITICAL NETLIST AREA SELECTION
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09680759
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Filing Dt:
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10/06/2000
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Title:
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BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09680893
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR ANALYSIS OF TIMING MARGINS AND SIGNAL SKEWS OF RELEVANT LOGIC CELLS USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09684015
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Filing Dt:
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10/06/2000
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Title:
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Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09684770
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR ISOLATING FAULTS FROM MULTIPLE FAILING PATHS IN A CIRCUIT USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09684868
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Filing Dt:
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10/06/2000
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Title:
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DIAGNOSTIC ARCHITECTURE USING FPGA CORE IN SYSTEM ON A CHIP DESIGN
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09685990
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Filing Dt:
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10/10/2000
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Title:
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METHOD AND APPARATUS FOR MINIMIZATION OF NET DELAY BY OPTIMAL BUFFER INSERTION
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09687263
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Filing Dt:
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10/12/2000
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Title:
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INSULATED BONDING WIRE FOR MICROELECTRONIC PACKAGING
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09689030
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Filing Dt:
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10/12/2000
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Title:
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METHOD OF FORMING A HIGH QUALITY GATE OXIDE LAYER HAVING A UNIFORM THICKNESS
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